diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index 97b926dc4eb..d94de12e716 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -802,7 +802,7 @@ registers:
02393393 0x9c7: 02393393
01365365 0x9c8: 01365365
00000000 CP_APERTURE_CNTL_HOST: 0
- 00000000 0xa01: 00000000
+ 00000000 CP_APERTURE_CNTL_SQE: 0
00000000 0xa02: 00000000
00000000 CP_APERTURE_CNTL_CD: 0
00000000 VSC_DBG_ECO_CNTL: 0
@@ -2971,7 +2971,7 @@ indexed-registers:
00000000 0x127: 00000000
00000000 0x128: 00000000
00000000 0x129: 00000000
- 00000101 MARKER: 0x101
+ 00000101 MARKER_TEMP: 0x101
00000004 MODE_BITMASK: 0x4
00000000 0x12c: 00000000
00000000 0x12d: 00000000
diff --git a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
index 3c1f35ed641..93e40c47a3f 100644
--- a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+++ b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
@@ -1017,7 +1017,7 @@ registers:
04355410 0x9c7: 04355410
083474e2 0x9c8: 083474e2
00000000 CP_APERTURE_CNTL_HOST: 0
- 00000010 0xa01: 00000010
+ 00000010 CP_APERTURE_CNTL_SQE: 0x10
00000000 0xa02: 00000000
00000000 CP_APERTURE_CNTL_CD: 0
00000000 VSC_DBG_ECO_CNTL: 0
@@ -14420,7 +14420,7 @@ indexed-registers:
00000000 0x127: 00000000
00000000 0x128: 00000000
00000000 0x129: 00000000
- 81000301 MARKER: 0x81000301
+ 81000301 MARKER_TEMP: 0x81000301
00000004 MODE_BITMASK: 0x4
00000000 0x12c: 00000000
00000000 0x12d: 00000000
diff --git a/src/freedreno/.gitlab-ci/reference/prefetch-test.log b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
index 73d4e8d8f04..8cf6c3b7189 100644
--- a/src/freedreno/.gitlab-ci/reference/prefetch-test.log
+++ b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
@@ -1596,7 +1596,7 @@ registers:
02451451 0x9c7: 02451451
023c33c3 0x9c8: 023c33c3
00000000 CP_APERTURE_CNTL_HOST: 0
- 00000010 0xa01: 00000010
+ 00000010 CP_APERTURE_CNTL_SQE: 0x10
00000000 0xa02: 00000000
00000000 CP_APERTURE_CNTL_CD: 0
00000000 VSC_DBG_ECO_CNTL: 0
@@ -148637,7 +148637,7 @@ indexed-registers:
00000000 0x127: 00000000
00000000 0x128: 00000000
00000000 0x129: 00000000
- ffff0301 MARKER: 0xffff0301
+ ffff0301 MARKER_TEMP: 0xffff0301
00000004 MODE_BITMASK: 0x4
00000000 0x12c: 00000000
00000000 0x12d: 00000000
diff --git a/src/freedreno/afuc/emu-regs.c b/src/freedreno/afuc/emu-regs.c
index 56f718d9ac1..e6a0dd359f8 100644
--- a/src/freedreno/afuc/emu-regs.c
+++ b/src/freedreno/afuc/emu-regs.c
@@ -192,18 +192,18 @@ emu_get_fifo_reg(struct emu *emu, unsigned n, bool peek)
/* $memdata */
EMU_CONTROL_REG(MEM_READ_DWORDS);
EMU_CONTROL_REG(MEM_READ_ADDR);
- EMU_CONTROL_REG(MEM_READ_ADDR_HI_PRIVILEGED);
+ EMU_CONTROL_REG(MEM_READ_ADDR_HI_PREEMPTION);
unsigned read_dwords = emu_get_reg32(emu, &MEM_READ_DWORDS);
uintptr_t read_addr = emu_get_reg64(emu, &MEM_READ_ADDR);
uintptr_t read_addr_hi = 0;
if (emu->fw_id == AFUC_A750)
- read_addr_hi = emu_get_reg64(emu, &MEM_READ_ADDR_HI_PRIVILEGED);
+ read_addr_hi = emu_get_reg64(emu, &MEM_READ_ADDR_HI_PREEMPTION);
/* We don't model privileged vs. non-privileged accesses here, so just
* use the right address.
*
- * TODO: all uses of MEM_READ_ADDR_HI_PRIVILEGED set bit 31, is this the
+ * TODO: all uses of MEM_READ_ADDR_HI_PREEMPTION set bit 31, is this the
* right bit or do we need to track writes to it?
*/
if (read_addr_hi & (1u << 31)) {
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index d49919f6344..81ba0bce65b 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2465,6 +2465,7 @@ to upconvert to 32b float internally?
+
diff --git a/src/freedreno/registers/adreno/adreno_control_regs.xml b/src/freedreno/registers/adreno/adreno_control_regs.xml
index 7a3af94fae0..56fba89ec1b 100644
--- a/src/freedreno/registers/adreno/adreno_control_regs.xml
+++ b/src/freedreno/registers/adreno/adreno_control_regs.xml
@@ -153,6 +153,19 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
Controls high 32 bits used by load and store afuc instructions
+
+ Used for testing whether register protection does not allow a
+ read. To use this register, write the register address to $usraddr
+ with bit 20 or'd in and then write the register count to $data. Then
+ the results of the test will be available in this register when
+ bit 0 is set.
+
+
+
+ Whether there was a register protection violation.
+
+
+
@@ -217,6 +230,17 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+
+ This is a mirror of PC_MARKER. At preemption time, it's used to
+ read the data written by CP_SET_MARKER to see what state the GPU
+ is in. Because PC_MARKER is "just" a normal GPU register, writes
+ to it are pipelined, so reading this gives the firmware the
+ state the GPU is in when preempted, rather than the SQE which
+ may be well ahead of the GPU. This is used e.g. to determine
+ whether to save/restore GMEM.
+
+
+
@@ -364,6 +403,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+
+
These registers seem to define a range that load/store instructions can access
@@ -376,6 +417,24 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+ Replaces CP_APERTURE_CNTL_SQE on a7xx. Uses same format as CP_APERTURE_CNTL_HOST.
+
+
+ Aperture control used specially for preemption save and restore.
+ Has extra fields compared to @APERTURE_CNTL.
+
+
+
+ When this is set this seems to redirect register writes
+ to a special register space for triggering preemption
+ save/restore actions.
+
+
+
+
+
+
+
@@ -410,19 +469,25 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+
+
+
+
-
+
+
+
@@ -437,6 +502,13 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+
+
+ Whether there was a register protection violation.
+
+
+
+
@@ -468,6 +540,14 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+
+
+
+
+
+
+
+