From e05aec3fcd86613abcb7b0618f1b5f49b8ce0f4e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 15 Apr 2024 02:27:52 -0400 Subject: [PATCH] ac/gpu_info: set tcc_rb_non_coherent only if number of TCCs != number of RBs This sets it to false for Navi31 to eliminate unnecessary L2 cache invalidations. Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_gpu_info.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index ff16585ab80..04e8314d561 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -1101,7 +1101,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info, info->num_tcc_blocks = info->max_tcc_blocks; } - info->tcc_rb_non_coherent = !util_is_power_of_two_or_zero(info->num_tcc_blocks); + info->tcc_rb_non_coherent = !util_is_power_of_two_or_zero(info->num_tcc_blocks) && + info->num_rb != info->num_tcc_blocks; if (info->drm_minor >= 52) { info->sqc_inst_cache_size = device_info.sqc_inst_cache_size * 1024;