From e05ad2680c7cec7fadb51a49b177ea4f78a7e400 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 30 Aug 2021 01:28:52 -0400 Subject: [PATCH] radeonsi: set gfx10 registers better in si_emit_initial_compute_regs Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 37dc9cd0cb5..ad961529fd4 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -423,11 +423,13 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf } if (sctx->chip_class >= GFX10) { - radeon_set_sh_reg(cs, R_00B890_COMPUTE_USER_ACCUM_0, 0); - radeon_set_sh_reg(cs, R_00B894_COMPUTE_USER_ACCUM_1, 0); - radeon_set_sh_reg(cs, R_00B898_COMPUTE_USER_ACCUM_2, 0); - radeon_set_sh_reg(cs, R_00B89C_COMPUTE_USER_ACCUM_3, 0); - radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, 0); + radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 5); + radeon_emit(cs, 0); /* R_00B890_COMPUTE_USER_ACCUM_0 */ + radeon_emit(cs, 0); /* R_00B894_COMPUTE_USER_ACCUM_1 */ + radeon_emit(cs, 0); /* R_00B898_COMPUTE_USER_ACCUM_2 */ + radeon_emit(cs, 0); /* R_00B89C_COMPUTE_USER_ACCUM_3 */ + radeon_emit(cs, 0); /* R_00B8A0_COMPUTE_PGM_RSRC3 */ + radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0); } radeon_end();