diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c b/src/gallium/drivers/etnaviv/etnaviv_context.c index 8c9e9cdc576..0373fcc7bae 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_context.c +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c @@ -187,7 +187,7 @@ etna_get_fs(struct etna_context *ctx, struct etna_shader_key* const key) const struct etna_shader_variant *old = ctx->shader.fs; /* update the key if we need to run nir_lower_sample_tex_compare(..). */ - if (ctx->screen->specs.halti < 2 && + if (ctx->screen->info->halti < 2 && (ctx->dirty & (ETNA_DIRTY_SAMPLERS | ETNA_DIRTY_SAMPLER_VIEWS))) { for (unsigned int i = 0; i < ctx->num_fragment_sampler_views; i++) { @@ -399,7 +399,7 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info, } } - if (screen->specs.halti >= 2) { + if (screen->info->halti >= 2) { /* On HALTI2+ (GC3000 and higher) only use instanced drawing commands, as the blob does */ etna_draw_instanced(ctx->stream, info->index_size, draw_mode, info->instance_count, draws[0].count, info->index_size ? draws->index_bias : draws[0].start); @@ -456,21 +456,21 @@ etna_reset_gpu_state(struct etna_context *ctx) etna_set_state(stream, VIVS_PS_CONTROL_EXT, 0x00000000); /* There is no HALTI0 specific state */ - if (screen->specs.halti >= 1) { /* Only on HALTI1+ */ + if (screen->info->halti >= 1) { /* Only on HALTI1+ */ etna_set_state(stream, VIVS_VS_HALTI1_UNK00884, 0x00000808); } - if (screen->specs.halti >= 2) { /* Only on HALTI2+ */ + if (screen->info->halti >= 2) { /* Only on HALTI2+ */ etna_set_state(stream, VIVS_RA_UNK00E0C, 0x00000000); } - if (screen->specs.halti >= 3) { /* Only on HALTI3+ */ + if (screen->info->halti >= 3) { /* Only on HALTI3+ */ etna_set_state(stream, VIVS_PS_HALTI3_UNK0103C, 0x76543210); } - if (screen->specs.halti >= 4) { /* Only on HALTI4+ */ + if (screen->info->halti >= 4) { /* Only on HALTI4+ */ etna_set_state(stream, VIVS_PS_MSAA_CONFIG, 0x6fffffff & 0xf70fffff & 0xfff6ffff & 0xffff6fff & 0xfffff6ff & 0xffffff7f); etna_set_state(stream, VIVS_PE_HALTI4_UNK014C0, 0x00000000); } - if (screen->specs.halti >= 5) { /* Only on HALTI5+ */ + if (screen->info->halti >= 5) { /* Only on HALTI5+ */ etna_set_state(stream, VIVS_NTE_DESCRIPTOR_UNK14C40, 0x00000001); etna_set_state(stream, VIVS_FE_HALTI5_UNK007D8, 0x00000002); etna_set_state(stream, VIVS_PS_SAMPLER_BASE, 0x00000000); @@ -489,7 +489,7 @@ etna_reset_gpu_state(struct etna_context *ctx) etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, COND(screen->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE)); } - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { /* TXDESC cache flush - do this once at the beginning, as texture * descriptors are only written by the CPU once, then patched by the kernel * before command stream submission. It does not need flushing if the @@ -513,12 +513,12 @@ etna_reset_gpu_state(struct etna_context *ctx) * all attributes seems to provide the GPU with the required edge to actually * disable the unused attributes on the next draw. */ - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0), VIVS_NFE_GENERIC_ATTRIB__LEN, dummy_attribs); } else { etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0), - screen->specs.halti >= 0 ? 16 : 12, dummy_attribs); + screen->info->halti >= 0 ? 16 : 12, dummy_attribs); } etna_cmd_stream_mark_end_of_context_init(stream); diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c index 9e098f1563b..a95a2ff5579 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -262,7 +262,7 @@ etna_emit_state(struct etna_context *ctx) * a) the number of vertex elements written matters: so write only active ones * b) the vertex element states must all be written: do not skip entries that stay the same */ if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) { - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0), ctx->vertex_elements->num_elements, ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG0); @@ -277,7 +277,7 @@ etna_emit_state(struct etna_context *ctx) /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0), ctx->vertex_elements->num_elements, ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG); - if (screen->specs.halti >= 2) { + if (screen->info->halti >= 2) { /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0), ctx->vertex_elements->num_elements, ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE); @@ -331,7 +331,7 @@ etna_emit_state(struct etna_context *ctx) /*00674*/ EMIT_STATE(FE_PRIMITIVE_RESTART_INDEX, ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX); } if (likely(dirty & (ETNA_DIRTY_VERTEX_BUFFERS))) { - if (screen->specs.halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */ + if (screen->info->halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */ for (int x = 0; x < ctx->vertex_buffer.count; ++x) { /*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR); } @@ -347,7 +347,7 @@ etna_emit_state(struct etna_context *ctx) if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) { for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) { if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) { - if (screen->specs.halti >= 2) + if (screen->info->halti >= 2) /*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]); else if (screen->specs.stream_count > 1) /*006A0*/ EMIT_STATE(FE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]); @@ -355,7 +355,7 @@ etna_emit_state(struct etna_context *ctx) /*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[0]); } } - if (screen->specs.halti >= 2) { + if (screen->info->halti >= 2) { for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) { /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_VERTEX_DIVISOR(x), ctx->vertex_elements->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[x]); } @@ -447,7 +447,7 @@ etna_emit_state(struct etna_context *ctx) if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE); - if (screen->specs.halti < 0 || screen->info->model == 0x880) { + if (screen->info->halti < 0 || screen->info->model == 0x880) { /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR); } @@ -484,7 +484,7 @@ etna_emit_state(struct etna_context *ctx) /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val); } if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) { - if (screen->specs.halti >= 0 && screen->info->model != 0x880) { + if (screen->info->halti >= 0 && screen->info->model != 0x880) { /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE); /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL); /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]); @@ -525,7 +525,7 @@ etna_emit_state(struct etna_context *ctx) if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) { /*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]); } - if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && screen->specs.halti >= 3) + if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && screen->info->halti >= 3) /*014BC*/ EMIT_STATE(PE_MEM_CONFIG, ctx->framebuffer.PE_MEM_CONFIG); if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) { /*01654*/ EMIT_STATE(TS_MEM_CONFIG, ctx->framebuffer.TS_MEM_CONFIG); @@ -544,7 +544,7 @@ etna_emit_state(struct etna_context *ctx) /* end only EMIT_STATE */ /* Emit strongly architecture-specific state */ - if (screen->specs.halti >= 5) + if (screen->info->halti >= 5) emit_halti5_only_state(ctx, vs_output_count); else emit_pre_halti5_state(ctx); @@ -554,7 +554,7 @@ etna_emit_state(struct etna_context *ctx) * before loading the new states to avoid corrupting the state of the * in-flight draw. */ - if (screen->specs.halti >= 0 && + if (screen->info->halti >= 0 && (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF | ETNA_DIRTY_SAMPLERS | ETNA_DIRTY_SAMPLER_VIEWS))) etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); @@ -575,7 +575,7 @@ etna_emit_state(struct etna_context *ctx) ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF; /**** Large dynamically-sized state ****/ - bool do_uniform_flush = screen->specs.halti < 5; + bool do_uniform_flush = screen->info->halti < 5; if (dirty & (ETNA_DIRTY_SHADER)) { /* Special case: a new shader was loaded; simply re-load all uniforms and * shader code at once */ @@ -587,7 +587,7 @@ etna_emit_state(struct etna_context *ctx) state can legitimately be programmed multiple times. */ - if (screen->specs.halti >= 5) { /* ICACHE (HALTI5) */ + if (screen->info->halti >= 5) { /* ICACHE (HALTI5) */ assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo); /* Set icache (VS) */ etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0); @@ -661,7 +661,7 @@ etna_emit_state(struct etna_context *ctx) etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb); - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { /* HALTI5 needs to be prompted to pre-fetch shaders */ etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000); etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000); diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h index 83d8a28cfce..aa9bfc35aa6 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_internal.h +++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h @@ -63,8 +63,6 @@ /* GPU chip 3D specs */ struct etna_specs { - /* HALTI (gross architecture) level. -1 for pre-HALTI. */ - int halti : 8; /* supports SUPERTILE (64x64) tiling? */ unsigned can_supertile : 1; /* needs z=(z+w)/2, for older GCxxx */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c b/src/gallium/drivers/etnaviv/etnaviv_rs.c index 97d6b99adf6..ce4c6a453cd 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_rs.c +++ b/src/gallium/drivers/etnaviv/etnaviv_rs.c @@ -295,7 +295,7 @@ etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf, format = RS_FORMAT_A8R8G8B8; break; case 64: - assert(screen->specs.halti >= 2); + assert(screen->info->halti >= 2); format = RS_FORMAT_64BPP_CLEAR; break; default: diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 39ff42e5573..07d53fb7567 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -230,9 +230,9 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_2D_SIZE: return screen->specs.max_texture_size; case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* TODO: verify */ - return screen->specs.halti >= 0 ? screen->specs.max_texture_size : 0; + return screen->info->halti >= 0 ? screen->specs.max_texture_size : 0; case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: - if (screen->specs.halti < 0) + if (screen->info->halti < 0) return 0; FALLTHROUGH; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: @@ -357,7 +357,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_cap param) { struct etna_screen *screen = etna_screen(pscreen); - bool ubo_enable = screen->specs.halti >= 2; + bool ubo_enable = screen->info->halti >= 2; if (DBG_ENABLED(ETNA_DBG_DEQP)) ubo_enable = true; @@ -416,7 +416,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: return 0; case PIPE_SHADER_CAP_INTEGERS: - return screen->specs.halti >= 2; + return screen->info->halti >= 2; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return shader == PIPE_SHADER_FRAGMENT @@ -452,7 +452,7 @@ gpu_supports_texture_target(struct etna_screen *screen, return false; /* pre-halti has no array/3D */ - if (screen->specs.halti < 0 && + if (screen->info->halti < 0 && (target == PIPE_TEXTURE_1D_ARRAY || target == PIPE_TEXTURE_2D_ARRAY || target == PIPE_TEXTURE_3D)) @@ -827,7 +827,7 @@ static void etna_determine_sampler_limits(struct etna_screen *screen) { /* vertex and fragment samplers live in one address space */ - if (screen->specs.halti >= 1) { + if (screen->info->halti >= 1) { screen->specs.vertex_sampler_offset = 16; screen->specs.fragment_sampler_count = 16; screen->specs.vertex_sampler_count = 16; @@ -881,9 +881,9 @@ etna_get_specs(struct etna_screen *screen) screen->specs.nn_core_version = 6; } - screen->specs.halti = info->halti; - if (screen->specs.halti >= 0) - DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti); + screen->info->halti = info->halti; + if (screen->info->halti >= 0) + DBG("etnaviv: GPU arch: HALTI%d", screen->info->halti); else DBG("etnaviv: GPU arch: pre-HALTI"); @@ -919,7 +919,7 @@ etna_get_specs(struct etna_screen *screen) (screen->info->model != 0x880) && /* Seamless cubemap is broken on GC880? */ VIV_FEATURE(screen, ETNA_FEATURE_SEAMLESS_CUBE_MAP); - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { /* GC7000 - this core must load shaders from memory. */ screen->specs.vs_offset = 0; screen->specs.ps_offset = 0; @@ -965,11 +965,11 @@ etna_get_specs(struct etna_screen *screen) etna_determine_uniform_limits(screen); etna_determine_sampler_limits(screen); - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { screen->specs.has_unified_uniforms = true; screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0); screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4); - } else if (screen->specs.halti >= 1) { + } else if (screen->info->halti >= 1) { /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess */ screen->specs.has_unified_uniforms = true; @@ -1111,7 +1111,7 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, etna_get_specs(screen); - if (screen->specs.halti >= 5 && !etnaviv_device_softpin_capable(dev)) { + if (screen->info->halti >= 5 && !etnaviv_device_softpin_capable(dev)) { DBG("halti5 requires softpin"); goto fail; } @@ -1158,7 +1158,7 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, screen->dummy_rt_reloc.offset = 0; screen->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { void *buf; /* create an empty dummy texture descriptor */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c index 7aa2222f517..856085ba57e 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_state.c +++ b/src/gallium/drivers/etnaviv/etnaviv_state.c @@ -191,7 +191,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx, cbuf->offset, cbuf->level->stride * 4); } - if (screen->specs.halti >= 0 && screen->info->model != 0x880) { + if (screen->info->halti >= 0 && screen->info->model != 0x880) { /* Rendertargets on GPUs with more than a single pixel pipe must always * be multi-tiled, or single-buffer mode must be supported */ assert(screen->specs.pixel_pipes == 1 || @@ -235,7 +235,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx, cs->PS_CONTROL = COND(util_format_is_unorm(cbuf->base.format), VIVS_PS_CONTROL_SATURATE_RT0); cs->PS_CONTROL_EXT = - VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->specs.halti >= 5)); + VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->info->halti >= 5)); } else { /* Clearing VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK and * VIVS_PE_COLOR_FORMAT_OVERWRITE prevents us from overwriting the @@ -274,7 +274,7 @@ etna_set_framebuffer_state(struct pipe_context *pctx, /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */ /* merged with depth_stencil_alpha */ - if (screen->specs.halti >= 0 && screen->info->model != 0x880) { + if (screen->info->halti >= 0 && screen->info->model != 0x880) { for (int i = 0; i < screen->specs.pixel_pipes; i++) { cs->PE_PIPE_DEPTH_ADDR[i] = zsbuf->reloc[i]; cs->PE_PIPE_DEPTH_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE; @@ -578,7 +578,7 @@ etna_vertex_elements_state_create(struct pipe_context *pctx, assert(format_type != ETNA_NO_MATCH); assert(normalize != ETNA_NO_MATCH); - if (screen->specs.halti < 5) { + if (screen->info->halti < 5) { cs->FE_VERTEX_ELEMENT_CONFIG[idx] = COND(nonconsecutive, VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE) | format_type | diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture.c b/src/gallium/drivers/etnaviv/etnaviv_texture.c index 53fb1a544cb..d25f7a08283 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_texture.c +++ b/src/gallium/drivers/etnaviv/etnaviv_texture.c @@ -367,7 +367,7 @@ etna_texture_init(struct pipe_context *pctx) pctx->set_sampler_views = etna_set_sampler_views; pctx->texture_barrier = etna_texture_barrier; - if (screen->specs.halti >= 5) { + if (screen->info->halti >= 5) { u_suballocator_init(&ctx->tex_desc_allocator, pctx, 4096, 0, PIPE_USAGE_IMMUTABLE, 0, true); etna_texture_desc_init(pctx); @@ -382,6 +382,6 @@ etna_texture_fini(struct pipe_context *pctx) struct etna_context *ctx = etna_context(pctx); struct etna_screen *screen = ctx->screen; - if (screen->specs.halti >= 5) + if (screen->info->halti >= 5) u_suballocator_destroy(&ctx->tex_desc_allocator); } diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture_state.c b/src/gallium/drivers/etnaviv/etnaviv_texture_state.c index 6844a83c0e0..e8eae5923b4 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_texture_state.c +++ b/src/gallium/drivers/etnaviv/etnaviv_texture_state.c @@ -139,7 +139,7 @@ etna_create_sampler_state_state(struct pipe_context *pipe, VIVS_NTE_SAMPLER_BASELOD_COMPARE_FUNC(translate_texture_compare(ss->compare_func)); /* force nearest filting for nir_lower_sample_tex_compare(..) */ - if ((ctx->screen->specs.halti < 2) && ss->compare_mode) { + if ((ctx->screen->info->halti < 2) && ss->compare_mode) { cs->config0 &= ~VIVS_TE_SAMPLER_CONFIG0_MIN__MASK; cs->config0 &= ~VIVS_TE_SAMPLER_CONFIG0_MAG__MASK; @@ -617,7 +617,7 @@ etna_texture_state_init(struct pipe_context *pctx) STATIC_ASSERT(VIVS_TE_SAMPLER_LOD_ADDR__LEN == VIVS_NTE_SAMPLER_ADDR_LOD__LEN); - if (ctx->screen->specs.halti >= 1) + if (ctx->screen->info->halti >= 1) ctx->emit_texture_state = etna_emit_new_texture_state; else ctx->emit_texture_state = etna_emit_texture_state;