diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h
index 41be0688550..783ef572355 100644
--- a/src/compiler/shader_enums.h
+++ b/src/compiler/shader_enums.h
@@ -122,7 +122,7 @@ mesa_shader_stage_is_rt(mesa_shader_stage stage)
 }
 
 static inline bool
-gl_shader_stage_can_set_fragment_shading_rate(mesa_shader_stage stage)
+mesa_shader_stage_can_set_fragment_shading_rate(mesa_shader_stage stage)
 {
    /* According to EXT_fragment_shading_rate :
     *
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index fddab45ac23..d83706bbc6f 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -2036,7 +2036,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
    if (devinfo->ver >= 30)
       NIR_PASS(_, nir, brw_nir_lower_sample_index_in_coord);
 
-   if (gl_shader_stage_can_set_fragment_shading_rate(nir->info.stage))
+   if (mesa_shader_stage_can_set_fragment_shading_rate(nir->info.stage))
       NIR_PASS(_, nir, intel_nir_lower_shading_rate_output);
 
    OPT(brw_nir_tag_speculative_access);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 5a40d8074ed..7d3b97b0264 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -2463,7 +2463,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline,
 
          if (anv_graphics_pipeline_skip_shader_compile(pipeline, stages,
                                                        link_optimize, s) ||
-             !gl_shader_stage_can_set_fragment_shading_rate(s))
+             !mesa_shader_stage_can_set_fragment_shading_rate(s))
             continue;
 
          last_psr = &stages[s];