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i965: Move up fs_inst::flag_subreg to backend_instruction.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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parent
639696aa05
commit
dfe957c02b
5 changed files with 16 additions and 7 deletions
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@ -239,11 +239,6 @@ public:
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*/
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uint8_t exec_size;
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/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
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* mod and predication.
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*/
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uint8_t flag_subreg;
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bool eot:1;
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bool force_uncompressed:1;
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bool force_sechalf:1;
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@ -135,6 +135,11 @@ struct backend_instruction {
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bool saturate:1;
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bool shadow_compare:1;
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bool header_present:1;
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/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
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* mod and predication.
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*/
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unsigned flag_subreg:1;
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};
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#ifdef __cplusplus
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@ -1283,13 +1283,20 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file)
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vec4_instruction *inst = (vec4_instruction *)be_inst;
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if (inst->predicate) {
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fprintf(file, "(%cf0) ",
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inst->predicate_inverse ? '-' : '+');
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fprintf(file, "(%cf0.%d) ",
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inst->predicate_inverse ? '-' : '+',
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inst->flag_subreg);
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}
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fprintf(file, "%s", brw_instruction_name(inst->opcode));
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if (inst->conditional_mod) {
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fprintf(file, "%s", conditional_modifier[inst->conditional_mod]);
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if (!inst->predicate &&
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(brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
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inst->opcode != BRW_OPCODE_IF &&
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inst->opcode != BRW_OPCODE_WHILE))) {
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fprintf(file, ".f0.%d", inst->flag_subreg);
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}
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}
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fprintf(file, " ");
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@ -1167,6 +1167,7 @@ vec4_generator::generate_code(const cfg_t *cfg)
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brw_set_default_predicate_control(p, inst->predicate);
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brw_set_default_predicate_inverse(p, inst->predicate_inverse);
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brw_set_default_flag_reg(p, 0, inst->flag_subreg);
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brw_set_default_saturate(p, inst->saturate);
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brw_set_default_mask_control(p, inst->force_writemask_all);
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brw_set_default_acc_write_control(p, inst->writes_accumulator);
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@ -49,6 +49,7 @@ vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst,
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this->ir = NULL;
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this->urb_write_flags = BRW_URB_WRITE_NO_FLAGS;
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this->header_present = false;
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this->flag_subreg = 0;
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this->mlen = 0;
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this->base_mrf = 0;
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this->offset = 0;
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