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radeonsi/gfx9: DB changes

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-15 15:22:34 +02:00
parent 94819a3e6c
commit dfd2b54948
2 changed files with 171 additions and 89 deletions
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8
src/gallium/drivers/radeon/r600_pipe_common.h
View file

@ -307,17 +307,19 @@ struct r600_surface {
struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */ struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
/* DB registers. */ /* DB registers. */
uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
uint64_t db_stencil_base; /* EG and later */
uint64_t db_htile_data_base;
unsigned db_depth_info; /* R600 only, then SI and later */ unsigned db_depth_info; /* R600 only, then SI and later */
unsigned db_z_info; /* EG and later */ unsigned db_z_info; /* EG and later */
unsigned db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */ unsigned db_z_info2; /* GFX9+ */
unsigned db_depth_view; unsigned db_depth_view;
unsigned db_depth_size; unsigned db_depth_size;
unsigned db_depth_slice; /* EG and later */ unsigned db_depth_slice; /* EG and later */
unsigned db_stencil_base; /* EG and later */
unsigned db_stencil_info; /* EG and later */ unsigned db_stencil_info; /* EG and later */
unsigned db_stencil_info2; /* GFX9+ */
unsigned db_prefetch_limit; /* R600 only */ unsigned db_prefetch_limit; /* R600 only */
unsigned db_htile_surface; unsigned db_htile_surface;
unsigned db_htile_data_base;
unsigned db_preload_control; /* EG and later */ unsigned db_preload_control; /* EG and later */
}; };

106
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2244,7 +2244,6 @@ static void si_init_depth_surface(struct si_context *sctx,
{ {
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level; unsigned level = surf->base.u.tex.level;
struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
unsigned format, stencil_format; unsigned format, stencil_format;
uint32_t z_info, s_info; uint32_t z_info, s_info;
@ -2261,6 +2260,58 @@ static void si_init_depth_surface(struct si_context *sctx,
surf->db_htile_data_base = 0; surf->db_htile_data_base = 0;
surf->db_htile_surface = 0; surf->db_htile_surface = 0;
if (sctx->b.chip_class >= GFX9) {
surf->db_depth_base = rtex->resource.gpu_address >> 8;
surf->db_stencil_base = (rtex->resource.gpu_address +
rtex->surface.u.gfx9.stencil_offset) >> 8;
z_info = S_028038_FORMAT(format) |
S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
S_028038_MAXMIP(rtex->resource.b.b.last_level);
s_info = S_02803C_FORMAT(stencil_format) |
S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
surf->db_depth_view |= S_028008_MIPID(level);
surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
/* Only use HTILE for the first level. */
if (rtex->htile_buffer && !level) {
z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
S_028038_ALLOW_EXPCLEAR(1);
if (rtex->tc_compatible_htile) {
unsigned max_zplanes = 4;
if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
rtex->resource.b.b.nr_samples > 1)
max_zplanes = 2;
z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
S_028038_ITERATE_FLUSH(1);
s_info |= S_02803C_ITERATE_FLUSH(1);
}
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
/* Stencil buffer workaround ported from the SI-CI-VI code.
* See that for explanation.
*/
s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
} else {
/* Use all HTILE for depth if there's no stencil. */
s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
}
surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
}
} else {
/* SI-CI-VI */
struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
surf->db_depth_base = (rtex->resource.gpu_address + surf->db_depth_base = (rtex->resource.gpu_address +
@ -2344,6 +2395,7 @@ static void si_init_depth_surface(struct si_context *sctx,
z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2); z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
} }
} }
}
surf->db_z_info = z_info; surf->db_z_info = z_info;
surf->db_stencil_info = s_info; surf->db_stencil_info = s_info;
@ -2694,30 +2746,58 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
RADEON_PRIO_HTILE); RADEON_PRIO_HTILE);
} }
radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); if (sctx->b.chip_class >= GFX9) {
radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
} else {
radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */ radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */ radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0)); S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */ radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */ radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
}
radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2); radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */ radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */ radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
} else if (sctx->framebuffer.dirty_zsbuf) { } else if (sctx->framebuffer.dirty_zsbuf) {
if (sctx->b.chip_class >= GFX9)
radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
else
radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
} }
/* Framebuffer dimensions. */ /* Framebuffer dimensions. */