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radv: use ac_surface data structures
This is mostly mechanical changes of renaming types and introducing "legacy" everywhere. It doesn't use the ac_surface computation functions yet. Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Nicolai Hähnle
Dave Airlie
parent
543de22f4b
commit
dfc06d2fac
8 changed files with 81 additions and 153 deletions
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@ -62,6 +62,7 @@ enum radeon_micro_mode {
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#define RADEON_SURF_SBUFFER (1 << 18)
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#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
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/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
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#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
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#define RADEON_SURF_FMASK (1 << 21)
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#define RADEON_SURF_DISABLE_DCC (1 << 22)
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#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
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@ -2643,9 +2643,9 @@ static inline unsigned
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si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
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{
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if (stencil)
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return image->surface.stencil_tiling_index[level];
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return image->surface.u.legacy.stencil_tiling_index[level];
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else
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return image->surface.tiling_index[level];
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return image->surface.u.legacy.tiling_index[level];
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}
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static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
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@ -2664,7 +2664,7 @@ radv_initialise_color_surface(struct radv_device *device,
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unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
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uint64_t va;
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const struct radeon_surf *surf = &iview->image->surface;
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const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
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const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
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desc = vk_format_description(iview->vk_format);
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@ -2792,7 +2792,7 @@ radv_initialise_color_surface(struct radv_device *device,
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/* This must be set for fast clear to work without FMASK. */
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if (!iview->image->fmask.size &&
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device->physical_device->rad_info.chip_class == SI) {
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unsigned bankh = util_logbase2(iview->image->surface.bankh);
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unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
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cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
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}
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}
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@ -2805,7 +2805,7 @@ radv_initialise_ds_surface(struct radv_device *device,
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unsigned level = iview->base_mip;
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unsigned format;
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uint64_t va, s_offs, z_offs;
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const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
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const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
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bool stencil_only = false;
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memset(ds, 0, sizeof(*ds));
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switch (iview->vk_format) {
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@ -2827,7 +2827,7 @@ radv_initialise_ds_surface(struct radv_device *device,
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break;
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case VK_FORMAT_S8_UINT:
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stencil_only = true;
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level_info = &iview->image->surface.stencil_level[level];
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level_info = &iview->image->surface.u.legacy.stencil_level[level];
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break;
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default:
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break;
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@ -2837,8 +2837,8 @@ radv_initialise_ds_surface(struct radv_device *device,
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va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
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s_offs = z_offs = va;
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z_offs += iview->image->surface.level[level].offset;
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s_offs += iview->image->surface.stencil_level[level].offset;
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z_offs += iview->image->surface.u.legacy.level[level].offset;
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s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
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uint32_t max_slice = radv_surface_layer_count(iview);
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ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
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@ -2856,9 +2856,9 @@ radv_initialise_ds_surface(struct radv_device *device,
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if (device->physical_device->rad_info.chip_class >= CIK) {
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struct radeon_info *info = &device->physical_device->rad_info;
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unsigned tiling_index = iview->image->surface.tiling_index[level];
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unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
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unsigned macro_index = iview->image->surface.macro_tile_index;
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unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
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unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
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unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
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unsigned tile_mode = info->si_tile_mode_array[tiling_index];
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unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
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unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
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@ -129,9 +129,9 @@ static inline unsigned
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si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
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{
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if (stencil)
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return image->surface.stencil_tiling_index[level];
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return image->surface.u.legacy.stencil_tiling_index[level];
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else
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return image->surface.tiling_index[level];
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return image->surface.u.legacy.tiling_index[level];
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}
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static unsigned radv_map_swizzle(unsigned swizzle)
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@ -189,7 +189,7 @@ radv_make_buffer_descriptor(struct radv_device *device,
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static void
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si_set_mutable_tex_desc_fields(struct radv_device *device,
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struct radv_image *image,
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const struct radeon_surf_level *base_level_info,
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const struct legacy_surf_level *base_level_info,
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unsigned base_level, unsigned first_level,
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unsigned block_width, bool is_stencil,
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uint32_t *state)
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@ -409,7 +409,7 @@ radv_query_opaque_metadata(struct radv_device *device,
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image->info.depth,
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desc, NULL);
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si_set_mutable_tex_desc_fields(device, image, &image->surface.level[0], 0, 0,
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si_set_mutable_tex_desc_fields(device, image, &image->surface.u.legacy.level[0], 0, 0,
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image->surface.blk_w, false, desc);
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/* Clear the base address and set the relative DCC offset. */
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@ -422,7 +422,7 @@ radv_query_opaque_metadata(struct radv_device *device,
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/* Dwords [10:..] contain the mipmap level offsets. */
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for (i = 0; i <= image->info.levels - 1; i++)
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md->metadata[10+i] = image->surface.level[i].offset >> 8;
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md->metadata[10+i] = image->surface.u.legacy.level[i].offset >> 8;
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md->size_metadata = (11 + image->info.levels - 1) * 4;
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}
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@ -435,17 +435,17 @@ radv_init_metadata(struct radv_device *device,
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struct radeon_surf *surface = &image->surface;
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memset(metadata, 0, sizeof(*metadata));
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metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
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metadata->microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
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RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
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metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
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metadata->macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
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RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
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metadata->pipe_config = surface->pipe_config;
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metadata->bankw = surface->bankw;
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metadata->bankh = surface->bankh;
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metadata->tile_split = surface->tile_split;
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metadata->mtilea = surface->mtilea;
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metadata->num_banks = surface->num_banks;
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metadata->stride = surface->level[0].nblk_x * surface->bpe;
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metadata->pipe_config = surface->u.legacy.pipe_config;
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metadata->bankw = surface->u.legacy.bankw;
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metadata->bankh = surface->u.legacy.bankh;
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metadata->tile_split = surface->u.legacy.tile_split;
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metadata->mtilea = surface->u.legacy.mtilea;
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metadata->num_banks = surface->u.legacy.num_banks;
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metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
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metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
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radv_query_opaque_metadata(device, image, metadata);
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@ -460,7 +460,7 @@ radv_image_get_fmask_info(struct radv_device *device,
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{
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/* FMASK is allocated like an ordinary texture. */
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struct radeon_surf fmask = image->surface;
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struct radeon_surf_info info = image->info;
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struct ac_surf_info info = image->info;
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memset(out, 0, sizeof(*out));
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fmask.surf_alignment = 0;
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@ -488,15 +488,15 @@ radv_image_get_fmask_info(struct radv_device *device,
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}
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device->ws->surface_init(device->ws, &info, &fmask);
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assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
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assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
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out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
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out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
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if (out->slice_tile_max)
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out->slice_tile_max -= 1;
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out->tile_mode_index = fmask.tiling_index[0];
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out->pitch_in_pixels = fmask.level[0].nblk_x;
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out->bank_height = fmask.bankh;
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out->tile_mode_index = fmask.u.legacy.tiling_index[0];
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out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
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out->bank_height = fmask.u.legacy.bankh;
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out->alignment = MAX2(256, fmask.surf_alignment);
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out->size = fmask.surf_size;
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}
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@ -760,7 +760,9 @@ radv_image_view_init(struct radv_image_view *iview,
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iview->descriptor,
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iview->fmask_descriptor);
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si_set_mutable_tex_desc_fields(device, image,
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is_stencil ? &image->surface.stencil_level[range->baseMipLevel] : &image->surface.level[range->baseMipLevel], range->baseMipLevel,
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is_stencil ? &image->surface.u.legacy.stencil_level[range->baseMipLevel]
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: &image->surface.u.legacy.level[range->baseMipLevel],
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range->baseMipLevel,
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range->baseMipLevel,
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blk_w, is_stencil, iview->descriptor);
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}
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@ -847,11 +849,11 @@ void radv_GetImageSubresourceLayout(
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int layer = pSubresource->arrayLayer;
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struct radeon_surf *surface = &image->surface;
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pLayout->offset = surface->level[level].offset + surface->level[level].slice_size * layer;
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pLayout->rowPitch = surface->level[level].nblk_x * surface->bpe;
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pLayout->arrayPitch = surface->level[level].slice_size;
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pLayout->depthPitch = surface->level[level].slice_size;
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pLayout->size = surface->level[level].slice_size;
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pLayout->offset = surface->u.legacy.level[level].offset + surface->u.legacy.level[level].slice_size * layer;
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pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
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pLayout->arrayPitch = surface->u.legacy.level[level].slice_size;
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pLayout->depthPitch = surface->u.legacy.level[level].slice_size;
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pLayout->size = surface->u.legacy.level[level].slice_size;
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if (image->type == VK_IMAGE_TYPE_3D)
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pLayout->size *= u_minify(image->info.depth, level);
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}
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@ -900,7 +900,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
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if (iview->image->info.levels > 1)
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goto fail;
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if (iview->image->surface.level[0].mode < RADEON_SURF_MODE_1D)
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if (iview->image->surface.u.legacy.level[0].mode < RADEON_SURF_MODE_1D)
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goto fail;
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if (!radv_image_extent_compare(iview->image, &iview->extent))
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goto fail;
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@ -53,6 +53,7 @@
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#include "radv_radeon_winsys.h"
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#include "ac_binary.h"
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#include "ac_nir_to_llvm.h"
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#include "ac_surface.h"
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#include "radv_debug.h"
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#include "radv_descriptor_set.h"
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@ -1176,7 +1177,7 @@ struct radv_image {
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*/
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VkFormat vk_format;
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VkImageAspectFlags aspects;
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struct radeon_surf_info info;
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struct ac_surf_info info;
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VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
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VkImageTiling tiling; /** VkImageCreateInfo::tiling */
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VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
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@ -35,6 +35,9 @@
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#include "main/macros.h"
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#include "amd_family.h"
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struct ac_surf_info;
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struct radeon_surf;
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#define FREE(x) free(x)
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enum radeon_bo_domain { /* bitfield */
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@ -126,8 +129,6 @@ struct radeon_info {
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uint32_t cik_macrotile_mode_array[16];
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};
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#define RADEON_SURF_MAX_LEVEL 32
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#define RADEON_SURF_TYPE_MASK 0xFF
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#define RADEON_SURF_TYPE_SHIFT 0
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#define RADEON_SURF_TYPE_1D 0
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@ -138,91 +139,11 @@ struct radeon_info {
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#define RADEON_SURF_TYPE_2D_ARRAY 5
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#define RADEON_SURF_MODE_MASK 0xFF
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#define RADEON_SURF_MODE_SHIFT 8
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#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
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#define RADEON_SURF_MODE_1D 2
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#define RADEON_SURF_MODE_2D 3
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#define RADEON_SURF_SCANOUT (1 << 16)
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#define RADEON_SURF_ZBUFFER (1 << 17)
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#define RADEON_SURF_SBUFFER (1 << 18)
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#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
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#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
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#define RADEON_SURF_FMASK (1 << 21)
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#define RADEON_SURF_DISABLE_DCC (1 << 22)
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#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
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#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
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#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
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#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
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struct radeon_surf_info {
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uint32_t width;
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uint32_t height;
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uint32_t depth;
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uint8_t samples;
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uint8_t levels;
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uint16_t array_size;
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};
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struct radeon_surf_level {
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uint64_t offset;
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uint64_t slice_size;
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uint32_t nblk_x;
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uint32_t nblk_y;
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uint32_t mode;
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uint64_t dcc_offset;
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uint64_t dcc_fast_clear_size;
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};
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/* surface defintions from the winsys */
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struct radeon_surf {
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/* These are inputs to the calculator. */
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uint32_t blk_w;
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uint32_t blk_h;
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uint32_t bpe;
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uint32_t flags;
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unsigned num_dcc_levels:4;
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/* These are return values. Some of them can be set by the caller, but
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* they will be treated as hints (e.g. bankw, bankh) and might be
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* changed by the calculator.
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*/
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/* This applies to EG and later. */
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uint32_t bankw;
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uint32_t bankh;
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uint32_t mtilea;
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uint32_t tile_split;
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uint32_t stencil_tile_split;
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uint64_t stencil_offset;
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struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
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struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
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uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
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uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
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uint32_t pipe_config;
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uint32_t num_banks;
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uint32_t macro_tile_index;
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uint32_t micro_tile_mode; /* displayable, thin, depth, rotated */
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/* Whether the depth miptree or stencil miptree as used by the DB are
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* adjusted from their TC compatible form to ensure depth/stencil
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* compatibility. If either is true, the corresponding plane cannot be
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* sampled from.
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*/
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bool depth_adjusted;
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bool stencil_adjusted;
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uint64_t surf_size;
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uint64_t surf_alignment;
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uint64_t dcc_size;
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uint64_t dcc_alignment;
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uint64_t htile_size;
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uint64_t htile_slice_size;
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uint64_t htile_alignment;
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};
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enum radeon_bo_layout {
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RADEON_LAYOUT_LINEAR = 0,
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RADEON_LAYOUT_TILED,
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@ -332,7 +253,7 @@ struct radeon_winsys {
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void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id);
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int (*surface_init)(struct radeon_winsys *ws,
|
||||
const struct radeon_surf_info *surf_info,
|
||||
const struct ac_surf_info *surf_info,
|
||||
struct radeon_surf *surf);
|
||||
|
||||
int (*surface_best)(struct radeon_winsys *ws,
|
||||
|
|
|
|||
|
|
@ -224,7 +224,7 @@ radv_wsi_image_create(VkDevice device_h,
|
|||
*memory_p = memory_h;
|
||||
*size = image->size;
|
||||
*offset = image->offset;
|
||||
*row_pitch = surface->level[0].nblk_x * surface->bpe;
|
||||
*row_pitch = surface->u.legacy.level[0].nblk_x * surface->bpe;
|
||||
return VK_SUCCESS;
|
||||
fail_alloc_memory:
|
||||
radv_FreeMemory(device_h, memory_h, pAllocator);
|
||||
|
|
|
|||
|
|
@ -35,6 +35,8 @@
|
|||
#include "radv_amdgpu_surface.h"
|
||||
#include "sid.h"
|
||||
|
||||
#include "ac_surface.h"
|
||||
|
||||
#ifndef NO_ENTRIES
|
||||
#define NO_ENTRIES 32
|
||||
#endif
|
||||
|
|
@ -47,7 +49,7 @@
|
|||
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
|
||||
#endif
|
||||
|
||||
static int radv_amdgpu_surface_sanity(const struct radeon_surf_info *surf_info,
|
||||
static int radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info,
|
||||
const struct radeon_surf *surf)
|
||||
{
|
||||
unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
|
||||
|
|
@ -159,7 +161,7 @@ ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family,
|
|||
}
|
||||
|
||||
static int radv_compute_level(ADDR_HANDLE addrlib,
|
||||
const struct radeon_surf_info *surf_info,
|
||||
const struct ac_surf_info *surf_info,
|
||||
struct radeon_surf *surf, bool is_stencil,
|
||||
unsigned level, unsigned type, bool compressed,
|
||||
ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
|
||||
|
|
@ -167,7 +169,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
|
|||
ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
|
||||
ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut)
|
||||
{
|
||||
struct radeon_surf_level *surf_level;
|
||||
struct legacy_surf_level *surf_level;
|
||||
ADDR_E_RETURNCODE ret;
|
||||
|
||||
AddrSurfInfoIn->mipLevel = level;
|
||||
|
|
@ -185,9 +187,9 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
|
|||
/* Set the base level pitch. This is needed for calculation
|
||||
* of non-zero levels. */
|
||||
if (is_stencil)
|
||||
AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
|
||||
AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
|
||||
else
|
||||
AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
|
||||
AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
|
||||
|
||||
/* Convert blocks to pixels for compressed formats. */
|
||||
if (compressed)
|
||||
|
|
@ -200,7 +202,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
|
|||
if (ret != ADDR_OK)
|
||||
return ret;
|
||||
|
||||
surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
|
||||
surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
|
||||
surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
|
||||
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
|
||||
surf_level->nblk_x = AddrSurfInfoOut->pitch;
|
||||
|
|
@ -221,9 +223,9 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
|
|||
}
|
||||
|
||||
if (is_stencil)
|
||||
surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
|
||||
surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
|
||||
else
|
||||
surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
|
||||
surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
|
||||
|
||||
surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
|
||||
|
||||
|
|
@ -282,7 +284,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
|
|||
static void radv_set_micro_tile_mode(struct radeon_surf *surf,
|
||||
struct radeon_info *info)
|
||||
{
|
||||
uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
|
||||
uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
|
||||
|
||||
if (info->chip_class >= CIK)
|
||||
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
|
||||
|
|
@ -295,7 +297,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
|
|||
unsigned index, tileb;
|
||||
|
||||
tileb = 8 * 8 * surf->bpe;
|
||||
tileb = MIN2(surf->tile_split, tileb);
|
||||
tileb = MIN2(surf->u.legacy.tile_split, tileb);
|
||||
|
||||
for (index = 0; tileb > 64; index++)
|
||||
tileb >>= 1;
|
||||
|
|
@ -305,7 +307,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
|
|||
}
|
||||
|
||||
static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
|
||||
const struct radeon_surf_info *surf_info,
|
||||
const struct ac_surf_info *surf_info,
|
||||
struct radeon_surf *surf)
|
||||
{
|
||||
struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
|
||||
|
|
@ -422,15 +424,16 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
|
|||
/* Set preferred macrotile parameters. This is usually required
|
||||
* for shared resources. This is for 2D tiling only. */
|
||||
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
|
||||
surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
|
||||
surf->u.legacy.bankw && surf->u.legacy.bankh && surf->u.legacy.mtilea &&
|
||||
surf->u.legacy.tile_split) {
|
||||
/* If any of these parameters are incorrect, the calculation
|
||||
* will fail. */
|
||||
AddrTileInfoIn.banks = surf->num_banks;
|
||||
AddrTileInfoIn.bankWidth = surf->bankw;
|
||||
AddrTileInfoIn.bankHeight = surf->bankh;
|
||||
AddrTileInfoIn.macroAspectRatio = surf->mtilea;
|
||||
AddrTileInfoIn.tileSplitBytes = surf->tile_split;
|
||||
AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
|
||||
AddrTileInfoIn.banks = surf->u.legacy.num_banks;
|
||||
AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
|
||||
AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
|
||||
AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
|
||||
AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
|
||||
AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
|
||||
AddrSurfInfoIn.flags.opt4Space = 0;
|
||||
AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
|
||||
|
||||
|
|
@ -486,19 +489,19 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
|
|||
|
||||
if (level == 0) {
|
||||
surf->surf_alignment = AddrSurfInfoOut.baseAlign;
|
||||
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
|
||||
surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
|
||||
radv_set_micro_tile_mode(surf, &ws->info);
|
||||
|
||||
/* For 2D modes only. */
|
||||
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
|
||||
surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
|
||||
surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
|
||||
surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
|
||||
surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
||||
surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
|
||||
surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
|
||||
surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
|
||||
surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
|
||||
surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
|
||||
surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
||||
surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
|
||||
surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
|
||||
} else {
|
||||
surf->macro_tile_index = 0;
|
||||
surf->u.legacy.macro_tile_index = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -509,7 +512,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
|
|||
AddrSurfInfoIn.flags.depth = 0;
|
||||
AddrSurfInfoIn.flags.stencil = 1;
|
||||
/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
|
||||
AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
|
||||
AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
|
||||
|
||||
for (level = 0; level <= last_level; level++) {
|
||||
r = radv_compute_level(ws->addrlib, surf_info, surf, true, level, type, compressed,
|
||||
|
|
@ -518,13 +521,13 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
|
|||
return r;
|
||||
|
||||
/* DB uses the depth pitch for both stencil and depth. */
|
||||
if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
|
||||
surf->stencil_adjusted = true;
|
||||
if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
|
||||
surf->u.legacy.stencil_adjusted = true;
|
||||
|
||||
if (level == 0) {
|
||||
/* For 2D modes only. */
|
||||
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
|
||||
surf->stencil_tile_split =
|
||||
surf->u.legacy.stencil_tile_split =
|
||||
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue