From dfa60b70e631f308523e8dca7ea68c84b166bc27 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Sat, 18 Nov 2023 22:06:28 -0400 Subject: [PATCH] radeonsi: use pipe_shader_from_nir MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alyssa Rosenzweig Reviewed-by: Eric Engestrom Reviewed-by: Marek Olšák Part-of: --- .../drivers/radeonsi/si_shaderlib_nir.c | 26 ++----------------- 1 file changed, 2 insertions(+), 24 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shaderlib_nir.c b/src/gallium/drivers/radeonsi/si_shaderlib_nir.c index 2b4373d16e3..ee9bf2fc159 100644 --- a/src/gallium/drivers/radeonsi/si_shaderlib_nir.c +++ b/src/gallium/drivers/radeonsi/si_shaderlib_nir.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: MIT */ +#include "gallium/auxiliary/nir/pipe_nir.h" #define AC_SURFACE_INCLUDE_NIR #include "ac_surface.h" #include "si_pipe.h" @@ -13,30 +14,7 @@ static void *create_shader_state(struct si_context *sctx, nir_shader *nir) { sctx->b.screen->finalize_nir(sctx->b.screen, (void*)nir); - - struct pipe_shader_state state = {0}; - state.type = PIPE_SHADER_IR_NIR; - state.ir.nir = nir; - - switch (nir->info.stage) { - case MESA_SHADER_VERTEX: - return sctx->b.create_vs_state(&sctx->b, &state); - case MESA_SHADER_TESS_CTRL: - return sctx->b.create_tcs_state(&sctx->b, &state); - case MESA_SHADER_TESS_EVAL: - return sctx->b.create_tes_state(&sctx->b, &state); - case MESA_SHADER_FRAGMENT: - return sctx->b.create_fs_state(&sctx->b, &state); - case MESA_SHADER_COMPUTE: { - struct pipe_compute_state cs_state = {0}; - cs_state.ir_type = PIPE_SHADER_IR_NIR; - cs_state.prog = nir; - return sctx->b.create_compute_state(&sctx->b, &cs_state); - } - default: - unreachable("invalid shader stage"); - return NULL; - } + return pipe_shader_from_nir(&sctx->b, nir); } static nir_def *get_global_ids(nir_builder *b, unsigned num_components)