diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index 209402f4718..0e139ac1a84 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -1097,7 +1097,7 @@ registers:
00000000 0x8635: 00000000
00000000 0x8636: 00000000
00000000 0x8637: 00000000
- 00000000 VPC_UNKNOWN_9600: 0
+ 00000000 VPC_DBG_ECO_CNTL: 0
00000001 VPC_ADDR_MODE_CNTL: ADDR_64B
00000000 VPC_UNKNOWN_9602: FALSE
00000000 VPC_UNKNOWN_9603: 0
@@ -1553,7 +1553,7 @@ registers:
00000000 VFD_PERFCTR_VFD_SEL[0x6]+0: 00000000
00000000 VFD_PERFCTR_VFD_SEL[0x7]+0: 00000000
00000000 0xa630: 00000000
- 00100000 RB_UNKNOWN_8E04: 0x100000
+ 00100000 RB_DBG_ECO_CNTL: 0x100000
00000001 RB_ADDR_MODE_CNTL: ADDR_64B
00000000 RB_CCU_CNTL: { COLOR_OFFSET = 0 | DEPTH_OFFSET = 0 }
00000004 RB_NC_MODE_CNTL: { LOWER_BIT = 2 | UPPER_BIT = 0 }
@@ -1613,7 +1613,7 @@ registers:
00000000 0x8e77: 00000000
00000000 HLSQ_UNKNOWN_BE00: 0
00000001 HLSQ_UNKNOWN_BE01: 0 | 0x1
- 00000004 HLSQ_UNKNOWN_BE04: 0x4
+ 00000004 HLSQ_DBG_ECO_CNTL: 0x4
00000000 HLSQ_ADDR_MODE_CNTL: ADDR_32B
deadbeef HLSQ_UNKNOWN_BE08: 0xbeef | 0xdead0000
deadbeef 0xbe09: deadbeef
@@ -1627,7 +1627,7 @@ registers:
00000000 0xbe21: 00000000
00000000 SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE: 0
00000000 0xbe23: 00000000
- 00000000 SP_UNKNOWN_AE00: 0
+ 00000000 SP_DBG_ECO_CNTL: 0
00000001 SP_ADDR_MODE_CNTL: ADDR_64B
deadbeef SP_NC_MODE_CNTL: 0xdeadbeef
deadbeef SP_CHICKEN_BITS: 0xdeadbeef
diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index 1fd463f3f21..47e16e6463a 100644
--- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -14,14 +14,14 @@ t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
t4 write RB_CCU_CNTL (8e07)
RB_CCU_CNTL: { COLOR_OFFSET = 0x20000 | DEPTH_OFFSET = 0 }
0000000001058014: 0000: 408e0701 10000000
-t4 write RB_UNKNOWN_8E04 (8e04)
- RB_UNKNOWN_8E04: 0x100000
+t4 write RB_DBG_ECO_CNTL (8e04)
+ RB_DBG_ECO_CNTL: 0x100000
000000000105801c: 0000: 408e0401 00100000
t4 write SP_FLOAT_CNTL (ae04)
SP_FLOAT_CNTL: { F16_NO_INF }
0000000001058024: 0000: 48ae0401 00000008
-t4 write SP_UNKNOWN_AE00 (ae00)
- SP_UNKNOWN_AE00: 0
+t4 write SP_DBG_ECO_CNTL (ae00)
+ SP_DBG_ECO_CNTL: 0
000000000105802c: 0000: 40ae0001 00000000
t4 write SP_PERFCTR_ENABLE (ae0f)
SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
@@ -38,14 +38,14 @@ t4 write HLSQ_UNKNOWN_BE00 (be00)
t4 write HLSQ_UNKNOWN_BE01 (be01)
HLSQ_UNKNOWN_BE01: 0
0000000001058054: 0000: 40be0101 00000000
-t4 write VPC_UNKNOWN_9600 (9600)
- VPC_UNKNOWN_9600: 0
+t4 write VPC_DBG_ECO_CNTL (9600)
+ VPC_DBG_ECO_CNTL: 0
000000000105805c: 0000: 48960001 00000000
t4 write GRAS_DBG_ECO_CNTL (8600)
GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
0000000001058064: 0000: 40860001 00000880
-t4 write HLSQ_UNKNOWN_BE04 (be04)
- HLSQ_UNKNOWN_BE04: 0
+t4 write HLSQ_DBG_ECO_CNTL (be04)
+ HLSQ_DBG_ECO_CNTL: 0
000000000105806c: 0000: 40be0401 00000000
t4 write SP_CHICKEN_BITS (ae03)
SP_CHICKEN_BITS: 0x410
@@ -321,7 +321,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 RB_2D_SRC_SOLID_C2: 0
!+ 000000ff RB_2D_SRC_SOLID_C3: 0xff
+ 00000000 RB_UNKNOWN_8E01: 0
-!+ 00100000 RB_UNKNOWN_8E04: 0x100000
+!+ 00100000 RB_DBG_ECO_CNTL: 0x100000
!+ 10000000 RB_CCU_CNTL: { COLOR_OFFSET = 0x20000 | DEPTH_OFFSET = 0 }
+ 00000000 VPC_UNKNOWN_9107: { 0 }
+ 00000000 VPC_UNKNOWN_9210: 0
@@ -329,7 +329,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 VPC_POINT_COORD_INVERT: { 0 }
+ 00000000 VPC_UNKNOWN_9300: 0
!+ 00000001 VPC_SO_DISABLE: { DISABLE }
- + 00000000 VPC_UNKNOWN_9600: 0
+ + 00000000 VPC_DBG_ECO_CNTL: 0
+ 00000000 VPC_UNKNOWN_9602: FALSE
!+ 0000001f PC_MODE_CNTL: 0x1f
+ 00000000 PC_RASTER_CNTL: { STREAM = 0 }
@@ -347,7 +347,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
+ 00000000 SP_IBO_COUNT: 0
!+ 0000f180 SP_2D_DST_FORMAT: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
- + 00000000 SP_UNKNOWN_AE00: 0
+ + 00000000 SP_DBG_ECO_CNTL: 0
!+ 00000410 SP_CHICKEN_BITS: 0x410
!+ 00000008 SP_FLOAT_CNTL: { F16_NO_INF }
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
@@ -365,7 +365,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords)
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
+ 00000000 HLSQ_UNKNOWN_BE01: 0
- + 00000000 HLSQ_UNKNOWN_BE04: 0
+ + 00000000 HLSQ_DBG_ECO_CNTL: 0
00000000010582dc: 0000: 702c0001 00000003
t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
{ EVENT = LRZ_FLUSH }
diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index 7d4b9869c29..7f20345c0d2 100644
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -11,14 +11,14 @@ t4 write HLSQ_INVALIDATE_CMD (bb08)
0000000001d91008: 0000: 40bb0801 000fffff
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d91010: 0000: 70268000
-t4 write RB_UNKNOWN_8E04 (8e04)
- RB_UNKNOWN_8E04: 0
+t4 write RB_DBG_ECO_CNTL (8e04)
+ RB_DBG_ECO_CNTL: 0
0000000001d91014: 0000: 408e0401 00000000
t4 write SP_FLOAT_CNTL (ae04)
SP_FLOAT_CNTL: { F16_NO_INF }
0000000001d9101c: 0000: 48ae0401 00000008
-t4 write SP_UNKNOWN_AE00 (ae00)
- SP_UNKNOWN_AE00: 0
+t4 write SP_DBG_ECO_CNTL (ae00)
+ SP_DBG_ECO_CNTL: 0
0000000001d91024: 0000: 40ae0001 00000000
t4 write SP_PERFCTR_ENABLE (ae0f)
SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
@@ -35,14 +35,14 @@ t4 write HLSQ_UNKNOWN_BE00 (be00)
t4 write HLSQ_UNKNOWN_BE01 (be01)
HLSQ_UNKNOWN_BE01: 0
0000000001d9104c: 0000: 40be0101 00000000
-t4 write VPC_UNKNOWN_9600 (9600)
- VPC_UNKNOWN_9600: 0
+t4 write VPC_DBG_ECO_CNTL (9600)
+ VPC_DBG_ECO_CNTL: 0
0000000001d91054: 0000: 48960001 00000000
t4 write GRAS_DBG_ECO_CNTL (8600)
GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
0000000001d9105c: 0000: 40860001 00000880
-t4 write HLSQ_UNKNOWN_BE04 (be04)
- HLSQ_UNKNOWN_BE04: 0x80000
+t4 write HLSQ_DBG_ECO_CNTL (be04)
+ HLSQ_DBG_ECO_CNTL: 0x80000
0000000001d91064: 0000: 40be0401 00080000
t4 write SP_CHICKEN_BITS (ae03)
SP_CHICKEN_BITS: 0x1430
@@ -1022,7 +1022,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
!+ 00000001 RB_UNKNOWN_8E01: 0x1
- + 00000000 RB_UNKNOWN_8E04: 0
+ + 00000000 RB_DBG_ECO_CNTL: 0
!+ 7c400004 RB_CCU_CNTL: { COLOR_OFFSET = 0xf8000 | DEPTH_OFFSET = 0 | GMEM | CONCURRENT_RESOLVE }
!+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
!+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 }
@@ -1040,7 +1040,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 }
+ 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 }
+ 00000000 VPC_SO_DISABLE: { 0 }
- + 00000000 VPC_UNKNOWN_9600: 0
+ + 00000000 VPC_DBG_ECO_CNTL: 0
+ 00000000 VPC_UNKNOWN_9602: FALSE
!+ ffffffff PC_RESTART_INDEX: 4294967295
!+ 0000001f PC_MODE_CNTL: 0x1f
@@ -1121,7 +1121,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
!+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
!+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_IBO_COUNT: 0
- + 00000000 SP_UNKNOWN_AE00: 0
+ + 00000000 SP_DBG_ECO_CNTL: 0
!+ 00001430 SP_CHICKEN_BITS: 0x1430
!+ 00000008 SP_FLOAT_CNTL: { F16_NO_INF }
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
@@ -1149,7 +1149,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
+ 00000000 HLSQ_SHARED_CONSTS: { 0 }
!+ 00000080 HLSQ_UNKNOWN_BE00: 0x80
+ 00000000 HLSQ_UNKNOWN_BE01: 0
-!+ 00080000 HLSQ_UNKNOWN_BE04: 0x80000
+!+ 00080000 HLSQ_DBG_ECO_CNTL: 0x80000
0000000001d8f130: 0000: 70388003 00000186 00000001 00000004
t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001d8f140: 0000: 70268000
diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index a0782aca0fb..1b1188f0afb 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -146,7 +146,7 @@ struct fd_dev_info {
bool lrz_track_quirk;
struct {
- uint32_t RB_UNKNOWN_8E04_blit;
+ uint32_t RB_DBG_ECO_CNTL_blit;
uint32_t PC_POWER_CNTL;
uint32_t TPL1_DBG_ECO_CNTL;
} magic;
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index fe93ea52500..e877744853a 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -109,7 +109,7 @@ class A6xxGPUInfo(GPUInfo):
duplication of parameters that are unique to the sub-generation.
"""
def __init__(self, template, num_sp_cores, num_ccu,
- RB_UNKNOWN_8E04_blit, PC_POWER_CNTL):
+ RB_DBG_ECO_CNTL_blit, PC_POWER_CNTL):
super().__init__(gmem_align_w = 16, gmem_align_h = 4,
tile_align_w = 32, tile_align_h = 32,
tile_max_w = 1024, # max_bitfield_val(5, 0, 5)
@@ -130,7 +130,7 @@ class A6xxGPUInfo(GPUInfo):
setattr(self.a6xx.magic, name, val)
# Various "magic" register values:
- self.a6xx.magic.RB_UNKNOWN_8E04_blit = RB_UNKNOWN_8E04_blit
+ self.a6xx.magic.RB_DBG_ECO_CNTL_blit = RB_DBG_ECO_CNTL_blit
self.a6xx.magic.PC_POWER_CNTL = PC_POWER_CNTL
# Things that earlier gens have and later gens remove, provide
@@ -291,7 +291,7 @@ add_gpus([
a6xx_gen1,
num_sp_cores = 1,
num_ccu = 1,
- RB_UNKNOWN_8E04_blit = 0x00100000,
+ RB_DBG_ECO_CNTL_blit = 0x00100000,
PC_POWER_CNTL = 0,
))
@@ -301,7 +301,7 @@ add_gpus([
a6xx_gen1,
num_sp_cores = 2,
num_ccu = 2,
- RB_UNKNOWN_8E04_blit = 0x01000000,
+ RB_DBG_ECO_CNTL_blit = 0x01000000,
PC_POWER_CNTL = 1,
))
@@ -311,7 +311,7 @@ add_gpus([
a6xx_gen2,
num_sp_cores = 2,
num_ccu = 2,
- RB_UNKNOWN_8E04_blit = 0x00100000,
+ RB_DBG_ECO_CNTL_blit = 0x00100000,
PC_POWER_CNTL = 1,
))
@@ -321,7 +321,7 @@ add_gpus([
a6xx_gen2,
num_sp_cores = 4,
num_ccu = 4,
- RB_UNKNOWN_8E04_blit = 0x04100000,
+ RB_DBG_ECO_CNTL_blit = 0x04100000,
PC_POWER_CNTL = 3,
))
@@ -331,7 +331,7 @@ add_gpus([
a6xx_gen3,
num_sp_cores = 3,
num_ccu = 3,
- RB_UNKNOWN_8E04_blit = 0x04100000,
+ RB_DBG_ECO_CNTL_blit = 0x04100000,
PC_POWER_CNTL = 2,
))
@@ -345,7 +345,7 @@ add_gpus([
a6xx_gen4,
num_sp_cores = 2,
num_ccu = 2,
- RB_UNKNOWN_8E04_blit = 0x00100000,
+ RB_DBG_ECO_CNTL_blit = 0x00100000,
PC_POWER_CNTL = 1,
))
@@ -355,7 +355,7 @@ add_gpus([
a6xx_gen4,
num_sp_cores = 3,
num_ccu = 3,
- RB_UNKNOWN_8E04_blit = 0x04100000,
+ RB_DBG_ECO_CNTL_blit = 0x04100000,
PC_POWER_CNTL = 2,
))
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 060a9541d46..83885e0c784 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -2338,7 +2338,7 @@ to upconvert to 32b float internally?
-
+
@@ -2549,7 +2549,7 @@ to upconvert to 32b float internally?
-
+
@@ -3394,7 +3394,7 @@ to upconvert to 32b float internally?
-
+
@@ -3704,7 +3704,7 @@ to upconvert to 32b float internally?
-
+
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 8261d349de4..8f9ea446865 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -844,9 +844,9 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_regs(cs,
A6XX_RB_CCU_CNTL(.color_offset = phys_dev->ccu_offset_bypass));
cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
- tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E04, 0x00100000);
+ tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL, 0x00100000);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
+ tu_cs_emit_write_reg(cs, REG_A6XX_SP_DBG_ECO_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL,
@@ -854,9 +854,9 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
- tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9600, 0);
+ tu_cs_emit_write_reg(cs, REG_A6XX_VPC_DBG_ECO_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_DBG_ECO_CNTL, 0x880);
- tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE04, 0);
+ tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_DBG_ECO_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS, 0x00000410);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_IBO_COUNT, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
@@ -3287,7 +3287,7 @@ vk2tu_access(VkAccessFlags2 flags, VkPipelineStageFlags2 stages, bool image_only
static VkPipelineStageFlags2
sanitize_src_stage(VkPipelineStageFlags2 stage_mask)
{
- /* From the Vulkan spec:
+ /* From the Vulkan spec:
*
* VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT is ... equivalent to
* VK_PIPELINE_STAGE_2_NONE in the first scope.
@@ -3305,7 +3305,7 @@ sanitize_src_stage(VkPipelineStageFlags2 stage_mask)
static VkPipelineStageFlags2
sanitize_dst_stage(VkPipelineStageFlags2 stage_mask)
{
- /* From the Vulkan spec:
+ /* From the Vulkan spec:
*
* VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT is equivalent to
* VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT with VkAccessFlags2 set to 0
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
index 9d381967674..1c01a4ad02a 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
@@ -412,16 +412,16 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, 0x3f);
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, 0); /* RB_DBG_ECO_CNTL */
}
}
@@ -507,16 +507,16 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt
OUT_RING(ring, 0x3f);
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, batch->ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, batch->ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, 0); /* RB_DBG_ECO_CNTL */
offset += w * h;
size -= w * h;
@@ -685,16 +685,16 @@ emit_blit_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, 0x3f);
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, 0); /* RB_DBG_ECO_CNTL */
}
}
@@ -813,16 +813,16 @@ fd6_clear_surface(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_RING(ring, 0x3f);
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, ctx->screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, 0); /* RB_UNKNOWN_8E04 */
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, 0); /* RB_DBG_ECO_CNTL */
}
}
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
index 87e3b43047f..a61af126240 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
@@ -431,16 +431,16 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth) a
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, screen->info->a6xx.magic.RB_UNKNOWN_8E04_blit);
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, screen->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, 0x0); /* RB_UNKNOWN_8E04 */
+ OUT_PKT4(ring, REG_A6XX_RB_DBG_ECO_CNTL, 1);
+ OUT_RING(ring, 0x0); /* RB_DBG_ECO_CNTL */
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 3ae8fb5949f..014f1c7e71d 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1256,18 +1256,18 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
OUT_WFI5(ring);
- WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
+ WRITE(REG_A6XX_RB_DBG_ECO_CNTL, 0x0);
WRITE(REG_A6XX_SP_FLOAT_CNTL, A6XX_SP_FLOAT_CNTL_F16_NO_INF);
- WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
+ WRITE(REG_A6XX_SP_DBG_ECO_CNTL, 0);
WRITE(REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
WRITE(REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
WRITE(REG_A6XX_TPL1_DBG_ECO_CNTL, screen->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
- WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
+ WRITE(REG_A6XX_VPC_DBG_ECO_CNTL, 0);
WRITE(REG_A6XX_GRAS_DBG_ECO_CNTL, 0x880);
- WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
+ WRITE(REG_A6XX_HLSQ_DBG_ECO_CNTL, 0x80000);
WRITE(REG_A6XX_SP_CHICKEN_BITS, 0x1430);
WRITE(REG_A6XX_SP_IBO_COUNT, 0);
WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);