From df0fe0dfbdd3de42039d9da881433952b92101ea Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Mon, 18 Dec 2023 08:18:13 -0800
Subject: [PATCH] intel/genxml/xe2: Remove L3ALLOC
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This register don't exist in Xe2 and there is no Bspec page with
another register to be programmed with L3 allocation layout so
intel_get_l3_config() can also always return NULL for Xe2.

Still allowing intel_get_l3_config() to return non-null because
intel_l3_config is used to calculate TBIMR parameters, see
intel_calculate_tile_dimensions().

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26742>
---
 src/gallium/drivers/iris/iris_state.c | 2 ++
 src/intel/genxml/gen20.xml            | 1 +
 src/intel/vulkan/genX_init_state.c    | 2 ++
 3 files changed, 5 insertions(+)

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 9fe6bc566d7..24580f3bcdf 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -833,6 +833,7 @@ static void
 iris_emit_l3_config(struct iris_batch *batch,
                     const struct intel_l3_config *cfg)
 {
+#if GFX_VER < 20
    assert(cfg || GFX_VER >= 12);
 
 #if GFX_VER >= 12
@@ -870,6 +871,7 @@ iris_emit_l3_config(struct iris_batch *batch,
 #endif
       }
    }
+#endif /* GFX_VER < 20 */
 }
 
 #if GFX_VER == 9
diff --git a/src/intel/genxml/gen20.xml b/src/intel/genxml/gen20.xml
index 944bf8fc98b..315f6a9ecfa 100644
--- a/src/intel/genxml/gen20.xml
+++ b/src/intel/genxml/gen20.xml
@@ -3,6 +3,7 @@
   <import name="gen125.xml">
     <exclude name="3DSTATE_CLEAR_PARAMS" />
     <exclude name="CLEAR_COLOR" />
+    <exclude name="L3ALLOC" />
   </import>
   <enum name="PREF_SLM_ALLOCATION_SIZE">
     <value name="SLM_ENCODES_0K" value="0" />
diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c
index b099f60981d..b52023bfda4 100644
--- a/src/intel/vulkan/genX_init_state.c
+++ b/src/intel/vulkan/genX_init_state.c
@@ -900,6 +900,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
                      const struct anv_device *device,
                      const struct intel_l3_config *cfg)
 {
+#if GFX_VER < 20
    UNUSED const struct intel_device_info *devinfo = device->info;
 
 #if GFX_VER >= 12
@@ -942,6 +943,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
          l3cr.AllAllocation = cfg->n[INTEL_L3P_ALL];
       }
    }
+#endif /* GFX_VER < 20 */
 }
 
 void