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radeon/r200: fix bogus clears
There were several problems with these functions (which are a remnant of dri1 hyperz mostly - should bring it back somehow someday). First, it would always do a swrast clear if the buffer to clear was a fbo. Second, for buffers we wouldn't handle the clear (I guess aux/accum?) we would actually still have tried to clear that later even when we already cleared it with swrast.
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5b88a2a22d
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2 changed files with 22 additions and 52 deletions
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@ -57,8 +57,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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static void r200Clear( struct gl_context *ctx, GLbitfield mask )
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{
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r200ContextPtr rmesa = R200_CONTEXT(ctx);
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GLuint flags = 0;
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GLuint orig_mask = mask;
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GLuint hwmask, swmask;
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GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT |
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BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL |
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BUFFER_BIT_COLOR0;
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if ( R200_DEBUG & RADEON_IOCTL ) {
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if (rmesa->radeon.sarea)
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@ -69,36 +71,19 @@ static void r200Clear( struct gl_context *ctx, GLbitfield mask )
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radeonFlush( ctx );
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if ( mask & BUFFER_BIT_FRONT_LEFT ) {
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flags |= RADEON_FRONT;
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mask &= ~BUFFER_BIT_FRONT_LEFT;
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}
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hwmask = mask & hwbits;
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swmask = mask & ~hwbits;
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if ( mask & BUFFER_BIT_BACK_LEFT ) {
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flags |= RADEON_BACK;
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mask &= ~BUFFER_BIT_BACK_LEFT;
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}
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if ( mask & BUFFER_BIT_DEPTH ) {
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flags |= RADEON_DEPTH;
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mask &= ~BUFFER_BIT_DEPTH;
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}
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if ( (mask & BUFFER_BIT_STENCIL) ) {
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flags |= RADEON_STENCIL;
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mask &= ~BUFFER_BIT_STENCIL;
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}
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if ( mask ) {
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if ( swmask ) {
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if (R200_DEBUG & RADEON_FALLBACKS)
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fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
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_swrast_Clear( ctx, mask );
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fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, swmask);
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_swrast_Clear( ctx, swmask );
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}
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if ( !flags )
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if ( !hwmask )
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return;
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radeonUserClear(ctx, orig_mask);
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radeonUserClear(ctx, hwmask);
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}
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GLboolean r200IsGartMemory( r200ContextPtr rmesa, const GLvoid *pointer,
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@ -381,8 +381,10 @@ void radeonEmitAOS( r100ContextPtr rmesa,
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static void radeonClear( struct gl_context *ctx, GLbitfield mask )
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{
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r100ContextPtr rmesa = R100_CONTEXT(ctx);
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GLuint flags = 0;
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GLuint orig_mask = mask;
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GLuint hwmask, swmask;
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GLuint hwbits = BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT |
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BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL |
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BUFFER_BIT_COLOR0;
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if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
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rmesa->radeon.front_buffer_dirty = GL_TRUE;
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@ -394,36 +396,19 @@ static void radeonClear( struct gl_context *ctx, GLbitfield mask )
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radeon_firevertices(&rmesa->radeon);
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if ( mask & BUFFER_BIT_FRONT_LEFT ) {
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flags |= RADEON_FRONT;
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mask &= ~BUFFER_BIT_FRONT_LEFT;
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}
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hwmask = mask & hwbits;
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swmask = mask & ~hwbits;
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if ( mask & BUFFER_BIT_BACK_LEFT ) {
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flags |= RADEON_BACK;
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mask &= ~BUFFER_BIT_BACK_LEFT;
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}
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if ( mask & BUFFER_BIT_DEPTH ) {
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flags |= RADEON_DEPTH;
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mask &= ~BUFFER_BIT_DEPTH;
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}
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if ( (mask & BUFFER_BIT_STENCIL) ) {
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flags |= RADEON_STENCIL;
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mask &= ~BUFFER_BIT_STENCIL;
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}
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if ( mask ) {
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if ( swmask ) {
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if (RADEON_DEBUG & RADEON_FALLBACKS)
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fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, mask);
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_swrast_Clear( ctx, mask );
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fprintf(stderr, "%s: swrast clear, mask: %x\n", __FUNCTION__, swmask);
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_swrast_Clear( ctx, swmask );
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}
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if ( !flags )
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if ( !hwmask )
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return;
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radeonUserClear(ctx, orig_mask);
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radeonUserClear(ctx, hwmask);
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}
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void radeonInitIoctlFuncs( struct gl_context *ctx )
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