fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-23 15:30:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

pan/mdg: Prioritize non-moves on VADD/VLUT

Browse source 
This helps reduce ALU cycle count.

total instructions in shared programs: 50507 -> 50501 (-0.01%)
instructions in affected programs: 487 -> 481 (-1.23%)
helped: 7
HURT: 3
helped stats (abs) min: 1 max: 2 x̄: 1.29 x̃: 1
helped stats (rel) min: 1.01% max: 8.33% x̄: 4.11% x̃: 4.35%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.54% max: 4.35% x̄: 2.80% x̃: 2.50%
95% mean confidence interval for instructions value: -1.44 0.24
95% mean confidence interval for instructions %-change: -5.12% 1.04%
Inconclusive result (value mean confidence interval includes 0).

total bundles in shared programs: 25640 -> 25511 (-0.50%)
bundles in affected programs: 5879 -> 5750 (-2.19%)
helped: 67
HURT: 7
helped stats (abs) min: 1 max: 16 x̄: 2.04 x̃: 1
helped stats (rel) min: 0.63% max: 18.18% x̄: 4.11% x̃: 2.12%
HURT stats (abs)   min: 1 max: 2 x̄: 1.14 x̃: 1
HURT stats (rel)   min: 1.75% max: 14.29% x̄: 5.42% x̃: 3.70%
95% mean confidence interval for bundles value: -2.29 -1.20
95% mean confidence interval for bundles %-change: -4.41% -2.00%
Bundles are helped.

total quadwords in shared programs: 40899 -> 40789 (-0.27%)
quadwords in affected programs: 11438 -> 11328 (-0.96%)
helped: 70
HURT: 26
helped stats (abs) min: 1 max: 8 x̄: 2.17 x̃: 1
helped stats (rel) min: 0.42% max: 9.76% x̄: 3.29% x̃: 2.56%
HURT stats (abs)   min: 1 max: 5 x̄: 1.62 x̃: 1
HURT stats (rel)   min: 0.48% max: 9.68% x̄: 3.58% x̃: 1.99%
95% mean confidence interval for quadwords value: -1.60 -0.69
95% mean confidence interval for quadwords %-change: -2.28% -0.58%
Quadwords are helped.

total registers in shared programs: 3916 -> 3911 (-0.13%)
registers in affected programs: 129 -> 124 (-3.88%)
helped: 10
HURT: 5
helped stats (abs) min: 1 max: 2 x̄: 1.10 x̃: 1
helped stats (rel) min: 8.33% max: 25.00% x̄: 12.84% x̃: 9.55%
HURT stats (abs)   min: 1 max: 2 x̄: 1.20 x̃: 1
HURT stats (rel)   min: 11.11% max: 66.67% x̄: 27.30% x̃: 14.29%
95% mean confidence interval for registers value: -0.98 0.32
95% mean confidence interval for registers %-change: -12.67% 13.75%
Inconclusive result (value mean confidence interval includes 0).

total threads in shared programs: 2455 -> 2455 (0.00%)
threads in affected programs: 6 -> 6 (0.00%)
helped: 1
HURT: 1
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs)   min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%

total loops in shared programs: 6 -> 6 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 168 -> 168 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0

total fills in shared programs: 186 -> 186 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5513>
This commit is contained in:
Alyssa Rosenzweig 2020-07-02 13:13:00 -04:00
parent 01e965d312
commit de41c4c103
1 changed files with 18 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
src/panfrost/midgard/midgard_schedule.c
View file

@ -341,6 +341,10 @@ struct midgard_predicate {
unsigned no_mask; unsigned no_mask;
unsigned dest; unsigned dest;
/* For VADD/VLUT whether to only/never schedule imov/fmov instructions
* This allows non-move instructions to get priority on each unit */
bool moves;
/* For load/store: how many pipeline registers are in use? The two /* For load/store: how many pipeline registers are in use? The two
* scheduled instructions cannot use more than the 256-bits of pipeline * scheduled instructions cannot use more than the 256-bits of pipeline
* space available or RA will fail (as it would run out of pipeline * space available or RA will fail (as it would run out of pipeline
@ -605,6 +609,10 @@ mir_choose_instruction(
} }
BITSET_FOREACH_SET(i, worklist, count) { BITSET_FOREACH_SET(i, worklist, count) {
bool is_move = alu &&
(instructions[i]->alu.op == midgard_alu_op_imov ||
instructions[i]->alu.op == midgard_alu_op_fmov);
if ((max_active - i) >= max_distance) if ((max_active - i) >= max_distance)
continue; continue;
@ -617,6 +625,9 @@ mir_choose_instruction(
if (alu && !branch && !(mir_has_unit(instructions[i], unit))) if (alu && !branch && !(mir_has_unit(instructions[i], unit)))
continue; continue;
if ((unit == UNIT_VLUT || unit == UNIT_VADD) && (predicate->moves != is_move))
continue;
if (branch && !instructions[i]->compact_branch) if (branch && !instructions[i]->compact_branch)
continue; continue;
@ -1112,11 +1123,13 @@ mir_schedule_alu(
mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL); mir_choose_alu(&smul, instructions, worklist, len, &predicate, UNIT_SMUL);
predicate.no_mask = writeout ? (1 << 3) : 0; for (unsigned moves = 0; moves < 2; ++moves) {
mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT); predicate.moves = moves;
predicate.no_mask = 0; predicate.no_mask = writeout ? (1 << 3) : 0;
mir_choose_alu(&vlut, instructions, worklist, len, &predicate, UNIT_VLUT);
mir_choose_alu(&vadd, instructions, worklist, len, &predicate, UNIT_VADD); predicate.no_mask = 0;
mir_choose_alu(&vadd, instructions, worklist, len, &predicate, UNIT_VADD);
}
mir_update_worklist(worklist, len, instructions, vlut); mir_update_worklist(worklist, len, instructions, vlut);
mir_update_worklist(worklist, len, instructions, vadd); mir_update_worklist(worklist, len, instructions, vadd);