fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 20:28:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

r300c, r600c: Remove these DRI drivers.

Browse source 
They have been superseded by the gallium equivalents.

Acked-by: Michel Dänzer <michel@daenzer.net>
Acked-by: Alex Deucher <alexdeucher@gmail.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Acked-by: Corbin Simpson <mostawesomedude@gmail.com>
This commit is contained in:
Eric Anholt 2011-10-20 15:06:54 -07:00
parent 2f4c7ebea6
commit de22b9018f
183 changed files with 0 additions and 56328 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/mesa/drivers/dri/r300/Lindent
View file

@ -1,2 +0,0 @@
#!/bin/sh
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs "$@"

68
src/mesa/drivers/dri/r300/Makefile
View file

@ -1,68 +0,0 @@
# src/mesa/drivers/dri/r300/Makefile
TOP = ../../../../..
include $(TOP)/configs/current
LIBNAME = r300_dri.so
include ../Makefile.defines
ifeq ($(RADEON_LDFLAGS),)
CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
endif
RADEON_COMMON_SOURCES = \
radeon_bo_legacy.c \
radeon_buffer_objects.c \
radeon_common_context.c \
radeon_common.c \
radeon_cs_legacy.c \
radeon_dma.c \
radeon_debug.c \
radeon_fbo.c \
radeon_lock.c \
radeon_mipmap_tree.c \
radeon_pixel_read.c \
radeon_queryobj.c \
radeon_span.c \
radeon_texture.c \
radeon_tex_copy.c \
radeon_tile.c
DRIVER_SOURCES = \
radeon_screen.c \
r300_blit.c \
r300_context.c \
r300_draw.c \
r300_cmdbuf.c \
r300_state.c \
r300_render.c \
r300_tex.c \
r300_texstate.c \
r300_vertprog.c \
r300_fragprog_common.c \
r300_shader.c \
radeon_mesa_to_rc.c \
r300_emit.c \
r300_swtcl.c \
$(RADEON_COMMON_SOURCES) \
$(EGL_SOURCES) \
$(CS_SOURCES)
C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
DRIVER_DEFINES = -DRADEON_R300
# -DRADEON_BO_TRACK \
INCLUDES += $(RADEON_CFLAGS)
DRI_LIB_DEPS += $(RADEON_LDFLAGS)
SUBDIRS = compiler
EXTRA_MODULES = compiler/libr300compiler.a
##### TARGETS #####
include ../Makefile.targets

674
src/mesa/drivers/dri/r300/r300_blit.c
View file

@ -1,674 +0,0 @@
/*
* Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "radeon_common.h"
#include "r300_context.h"
#include "r300_blit.h"
#include "r300_cmdbuf.h"
#include "r300_emit.h"
#include "r300_tex.h"
#include "compiler/radeon_compiler.h"
#include "compiler/radeon_opcodes.h"
static void vp_ins_outs(struct r300_vertex_program_compiler *c)
{
c->code->inputs[VERT_ATTRIB_POS] = 0;
c->code->inputs[VERT_ATTRIB_TEX0] = 1;
c->code->outputs[VERT_RESULT_HPOS] = 0;
c->code->outputs[VERT_RESULT_TEX0] = 1;
}
static void fp_allocate_hw_inputs(
struct r300_fragment_program_compiler * c,
void (*allocate)(void * data, unsigned input, unsigned hwreg),
void * mydata)
{
allocate(mydata, FRAG_ATTRIB_TEX0, 0);
}
static void create_vertex_program(struct r300_context *r300)
{
struct r300_vertex_program_compiler compiler;
struct rc_instruction *inst;
memset(&compiler, 0, sizeof(compiler));
rc_init(&compiler.Base);
inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
inst->U.I.Opcode = RC_OPCODE_MOV;
inst->U.I.DstReg.File = RC_FILE_OUTPUT;
inst->U.I.DstReg.Index = VERT_RESULT_HPOS;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.SrcReg[0].Abs = 0;
inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
inst->U.I.SrcReg[0].Index = VERT_ATTRIB_POS;
inst->U.I.SrcReg[0].Negate = 0;
inst->U.I.SrcReg[0].RelAddr = 0;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
inst->U.I.Opcode = RC_OPCODE_MOV;
inst->U.I.DstReg.File = RC_FILE_OUTPUT;
inst->U.I.DstReg.Index = VERT_RESULT_TEX0;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.SrcReg[0].Abs = 0;
inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
inst->U.I.SrcReg[0].Index = VERT_ATTRIB_TEX0;
inst->U.I.SrcReg[0].Negate = 0;
inst->U.I.SrcReg[0].RelAddr = 0;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
compiler.Base.Program.InputsRead = (1 << VERT_ATTRIB_POS) | (1 << VERT_ATTRIB_TEX0);
compiler.RequiredOutputs = compiler.Base.Program.OutputsWritten = (1 << VERT_RESULT_HPOS) | (1 << VERT_RESULT_TEX0);
compiler.SetHwInputOutput = vp_ins_outs;
compiler.code = &r300->blit.vp_code;
compiler.Base.is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
compiler.Base.disable_optimizations = 0;
compiler.Base.has_half_swizzles = 0;
compiler.Base.max_temp_regs = 32;
compiler.Base.max_constants = 256;
compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256;
r3xx_compile_vertex_program(&compiler);
}
static void create_fragment_program(struct r300_context *r300)
{
struct r300_fragment_program_compiler compiler;
struct rc_instruction *inst;
memset(&compiler, 0, sizeof(struct r300_fragment_program_compiler));
rc_init(&compiler.Base);
inst = rc_insert_new_instruction(&compiler.Base, compiler.Base.Program.Instructions.Prev);
inst->U.I.Opcode = RC_OPCODE_TEX;
inst->U.I.TexSrcTarget = RC_TEXTURE_2D;
inst->U.I.TexSrcUnit = 0;
inst->U.I.DstReg.File = RC_FILE_OUTPUT;
inst->U.I.DstReg.Index = FRAG_RESULT_COLOR;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.SrcReg[0].Abs = 0;
inst->U.I.SrcReg[0].File = RC_FILE_INPUT;
inst->U.I.SrcReg[0].Index = FRAG_ATTRIB_TEX0;
inst->U.I.SrcReg[0].Negate = 0;
inst->U.I.SrcReg[0].RelAddr = 0;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.TexSwizzle = RC_SWIZZLE_XYZW;
compiler.Base.Program.InputsRead = (1 << FRAG_ATTRIB_TEX0);
compiler.OutputColor[0] = FRAG_RESULT_COLOR;
compiler.OutputDepth = FRAG_RESULT_DEPTH;
compiler.enable_shadow_ambient = GL_TRUE;
compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
compiler.Base.disable_optimizations = 0;
compiler.Base.has_half_swizzles = 1;
compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32;
compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32;
compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64;
compiler.Base.max_tex_insts = compiler.Base.is_r500 ? 512 : 32;
compiler.code = &r300->blit.fp_code;
compiler.AllocateHwInputs = fp_allocate_hw_inputs;
r3xx_compile_fragment_program(&compiler);
}
void r300_blit_init(struct r300_context *r300)
{
if (r300->options.hw_tcl_enabled)
create_vertex_program(r300);
create_fragment_program(r300);
}
static void r300_emit_tx_setup(struct r300_context *r300,
gl_format mesa_format,
struct radeon_bo *bo,
intptr_t offset,
unsigned width,
unsigned height,
unsigned pitch)
{
int is_r500 = r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
BATCH_LOCALS(&r300->radeon);
assert(is_r500 ? width <= 4096 : width <= 2048);
assert(is_r500 ? height <= 4096 : height <= 2048);
assert(r300TranslateTexFormat(mesa_format) >= 0);
assert(offset % 32 == 0);
BEGIN_BATCH(17);
OUT_BATCH_REGVAL(R300_TX_FILTER0_0,
(R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_S_SHIFT) |
(R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_T_SHIFT) |
(R300_TX_CLAMP_TO_EDGE << R300_TX_WRAP_R_SHIFT) |
R300_TX_MIN_FILTER_MIP_NONE |
R300_TX_MIN_FILTER_NEAREST |
R300_TX_MAG_FILTER_NEAREST |
(0 << 28));
OUT_BATCH_REGVAL(R300_TX_FILTER1_0, 0);
OUT_BATCH_REGVAL(R300_TX_SIZE_0,
(((width - 1) & 0x7ff) << R300_TX_WIDTHMASK_SHIFT) |
(((height - 1) & 0x7ff) << R300_TX_HEIGHTMASK_SHIFT) |
(0 << R300_TX_DEPTHMASK_SHIFT) |
(0 << R300_TX_MAX_MIP_LEVEL_SHIFT) |
R300_TX_SIZE_TXPITCH_EN);
OUT_BATCH_REGVAL(R300_TX_FORMAT_0, r300TranslateTexFormat(mesa_format));
OUT_BATCH_REGVAL(R300_TX_FORMAT2_0,
(pitch - 1) |
(is_r500 && width > 2048 ? R500_TXWIDTH_BIT11 : 0) |
(is_r500 && height > 2048 ? R500_TXHEIGHT_BIT11 : 0));
OUT_BATCH_REGSEQ(R300_TX_OFFSET_0, 1);
OUT_BATCH_RELOC(0, bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
OUT_BATCH_REGSEQ(R300_TX_INVALTAGS, 2);
OUT_BATCH(0);
OUT_BATCH(1);
END_BATCH();
}
#define EASY_US_FORMAT(FMT, C0, C1, C2, C3, SIGN) \
(FMT | R500_C0_SEL_##C0 | R500_C1_SEL_##C1 | \
R500_C2_SEL_##C2 | R500_C3_SEL_##C3 | R500_OUT_SIGN(SIGN))
static uint32_t mesa_format_to_us_format(gl_format mesa_format)
{
switch(mesa_format)
{
case MESA_FORMAT_RGBA8888: // x
return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0);
case MESA_FORMAT_RGB565: // x
case MESA_FORMAT_ARGB1555: // x
case MESA_FORMAT_RGBA8888_REV: // x
return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0);
case MESA_FORMAT_ARGB8888: // x
return EASY_US_FORMAT(R500_OUT_FMT_C4_8, B, G, R, A, 0);
case MESA_FORMAT_ARGB8888_REV:
return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
case MESA_FORMAT_XRGB8888:
return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, R, G, B, 0);
case MESA_FORMAT_RGB332:
return EASY_US_FORMAT(R500_OUT_FMT_C_3_3_2, A, R, G, B, 0);
case MESA_FORMAT_RGBA_FLOAT32:
return EASY_US_FORMAT(R500_OUT_FMT_C4_32_FP, R, G, B, A, 0);
case MESA_FORMAT_RGBA_FLOAT16:
return EASY_US_FORMAT(R500_OUT_FMT_C4_16_FP, R, G, B, A, 0);
case MESA_FORMAT_ALPHA_FLOAT32:
return EASY_US_FORMAT(R500_OUT_FMT_C_32_FP, A, A, A, A, 0);
case MESA_FORMAT_ALPHA_FLOAT16:
return EASY_US_FORMAT(R500_OUT_FMT_C_16_FP, A, A, A, A, 0);
case MESA_FORMAT_SIGNED_RGBA8888:
return EASY_US_FORMAT(R500_OUT_FMT_C4_8, R, G, B, A, 0xf);
case MESA_FORMAT_SIGNED_RGBA8888_REV:
return EASY_US_FORMAT(R500_OUT_FMT_C4_8, A, B, G, R, 0xf);
case MESA_FORMAT_SIGNED_RGBA_16:
return EASY_US_FORMAT(R500_OUT_FMT_C4_16, R, G, B, A, 0xf);
default:
fprintf(stderr, "Unsupported format %s for US output\n", _mesa_get_format_name(mesa_format));
assert(0);
return 0;
}
}
#undef EASY_US_FORMAT
static void r500_emit_fp_setup(struct r300_context *r300,
struct r500_fragment_program_code *fp,
gl_format dst_format)
{
r500_emit_fp(r300, (uint32_t *)fp->inst, (fp->inst_end + 1) * 6, 0, 0, 0);
BATCH_LOCALS(&r300->radeon);
BEGIN_BATCH(10);
OUT_BATCH_REGSEQ(R500_US_CODE_ADDR, 3);
OUT_BATCH(R500_US_CODE_START_ADDR(0) | R500_US_CODE_END_ADDR(fp->inst_end));
OUT_BATCH(R500_US_CODE_RANGE_ADDR(0) | R500_US_CODE_RANGE_SIZE(fp->inst_end));
OUT_BATCH(0);
OUT_BATCH_REGVAL(R500_US_CONFIG, 0);
OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
OUT_BATCH_REGVAL(R500_US_PIXSIZE, fp->max_temp_idx);
END_BATCH();
}
static void r500_emit_rs_setup(struct r300_context *r300)
{
BATCH_LOCALS(&r300->radeon);
BEGIN_BATCH(7);
OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
OUT_BATCH(0);
OUT_BATCH_REGVAL(R500_RS_INST_0,
(0 << R500_RS_INST_TEX_ID_SHIFT) |
(0 << R500_RS_INST_TEX_ADDR_SHIFT) |
R500_RS_INST_TEX_CN_WRITE |
R500_RS_INST_COL_CN_NO_WRITE);
OUT_BATCH_REGVAL(R500_RS_IP_0,
(0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
(1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
(2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
(3 << R500_RS_IP_TEX_PTR_Q_SHIFT));
END_BATCH();
}
static void r300_emit_fp_setup(struct r300_context *r300,
struct r300_fragment_program_code *code,
gl_format dst_format)
{
unsigned i;
BATCH_LOCALS(&r300->radeon);
BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 11);
OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
for (i = 0; i < code->alu.length; i++) {
OUT_BATCH(code->alu.inst[i].rgb_inst);
}
OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
for (i = 0; i < code->alu.length; i++) {
OUT_BATCH(code->alu.inst[i].rgb_addr);
}
OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
for (i = 0; i < code->alu.length; i++) {
OUT_BATCH(code->alu.inst[i].alpha_inst);
}
OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
for (i = 0; i < code->alu.length; i++) {
OUT_BATCH(code->alu.inst[i].alpha_addr);
}
OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length);
OUT_BATCH_TABLE(code->tex.inst, code->tex.length);
OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX);
OUT_BATCH(code->pixsize);
OUT_BATCH(code->code_offset);
OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
OUT_BATCH_TABLE(code->code_addr, 4);
OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
END_BATCH();
}
static void r300_emit_rs_setup(struct r300_context *r300)
{
BATCH_LOCALS(&r300->radeon);
BEGIN_BATCH(7);
OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
OUT_BATCH(0);
OUT_BATCH_REGVAL(R300_RS_INST_0,
R300_RS_INST_TEX_ID(0) |
R300_RS_INST_TEX_ADDR(0) |
R300_RS_INST_TEX_CN_WRITE);
OUT_BATCH_REGVAL(R300_RS_IP_0,
R300_RS_TEX_PTR(0) |
R300_RS_SEL_S(R300_RS_SEL_C0) |
R300_RS_SEL_T(R300_RS_SEL_C1) |
R300_RS_SEL_R(R300_RS_SEL_K0) |
R300_RS_SEL_Q(R300_RS_SEL_K1));
END_BATCH();
}
static void emit_pvs_setup(struct r300_context *r300,
uint32_t *vp_code,
unsigned vp_len)
{
BATCH_LOCALS(&r300->radeon);
r300_emit_vpu(r300, vp_code, vp_len * 4, R300_PVS_CODE_START);
BEGIN_BATCH(4);
OUT_BATCH_REGSEQ(R300_VAP_PVS_CODE_CNTL_0, 3);
OUT_BATCH((0 << R300_PVS_FIRST_INST_SHIFT) |
((vp_len - 1) << R300_PVS_XYZW_VALID_INST_SHIFT) |
((vp_len - 1)<< R300_PVS_LAST_INST_SHIFT));
OUT_BATCH(0);
OUT_BATCH((vp_len - 1) << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
END_BATCH();
}
static void emit_vap_setup(struct r300_context *r300)
{
int tex_offset;
BATCH_LOCALS(&r300->radeon);
if (r300->options.hw_tcl_enabled)
tex_offset = 1;
else
tex_offset = 6;
BEGIN_BATCH(12);
OUT_BATCH_REGSEQ(R300_SE_VTE_CNTL, 2);
OUT_BATCH(R300_VTX_XY_FMT | R300_VTX_Z_FMT);
OUT_BATCH(4);
OUT_BATCH_REGVAL(R300_VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_0,
((R300_DATA_TYPE_FLOAT_2 | (0 << R300_DST_VEC_LOC_SHIFT)) << 0) |
(((tex_offset << R300_DST_VEC_LOC_SHIFT) | R300_DATA_TYPE_FLOAT_2 | R300_LAST_VEC) << 16));
OUT_BATCH_REGVAL(R300_VAP_PROG_STREAM_CNTL_EXT_0,
((((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
(0xf << R300_WRITE_ENA_SHIFT) ) << 0) |
(((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_SHIFT) |
(R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ZERO << R300_SWIZZLE_SELECT_Z_SHIFT) |
(R300_SWIZZLE_SELECT_FP_ONE << R300_SWIZZLE_SELECT_W_SHIFT) |
(0xf << R300_WRITE_ENA_SHIFT) ) << 16) ) );
OUT_BATCH_REGSEQ(R300_VAP_OUTPUT_VTX_FMT_0, 2);
OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT);
OUT_BATCH(R300_VAP_OUTPUT_VTX_FMT_1__4_COMPONENTS);
END_BATCH();
}
static GLboolean validate_buffers(struct r300_context *r300,
struct radeon_bo *src_bo,
struct radeon_bo *dst_bo)
{
int ret;
radeon_cs_space_reset_bos(r300->radeon.cmdbuf.cs);
ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
if (ret)
return GL_FALSE;
ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs,
dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT);
if (ret)
return GL_FALSE;
return GL_TRUE;
}
/**
* Calculate texcoords for given image region.
* Output values are [minx, maxx, miny, maxy]
*/
static void calc_tex_coords(float img_width, float img_height,
float x, float y,
float reg_width, float reg_height,
unsigned flip_y, float *buf)
{
buf[0] = x / img_width;
buf[1] = buf[0] + reg_width / img_width;
buf[2] = y / img_height;
buf[3] = buf[2] + reg_height / img_height;
if (flip_y)
{
buf[2] = 1.0 - buf[2];
buf[3] = 1.0 - buf[3];
}
}
static void emit_draw_packet(struct r300_context *r300,
unsigned src_width, unsigned src_height,
unsigned src_x_offset, unsigned src_y_offset,
unsigned dst_x_offset, unsigned dst_y_offset,
unsigned reg_width, unsigned reg_height,
unsigned flip_y)
{
float texcoords[4];
calc_tex_coords(src_width, src_height,
src_x_offset, src_y_offset,
reg_width, reg_height,
flip_y, texcoords);
float verts[] = { dst_x_offset, dst_y_offset,
texcoords[0], texcoords[2],
dst_x_offset, dst_y_offset + reg_height,
texcoords[0], texcoords[3],
dst_x_offset + reg_width, dst_y_offset + reg_height,
texcoords[1], texcoords[3],
dst_x_offset + reg_width, dst_y_offset,
texcoords[1], texcoords[2] };
BATCH_LOCALS(&r300->radeon);
BEGIN_BATCH(19);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_IMMD_2, 16);
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED |
(4 << 16) | R300_VAP_VF_CNTL__PRIM_QUADS);
OUT_BATCH_TABLE(verts, 16);
END_BATCH();
}
static void other_stuff(struct r300_context *r300)
{
BATCH_LOCALS(&r300->radeon);
BEGIN_BATCH(13);
OUT_BATCH_REGVAL(R300_GA_POLY_MODE,
R300_GA_POLY_MODE_FRONT_PTYPE_TRI | R300_GA_POLY_MODE_BACK_PTYPE_TRI);
OUT_BATCH_REGVAL(R300_SU_CULL_MODE, R300_FRONT_FACE_CCW);
OUT_BATCH_REGVAL(R300_FG_FOG_BLEND, 0);
OUT_BATCH_REGVAL(R300_FG_ALPHA_FUNC, 0);
OUT_BATCH_REGSEQ(R300_RB3D_CBLEND, 2);
OUT_BATCH(0x0);
OUT_BATCH(0x0);
OUT_BATCH_REGVAL(R300_ZB_CNTL, 0);
END_BATCH();
if (r300->options.hw_tcl_enabled) {
BEGIN_BATCH(2);
OUT_BATCH_REGVAL(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE);
END_BATCH();
}
}
static void emit_cb_setup(struct r300_context *r300,
struct radeon_bo *bo,
intptr_t offset,
gl_format mesa_format,
unsigned pitch,
unsigned width,
unsigned height)
{
BATCH_LOCALS(&r300->radeon);
unsigned x1, y1, x2, y2;
x1 = 0;
y1 = 0;
x2 = width - 1;
y2 = height - 1;
if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
x1 += R300_SCISSORS_OFFSET;
y1 += R300_SCISSORS_OFFSET;
x2 += R300_SCISSORS_OFFSET;
y2 += R300_SCISSORS_OFFSET;
}
r300_emit_cb_setup(r300, bo, offset, mesa_format,
_mesa_get_format_bytes(mesa_format),
_mesa_format_row_stride(mesa_format, pitch));
BEGIN_BATCH_NO_AUTOSTATE(5);
OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
OUT_BATCH_REGVAL(R300_RB3D_CCTL, 0);
END_BATCH();
}
unsigned r300_check_blit(gl_format dst_format)
{
switch (dst_format) {
case MESA_FORMAT_RGB565:
case MESA_FORMAT_ARGB1555:
case MESA_FORMAT_RGBA8888:
case MESA_FORMAT_RGBA8888_REV:
case MESA_FORMAT_ARGB8888:
case MESA_FORMAT_ARGB8888_REV:
case MESA_FORMAT_XRGB8888:
break;
default:
return 0;
}
if (_mesa_get_format_bits(dst_format, GL_DEPTH_BITS) > 0)
return 0;
return 1;
}
/**
* Copy a region of [@a width x @a height] pixels from source buffer
* to destination buffer.
* @param[in] r300 r300 context
* @param[in] src_bo source radeon buffer object
* @param[in] src_offset offset of the source image in the @a src_bo
* @param[in] src_mesaformat source image format
* @param[in] src_pitch aligned source image width
* @param[in] src_width source image width
* @param[in] src_height source image height
* @param[in] src_x_offset x offset in the source image
* @param[in] src_y_offset y offset in the source image
* @param[in] dst_bo destination radeon buffer object
* @param[in] dst_offset offset of the destination image in the @a dst_bo
* @param[in] dst_mesaformat destination image format
* @param[in] dst_pitch aligned destination image width
* @param[in] dst_width destination image width
* @param[in] dst_height destination image height
* @param[in] dst_x_offset x offset in the destination image
* @param[in] dst_y_offset y offset in the destination image
* @param[in] width region width
* @param[in] height region height
* @param[in] flip_y set if y coords of the source image need to be flipped
*/
unsigned r300_blit(struct gl_context *ctx,
struct radeon_bo *src_bo,
intptr_t src_offset,
gl_format src_mesaformat,
unsigned src_pitch,
unsigned src_width,
unsigned src_height,
unsigned src_x_offset,
unsigned src_y_offset,
struct radeon_bo *dst_bo,
intptr_t dst_offset,
gl_format dst_mesaformat,
unsigned dst_pitch,
unsigned dst_width,
unsigned dst_height,
unsigned dst_x_offset,
unsigned dst_y_offset,
unsigned reg_width,
unsigned reg_height,
unsigned flip_y)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
if (!r300_check_blit(dst_mesaformat))
return 0;
/* Make sure that colorbuffer has even width - hw limitation */
if (dst_pitch % 2 > 0)
++dst_pitch;
/* Need to clamp the region size to make sure
* we don't read outside of the source buffer
* or write outside of the destination buffer.
*/
if (reg_width + src_x_offset > src_width)
reg_width = src_width - src_x_offset;
if (reg_height + src_y_offset > src_height)
reg_height = src_height - src_y_offset;
if (reg_width + dst_x_offset > dst_width)
reg_width = dst_width - dst_x_offset;
if (reg_height + dst_y_offset > dst_height)
reg_height = dst_height - dst_y_offset;
if (src_bo == dst_bo) {
return 0;
}
if (src_offset % 32 || dst_offset % 32) {
return GL_FALSE;
}
if (0) {
fprintf(stderr, "src: size [%d x %d], pitch %d, "
"offset [%d x %d], format %s, bo %p\n",
src_width, src_height, src_pitch,
src_x_offset, src_y_offset,
_mesa_get_format_name(src_mesaformat),
src_bo);
fprintf(stderr, "dst: pitch %d, offset[%d x %d], format %s, bo %p\n",
dst_pitch, dst_x_offset, dst_y_offset,
_mesa_get_format_name(dst_mesaformat), dst_bo);
fprintf(stderr, "region: %d x %d\n", reg_width, reg_height);
}
/* Flush is needed to make sure that source buffer has correct data */
radeonFlush(r300->radeon.glCtx);
if (!validate_buffers(r300, src_bo, dst_bo))
return 0;
rcommonEnsureCmdBufSpace(&r300->radeon, 200, __FUNCTION__);
other_stuff(r300);
r300_emit_tx_setup(r300, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat);
r500_emit_rs_setup(r300);
} else {
r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300, dst_mesaformat);
r300_emit_rs_setup(r300);
}
if (r300->options.hw_tcl_enabled)
emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
emit_vap_setup(r300);
emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
emit_draw_packet(r300, src_width, src_height,
src_x_offset, src_y_offset,
dst_x_offset, dst_y_offset,
reg_width, reg_height,
flip_y);
r300EmitCacheFlush(r300);
radeonFlush(r300->radeon.glCtx);
return 1;
}

56
src/mesa/drivers/dri/r300/r300_blit.h
View file

@ -1,56 +0,0 @@
/*
* Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef R300_BLIT_H
#define R300_BLIT_H
void r300_blit_init(struct r300_context *r300);
unsigned r300_check_blit(gl_format mesa_format);
unsigned r300_blit(struct gl_context *ctx,
struct radeon_bo *src_bo,
intptr_t src_offset,
gl_format src_mesaformat,
unsigned src_pitch,
unsigned src_width,
unsigned src_height,
unsigned src_x_offset,
unsigned src_y_offset,
struct radeon_bo *dst_bo,
intptr_t dst_offset,
gl_format dst_mesaformat,
unsigned dst_pitch,
unsigned dst_width,
unsigned dst_height,
unsigned dst_x_offset,
unsigned dst_y_offset,
unsigned reg_width,
unsigned reg_height,
unsigned flip_y);
#endif // R300_BLIT_H

907
src/mesa/drivers/dri/r300/r300_cmdbuf.c
View file

@ -1,907 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file
*
* \author Nicolai Haehnle <prefect_@gmx.net>
*/
#include "main/glheader.h"
#include "main/state.h"
#include "main/imports.h"
#include "main/macros.h"
#include "main/context.h"
#include "main/simple_list.h"
#include "drm.h"
#include "radeon_drm.h"
#include "r300_context.h"
#include "r300_reg.h"
#include "r300_cmdbuf.h"
#include "r300_emit.h"
#include "radeon_bocs_wrapper.h"
#include "radeon_mipmap_tree.h"
#include "radeon_queryobj.h"
/** # of dwords reserved for additional instructions that may need to be written
* during flushing.
*/
#define SPACE_FOR_FLUSHING 4
static unsigned packet0_count(r300ContextPtr r300, uint32_t *pkt)
{
if (r300->radeon.radeonScreen->kernel_mm) {
return ((((*pkt) >> 16) & 0x3FFF) + 1);
} else {
drm_r300_cmd_header_t *t = (drm_r300_cmd_header_t*)pkt;
return t->packet0.count;
}
}
#define vpu_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->vpu.count)
#define r500fp_count(ptr) (((drm_r300_cmd_header_t*)(ptr))->r500fp.count)
static int check_vpu(struct gl_context *ctx, struct radeon_state_atom *atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
int cnt;
int extra = 1;
cnt = vpu_count(atom->cmd);
if (r300->radeon.radeonScreen->kernel_mm) {
extra = 3;
}
return cnt ? (cnt * 4) + extra : 0;
}
static int check_vpp(struct gl_context *ctx, struct radeon_state_atom *atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
int cnt;
int extra = 1;
if (r300->radeon.radeonScreen->kernel_mm) {
cnt = r300->selected_vp->code.constants.Count * 4;
extra = 3;
} else {
cnt = vpu_count(atom->cmd);
extra = 1;
}
return cnt ? (cnt * 4) + extra : 0;
}
void r300_emit_vpu(struct r300_context *r300,
uint32_t *data,
unsigned len,
uint32_t addr)
{
BATCH_LOCALS(&r300->radeon);
BEGIN_BATCH_NO_AUTOSTATE(3 + len);
OUT_BATCH_REGVAL(R300_VAP_PVS_VECTOR_INDX_REG, addr);
OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, len-1) | RADEON_ONE_REG_WR);
OUT_BATCH_TABLE(data, len);
END_BATCH();
}
static void emit_vpu_state(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
drm_r300_cmd_header_t cmd;
uint32_t addr;
cmd.u = atom->cmd[0];
addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
r300_emit_vpu(r300, &atom->cmd[1], vpu_count(atom->cmd) * 4, addr);
}
static void emit_vpp_state(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
drm_r300_cmd_header_t cmd;
uint32_t addr;
cmd.u = atom->cmd[0];
addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
r300_emit_vpu(r300, &atom->cmd[1], r300->selected_vp->code.constants.Count * 4, addr);
}
void r500_emit_fp(struct r300_context *r300,
uint32_t *data,
unsigned len,
uint32_t addr,
unsigned type,
unsigned clamp)
{
BATCH_LOCALS(&r300->radeon);
addr |= (type << 16);
addr |= (clamp << 17);
BEGIN_BATCH_NO_AUTOSTATE(len + 3);
OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_INDEX, 0));
OUT_BATCH(addr);
OUT_BATCH(CP_PACKET0(R500_GA_US_VECTOR_DATA, len-1) | RADEON_ONE_REG_WR);
OUT_BATCH_TABLE(data, len);
END_BATCH();
}
static void emit_r500fp_atom(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
drm_r300_cmd_header_t cmd;
uint32_t addr, count;
int type, clamp;
cmd.u = atom->cmd[0];
addr = ((cmd.r500fp.adrhi_flags & 1) << 8) | cmd.r500fp.adrlo;
type = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
clamp = !!(cmd.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
if (type) {
count = r500fp_count(atom->cmd) * 4;
} else {
count = r500fp_count(atom->cmd) * 6;
}
r500_emit_fp(r300, &atom->cmd[1], count, addr, type, clamp);
}
static int check_tex_offsets(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
int dw = 0, i;
if (atom->cmd[0] == CP_PACKET2) {
return dw;
}
for(i = 0; i < numtmus; ++i) {
radeonTexObj *t = r300->hw.textures[i];
if (!t && !r300->radeon.radeonScreen->kernel_mm) {
dw += 0;
} else if (t && t->image_override && !t->bo) {
if (!r300->radeon.radeonScreen->kernel_mm)
dw += 2;
} else
dw += 4;
}
return dw;
}
static void emit_tex_offsets(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
int numtmus = packet0_count(r300, r300->hw.tex.offset.cmd);
int i;
for(i = 0; i < numtmus; ++i) {
radeonTexObj *t = r300->hw.textures[i];
if (t && !t->image_override) {
BEGIN_BATCH_NO_AUTOSTATE(4);
OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
END_BATCH();
} else if (!t) {
/* Texture unit hasn't a texture bound.
* We assign the current color buffer as a fakery to make
* KIL work on KMS (without it, the CS checker will complain).
*/
if (r300->radeon.radeonScreen->kernel_mm) {
struct radeon_renderbuffer *rrb = radeon_get_colorbuffer(&r300->radeon);
if (rrb && rrb->bo) {
BEGIN_BATCH_NO_AUTOSTATE(4);
OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_BATCH_RELOC(0, rrb->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
END_BATCH();
}
}
} else { /* override cases */
if (t->bo) {
BEGIN_BATCH_NO_AUTOSTATE(4);
OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
END_BATCH();
} else if (!r300->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGSEQ(R300_TX_OFFSET_0 + (i * 4), 1);
OUT_BATCH(t->override_offset);
END_BATCH();
} else {
/* Texture unit hasn't a texture bound nothings to do */
}
}
}
}
void r300_emit_scissor(struct gl_context *ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
unsigned x1, y1, x2, y2;
struct radeon_renderbuffer *rrb;
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
return;
}
rrb = radeon_get_colorbuffer(&r300->radeon);
if (!rrb || !rrb->bo) {
fprintf(stderr, "no rrb\n");
return;
}
if (r300->radeon.state.scissor.enabled) {
x1 = r300->radeon.state.scissor.rect.x1;
y1 = r300->radeon.state.scissor.rect.y1;
x2 = r300->radeon.state.scissor.rect.x2;
y2 = r300->radeon.state.scissor.rect.y2;
} else {
x1 = 0;
y1 = 0;
x2 = rrb->base.Width - 1;
y2 = rrb->base.Height - 1;
}
if (r300->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV515) {
x1 += R300_SCISSORS_OFFSET;
y1 += R300_SCISSORS_OFFSET;
x2 += R300_SCISSORS_OFFSET;
y2 += R300_SCISSORS_OFFSET;
}
BEGIN_BATCH_NO_AUTOSTATE(3);
OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
OUT_BATCH((x1 << R300_SCISSORS_X_SHIFT)|(y1 << R300_SCISSORS_Y_SHIFT));
OUT_BATCH((x2 << R300_SCISSORS_X_SHIFT)|(y2 << R300_SCISSORS_Y_SHIFT));
END_BATCH();
}
static int check_cb_offset(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
uint32_t dw = 6 + 3 + 16;
if (r300->radeon.radeonScreen->kernel_mm)
dw += 2;
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
dw -= 3 + 16;
}
return dw;
}
static void emit_scissor(struct r300_context *r300,
unsigned width,
unsigned height)
{
int i;
BATCH_LOCALS(&r300->radeon);
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
BEGIN_BATCH_NO_AUTOSTATE(3);
OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
OUT_BATCH(0);
OUT_BATCH(((width - 1) << R300_SCISSORS_X_SHIFT) |
((height - 1) << R300_SCISSORS_Y_SHIFT));
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(16);
for (i = 0; i < 4; i++) {
OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
OUT_BATCH((0 << R300_CLIPRECT_X_SHIFT) | (0 << R300_CLIPRECT_Y_SHIFT));
OUT_BATCH(((width - 1) << R300_CLIPRECT_X_SHIFT) | ((height - 1) << R300_CLIPRECT_Y_SHIFT));
}
OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
OUT_BATCH(0xAAAA);
OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
OUT_BATCH(0xffffff);
END_BATCH();
} else {
BEGIN_BATCH_NO_AUTOSTATE(3);
OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
OUT_BATCH((R300_SCISSORS_OFFSET << R300_SCISSORS_X_SHIFT) |
(R300_SCISSORS_OFFSET << R300_SCISSORS_Y_SHIFT));
OUT_BATCH(((width + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_X_SHIFT) |
((height + R300_SCISSORS_OFFSET - 1) << R300_SCISSORS_Y_SHIFT));
END_BATCH();
BEGIN_BATCH_NO_AUTOSTATE(16);
for (i = 0; i < 4; i++) {
OUT_BATCH_REGSEQ(R300_SC_CLIPRECT_TL_0 + (i * 8), 2);
OUT_BATCH((R300_SCISSORS_OFFSET << R300_CLIPRECT_X_SHIFT) | (R300_SCISSORS_OFFSET << R300_CLIPRECT_Y_SHIFT));
OUT_BATCH(((R300_SCISSORS_OFFSET + width - 1) << R300_CLIPRECT_X_SHIFT) |
((R300_SCISSORS_OFFSET + height - 1) << R300_CLIPRECT_Y_SHIFT));
}
OUT_BATCH_REGSEQ(R300_SC_CLIP_RULE, 1);
OUT_BATCH(0xAAAA);
OUT_BATCH_REGSEQ(R300_SC_SCREENDOOR, 1);
OUT_BATCH(0xffffff);
END_BATCH();
}
}
void r300_emit_cb_setup(struct r300_context *r300,
struct radeon_bo *bo,
uint32_t offset,
GLuint format,
unsigned cpp,
unsigned pitch)
{
BATCH_LOCALS(&r300->radeon);
uint32_t cbpitch = pitch / cpp;
uint32_t dw = 6;
assert(offset % 32 == 0);
switch (format) {
case MESA_FORMAT_SL8:
case MESA_FORMAT_A8:
case MESA_FORMAT_L8:
case MESA_FORMAT_I8:
cbpitch |= R300_COLOR_FORMAT_I8;
break;
case MESA_FORMAT_RGB565:
case MESA_FORMAT_RGB565_REV:
cbpitch |= R300_COLOR_FORMAT_RGB565;
break;
case MESA_FORMAT_ARGB4444:
case MESA_FORMAT_ARGB4444_REV:
cbpitch |= R300_COLOR_FORMAT_ARGB4444;
break;
case MESA_FORMAT_RGBA5551:
case MESA_FORMAT_ARGB1555:
case MESA_FORMAT_ARGB1555_REV:
cbpitch |= R300_COLOR_FORMAT_ARGB1555;
break;
case MESA_FORMAT_RGBA8888:
case MESA_FORMAT_RGBA8888_REV:
case MESA_FORMAT_XRGB8888:
case MESA_FORMAT_ARGB8888:
case MESA_FORMAT_XRGB8888_REV:
case MESA_FORMAT_ARGB8888_REV:
case MESA_FORMAT_SRGBA8:
case MESA_FORMAT_SARGB8:
cbpitch |= R300_COLOR_FORMAT_ARGB8888;
break;
default:
_mesa_problem(r300->radeon.glCtx, "unexpected format in emit_cb_offset()");
break;
}
if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
cbpitch |= R300_COLOR_TILE_ENABLE;
if (r300->radeon.radeonScreen->kernel_mm)
dw += 2;
BEGIN_BATCH_NO_AUTOSTATE(dw);
OUT_BATCH_REGSEQ(R300_RB3D_COLOROFFSET0, 1);
OUT_BATCH_RELOC(offset, bo, offset, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGSEQ(R300_RB3D_COLORPITCH0, 1);
if (!r300->radeon.radeonScreen->kernel_mm)
OUT_BATCH(cbpitch);
else
OUT_BATCH_RELOC(cbpitch, bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
}
static void emit_cb_offset_atom(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
struct radeon_renderbuffer *rrb;
uint32_t offset = r300->radeon.state.color.draw_offset;
rrb = radeon_get_colorbuffer(&r300->radeon);
if (!rrb || !rrb->bo) {
fprintf(stderr, "no rrb\n");
return;
}
if (RADEON_DEBUG & RADEON_STATE)
fprintf(stderr,"rrb is %p %d %dx%d\n", rrb, offset, rrb->base.Width, rrb->base.Height);
r300_emit_cb_setup(r300, rrb->bo, offset, rrb->base.Format, rrb->cpp, rrb->pitch);
if (r300->radeon.radeonScreen->driScreen->dri2.enabled) {
emit_scissor(r300, rrb->base.Width, rrb->base.Height);
}
}
static int check_zb_offset(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
uint32_t dw;
dw = 6;
if (r300->radeon.radeonScreen->kernel_mm)
dw += 2;
return dw;
}
static void emit_zb_offset(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
struct radeon_renderbuffer *rrb;
uint32_t zbpitch;
uint32_t dw = atom->check(ctx, atom);
rrb = radeon_get_depthbuffer(&r300->radeon);
if (!rrb)
return;
zbpitch = (rrb->pitch / rrb->cpp);
if (!r300->radeon.radeonScreen->kernel_mm) {
if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE) {
zbpitch |= R300_DEPTHMACROTILE_ENABLE;
}
if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
zbpitch |= R300_DEPTHMICROTILE_TILED;
}
}
BEGIN_BATCH_NO_AUTOSTATE(dw);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHPITCH, 1);
if (!r300->radeon.radeonScreen->kernel_mm)
OUT_BATCH(zbpitch);
else
OUT_BATCH_RELOC(cbpitch, rrb->bo, zbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
END_BATCH();
}
static void emit_zstencil_format(struct gl_context *ctx, struct radeon_state_atom * atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
BATCH_LOCALS(&r300->radeon);
struct radeon_renderbuffer *rrb;
uint32_t format = 0;
rrb = radeon_get_depthbuffer(&r300->radeon);
if (!rrb)
format = 0;
else {
if (rrb->cpp == 2)
format = R300_DEPTHFORMAT_16BIT_INT_Z;
else if (rrb->cpp == 4)
format = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
}
BEGIN_BATCH_NO_AUTOSTATE(atom->cmd_size);
OUT_BATCH(atom->cmd[0]);
atom->cmd[1] &= ~0xf;
atom->cmd[1] |= format;
OUT_BATCH(atom->cmd[1]);
OUT_BATCH(atom->cmd[2]);
OUT_BATCH(atom->cmd[3]);
OUT_BATCH(atom->cmd[4]);
END_BATCH();
}
static int check_never(struct gl_context *ctx, struct radeon_state_atom *atom)
{
return 0;
}
static int check_always(struct gl_context *ctx, struct radeon_state_atom *atom)
{
return atom->cmd_size;
}
static int check_variable(struct gl_context *ctx, struct radeon_state_atom *atom)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
int cnt;
if (atom->cmd[0] == CP_PACKET2) {
return 0;
}
cnt = packet0_count(r300, atom->cmd);
return cnt ? cnt + 1 : 0;
}
static int check_r500fp(struct gl_context *ctx, struct radeon_state_atom *atom)
{
int cnt;
r300ContextPtr r300 = R300_CONTEXT(ctx);
int extra = 1;
cnt = r500fp_count(atom->cmd);
if (r300->radeon.radeonScreen->kernel_mm)
extra = 3;
return cnt ? (cnt * 6) + extra : 0;
}
static int check_r500fp_const(struct gl_context *ctx, struct radeon_state_atom *atom)
{
int cnt;
r300ContextPtr r300 = R300_CONTEXT(ctx);
int extra = 1;
cnt = r500fp_count(atom->cmd);
if (r300->radeon.radeonScreen->kernel_mm)
extra = 3;
cnt = r500fp_count(atom->cmd);
return cnt ? (cnt * 4) + extra : 0;
}
#define ALLOC_STATE( ATOM, CHK, SZ, IDX ) \
do { \
r300->hw.ATOM.cmd_size = (SZ); \
r300->hw.ATOM.cmd = (uint32_t*)CALLOC((SZ) * sizeof(uint32_t)); \
r300->hw.ATOM.name = #ATOM; \
r300->hw.ATOM.idx = (IDX); \
r300->hw.ATOM.check = check_##CHK; \
r300->hw.ATOM.dirty = GL_FALSE; \
r300->radeon.hw.max_state_size += (SZ); \
insert_at_tail(&r300->radeon.hw.atomlist, &r300->hw.ATOM); \
} while (0)
/**
* Allocate memory for the command buffer and initialize the state atom
* list. Note that the initial hardware state is set by r300InitState().
*/
void r300InitCmdBuf(r300ContextPtr r300)
{
int mtu;
int has_tcl;
int is_r500 = 0;
has_tcl = r300->options.hw_tcl_enabled;
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515)
is_r500 = 1;
r300->radeon.hw.max_state_size = 2 + 2; /* reserve extra space for WAIT_IDLE and tex cache flush */
mtu = r300->radeon.glCtx->Const.MaxTextureUnits;
if (RADEON_DEBUG & RADEON_TEXTURE) {
fprintf(stderr, "Using %d maximum texture units..\n", mtu);
}
/* Setup the atom linked list */
make_empty_list(&r300->radeon.hw.atomlist);
r300->radeon.hw.atomlist.name = "atom-list";
/* Initialize state atoms */
ALLOC_STATE(vpt, always, R300_VPT_CMDSIZE, 0);
r300->hw.vpt.cmd[R300_VPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VPORT_XSCALE, 6);
ALLOC_STATE(vap_cntl, always, R300_VAP_CNTL_SIZE, 0);
r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_STATE_FLUSH_REG, 1);
r300->hw.vap_cntl.cmd[R300_VAP_CNTL_FLUSH_1] = 0;
r300->hw.vap_cntl.cmd[R300_VAP_CNTL_CMD] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL, 1);
if (is_r500 && !r300->radeon.radeonScreen->kernel_mm) {
ALLOC_STATE(vap_index_offset, always, 2, 0);
r300->hw.vap_index_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_VAP_INDEX_OFFSET, 1);
r300->hw.vap_index_offset.cmd[1] = 0;
}
ALLOC_STATE(vte, always, 3, 0);
r300->hw.vte.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SE_VTE_CNTL, 2);
ALLOC_STATE(vap_vf_max_vtx_indx, always, 3, 0);
r300->hw.vap_vf_max_vtx_indx.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VF_MAX_VTX_INDX, 2);
ALLOC_STATE(vap_cntl_status, always, 2, 0);
r300->hw.vap_cntl_status.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CNTL_STATUS, 1);
ALLOC_STATE(vir[0], variable, R300_VIR_CMDSIZE, 0);
r300->hw.vir[0].cmd[R300_VIR_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_0, 1);
ALLOC_STATE(vir[1], variable, R300_VIR_CMDSIZE, 1);
r300->hw.vir[1].cmd[R300_VIR_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PROG_STREAM_CNTL_EXT_0, 1);
ALLOC_STATE(vic, always, R300_VIC_CMDSIZE, 0);
r300->hw.vic.cmd[R300_VIC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_VTX_STATE_CNTL, 2);
ALLOC_STATE(vap_psc_sgn_norm_cntl, always, 2, 0);
r300->hw.vap_psc_sgn_norm_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PSC_SGN_NORM_CNTL, SGN_NORM_ZERO_CLAMP_MINUS_ONE);
if (has_tcl) {
ALLOC_STATE(vap_clip_cntl, always, 2, 0);
r300->hw.vap_clip_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_CLIP_CNTL, 1);
ALLOC_STATE(vap_clip, always, 5, 0);
r300->hw.vap_clip.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_VAP_GB_VERT_CLIP_ADJ, 4);
ALLOC_STATE(vap_pvs_vtx_timeout_reg, always, 2, 0);
r300->hw.vap_pvs_vtx_timeout_reg.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, VAP_PVS_VTX_TIMEOUT_REG, 1);
}
ALLOC_STATE(vof, always, R300_VOF_CMDSIZE, 0);
r300->hw.vof.cmd[R300_VOF_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_OUTPUT_VTX_FMT_0, 2);
if (has_tcl) {
ALLOC_STATE(pvs, always, R300_PVS_CMDSIZE, 0);
r300->hw.pvs.cmd[R300_PVS_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_VAP_PVS_CODE_CNTL_0, 3);
}
ALLOC_STATE(gb_enable, always, 2, 0);
r300->hw.gb_enable.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_ENABLE, 1);
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
ALLOC_STATE(gb_misc, always, R300_GB_MISC_CMDSIZE, 0);
} else {
ALLOC_STATE(gb_misc, never, R300_GB_MISC_CMDSIZE, 0);
}
r300->hw.gb_misc.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GB_MSPOS0, 3);
ALLOC_STATE(gb_misc2, always, R300_GB_MISC2_CMDSIZE, 0);
r300->hw.gb_misc2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x401C, 2);
ALLOC_STATE(txe, always, R300_TXE_CMDSIZE, 0);
r300->hw.txe.cmd[R300_TXE_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_ENABLE, 1);
ALLOC_STATE(ga_point_s0, always, 5, 0);
r300->hw.ga_point_s0.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_S0, 4);
ALLOC_STATE(ga_triangle_stipple, always, 2, 0);
r300->hw.ga_triangle_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_TRIANGLE_STIPPLE, 1);
ALLOC_STATE(ps, always, R300_PS_CMDSIZE, 0);
r300->hw.ps.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_SIZE, 1);
ALLOC_STATE(ga_point_minmax, always, 4, 0);
r300->hw.ga_point_minmax.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POINT_MINMAX, 3);
ALLOC_STATE(lcntl, always, 2, 0);
r300->hw.lcntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_CNTL, 1);
ALLOC_STATE(ga_line_stipple, always, 4, 0);
r300->hw.ga_line_stipple.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_LINE_STIPPLE_VALUE, 3);
if (!r300->radeon.radeonScreen->driScreen->dri2.enabled) {
ALLOC_STATE(shade, always, 2, 0);
} else {
ALLOC_STATE(shade, never, 2, 0);
}
r300->hw.shade.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_ENHANCE, 1);
ALLOC_STATE(shade2, always, 4, 0);
r300->hw.shade2.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4278, 3);
ALLOC_STATE(polygon_mode, always, 4, 0);
r300->hw.polygon_mode.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_POLY_MODE, 3);
ALLOC_STATE(fogp, always, 3, 0);
r300->hw.fogp.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_GA_FOG_SCALE, 2);
ALLOC_STATE(zbias_cntl, always, 2, 0);
r300->hw.zbias_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_TEX_WRAP, 1);
ALLOC_STATE(zbs, always, R300_ZBS_CMDSIZE, 0);
r300->hw.zbs.cmd[R300_ZBS_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_FRONT_SCALE, 4);
ALLOC_STATE(occlusion_cntl, always, 2, 0);
r300->hw.occlusion_cntl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_POLY_OFFSET_ENABLE, 1);
ALLOC_STATE(cul, always, R300_CUL_CMDSIZE, 0);
r300->hw.cul.cmd[R300_CUL_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_CULL_MODE, 1);
ALLOC_STATE(su_depth_scale, always, 3, 0);
r300->hw.su_depth_scale.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_DEPTH_SCALE, 2);
ALLOC_STATE(rc, always, R300_RC_CMDSIZE, 0);
r300->hw.rc.cmd[R300_RC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_COUNT, 2);
if (is_r500) {
ALLOC_STATE(ri, variable, R500_RI_CMDSIZE, 0);
r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_IP_0, 16);
ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_RS_INST_0, 1);
} else {
ALLOC_STATE(ri, variable, R300_RI_CMDSIZE, 0);
r300->hw.ri.cmd[R300_RI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_IP_0, 8);
ALLOC_STATE(rr, variable, R300_RR_CMDSIZE, 0);
r300->hw.rr.cmd[R300_RR_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RS_INST_0, 1);
}
ALLOC_STATE(sc_hyperz, always, 3, 0);
r300->hw.sc_hyperz.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_HYPERZ, 2);
ALLOC_STATE(sc_screendoor, always, 2, 0);
r300->hw.sc_screendoor.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_SC_SCREENDOOR, 1);
ALLOC_STATE(us_out_fmt, always, 6, 0);
r300->hw.us_out_fmt.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_OUT_FMT, 5);
if (is_r500) {
ALLOC_STATE(fp, always, R500_FP_CMDSIZE, 0);
r300->hw.fp.cmd[R500_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CONFIG, 2);
r300->hw.fp.cmd[R500_FP_CNTL] = R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO;
r300->hw.fp.cmd[R500_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R500_US_CODE_ADDR, 3);
r300->hw.fp.cmd[R500_FP_CMD_2] = cmdpacket0(r300->radeon.radeonScreen, R500_US_FC_CTRL, 1);
r300->hw.fp.cmd[R500_FP_FC_CNTL] = 0; /* FIXME when we add flow control */
ALLOC_STATE(r500fp, r500fp, R500_FPI_CMDSIZE, 0);
r300->hw.r500fp.cmd[R300_FPI_CMD_0] =
cmdr500fp(r300->radeon.radeonScreen, 0, 0, 0, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.r500fp.emit = emit_r500fp_atom;
ALLOC_STATE(r500fp_const, r500fp_const, R500_FPP_CMDSIZE, 0);
r300->hw.r500fp_const.cmd[R300_FPI_CMD_0] =
cmdr500fp(r300->radeon.radeonScreen, 0, 0, 1, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.r500fp_const.emit = emit_r500fp_atom;
} else {
ALLOC_STATE(fp, always, R300_FP_CMDSIZE, 0);
r300->hw.fp.cmd[R300_FP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CONFIG, 3);
r300->hw.fp.cmd[R300_FP_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_US_CODE_ADDR_0, 4);
ALLOC_STATE(fpt, variable, R300_FPT_CMDSIZE, 0);
r300->hw.fpt.cmd[R300_FPT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_TEX_INST_0, 0);
ALLOC_STATE(fpi[0], variable, R300_FPI_CMDSIZE, 0);
r300->hw.fpi[0].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_INST_0, 1);
ALLOC_STATE(fpi[1], variable, R300_FPI_CMDSIZE, 1);
r300->hw.fpi[1].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_RGB_ADDR_0, 1);
ALLOC_STATE(fpi[2], variable, R300_FPI_CMDSIZE, 2);
r300->hw.fpi[2].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_INST_0, 1);
ALLOC_STATE(fpi[3], variable, R300_FPI_CMDSIZE, 3);
r300->hw.fpi[3].cmd[R300_FPI_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_US_ALU_ALPHA_ADDR_0, 1);
ALLOC_STATE(fpp, variable, R300_FPP_CMDSIZE, 0);
r300->hw.fpp.cmd[R300_FPP_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_PFS_PARAM_0_X, 0);
}
ALLOC_STATE(fogs, always, R300_FOGS_CMDSIZE, 0);
r300->hw.fogs.cmd[R300_FOGS_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_BLEND, 1);
ALLOC_STATE(fogc, always, R300_FOGC_CMDSIZE, 0);
r300->hw.fogc.cmd[R300_FOGC_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_FOG_COLOR_R, 3);
ALLOC_STATE(at, always, R300_AT_CMDSIZE, 0);
r300->hw.at.cmd[R300_AT_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_ALPHA_FUNC, 2);
ALLOC_STATE(fg_depth_src, always, 2, 0);
r300->hw.fg_depth_src.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_FG_DEPTH_SRC, 1);
ALLOC_STATE(rb3d_cctl, always, 2, 0);
r300->hw.rb3d_cctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CCTL, 1);
ALLOC_STATE(bld, always, R300_BLD_CMDSIZE, 0);
r300->hw.bld.cmd[R300_BLD_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_CBLEND, 2);
ALLOC_STATE(cmk, always, R300_CMK_CMDSIZE, 0);
r300->hw.cmk.cmd[R300_CMK_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RB3D_COLOR_CHANNEL_MASK, 1);
if (is_r500) {
ALLOC_STATE(blend_color, always, 3, 0);
r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_CONSTANT_COLOR_AR, 2);
} else {
ALLOC_STATE(blend_color, always, 2, 0);
r300->hw.blend_color.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_BLEND_COLOR, 1);
}
ALLOC_STATE(rop, always, 2, 0);
r300->hw.rop.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_ROPCNTL, 1);
ALLOC_STATE(cb, cb_offset, R300_CB_CMDSIZE, 0);
r300->hw.cb.emit = &emit_cb_offset_atom;
ALLOC_STATE(rb3d_dither_ctl, always, 10, 0);
r300->hw.rb3d_dither_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_DITHER_CTL, 9);
ALLOC_STATE(rb3d_aaresolve_ctl, always, 2, 0);
r300->hw.rb3d_aaresolve_ctl.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_RB3D_AARESOLVE_CTL, 1);
if (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV350) {
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, always, 3, 0);
} else {
ALLOC_STATE(rb3d_discard_src_pixel_lte_threshold, never, 3, 0);
}
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
r300->hw.zs.cmd[R300_ZS_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_ZB_CNTL, 3);
if (is_r500) {
if (r300->radeon.radeonScreen->kernel_mm)
ALLOC_STATE(zsb, always, R300_ZSB_CMDSIZE, 0);
else
ALLOC_STATE(zsb, never, R300_ZSB_CMDSIZE, 0);
r300->hw.zsb.cmd[R300_ZSB_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R500_ZB_STENCILREFMASK_BF, 1);
}
ALLOC_STATE(zstencil_format, always, 5, 0);
r300->hw.zstencil_format.cmd[0] =
cmdpacket0(r300->radeon.radeonScreen, R300_ZB_FORMAT, 4);
r300->hw.zstencil_format.emit = emit_zstencil_format;
ALLOC_STATE(zb, zb_offset, R300_ZB_CMDSIZE, 0);
r300->hw.zb.emit = emit_zb_offset;
ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
ALLOC_STATE(zb_zmask, always, 3, 0);
r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
ALLOC_STATE(zb_hiz_offset, always, 2, 0);
r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_PITCH, 1);
/* VPU only on TCL */
if (has_tcl) {
int i;
ALLOC_STATE(vpi, vpu, R300_VPI_CMDSIZE, 0);
r300->hw.vpi.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CODE_START, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpi.emit = emit_vpu_state;
if (is_r500) {
ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_PVS_CONST_START, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpp.emit = emit_vpp_state;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R500_POINT_VPORT_SCALE_OFFSET, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vps.emit = emit_vpu_state;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
r300->hw.vpucp[i].cmd[0] =
cmdvpu(r300->radeon.radeonScreen,
R500_PVS_UCP_START + i, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpucp[i].emit = emit_vpu_state;
}
} else {
ALLOC_STATE(vpp, vpp, R300_VPP_CMDSIZE, 0);
r300->hw.vpp.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_PVS_CONST_START, 0);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpp.emit = emit_vpp_state;
ALLOC_STATE(vps, vpu, R300_VPS_CMDSIZE, 0);
r300->hw.vps.cmd[0] =
cmdvpu(r300->radeon.radeonScreen, R300_POINT_VPORT_SCALE_OFFSET, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vps.emit = emit_vpu_state;
for (i = 0; i < 6; i++) {
ALLOC_STATE(vpucp[i], vpu, R300_VPUCP_CMDSIZE, 0);
r300->hw.vpucp[i].cmd[0] =
cmdvpu(r300->radeon.radeonScreen,
R300_PVS_UCP_START + i, 1);
if (r300->radeon.radeonScreen->kernel_mm)
r300->hw.vpucp[i].emit = emit_vpu_state;
}
}
}
/* Textures */
ALLOC_STATE(tex.filter, variable, mtu + 1, 0);
r300->hw.tex.filter.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER0_0, 0);
ALLOC_STATE(tex.filter_1, variable, mtu + 1, 0);
r300->hw.tex.filter_1.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_FILTER1_0, 0);
ALLOC_STATE(tex.size, variable, mtu + 1, 0);
r300->hw.tex.size.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_SIZE_0, 0);
ALLOC_STATE(tex.format, variable, mtu + 1, 0);
r300->hw.tex.format.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT_0, 0);
ALLOC_STATE(tex.pitch, variable, mtu + 1, 0);
r300->hw.tex.pitch.cmd[R300_TEX_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_TX_FORMAT2_0, 0);
ALLOC_STATE(tex.offset, tex_offsets, 1, 0);
r300->hw.tex.offset.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_OFFSET_0, 0);
r300->hw.tex.offset.emit = &emit_tex_offsets;
ALLOC_STATE(tex.chroma_key, variable, mtu + 1, 0);
r300->hw.tex.chroma_key.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_CHROMA_KEY_0, 0);
ALLOC_STATE(tex.border_color, variable, mtu + 1, 0);
r300->hw.tex.border_color.cmd[R300_TEX_CMD_0] =
cmdpacket0(r300->radeon.radeonScreen, R300_TX_BORDER_COLOR_0, 0);
radeon_init_query_stateobj(&r300->radeon, R300_QUERYOBJ_CMDSIZE);
if (r300->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV530) {
r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, RV530_FG_ZBREG_DEST, 1);
r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL;
} else {
r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_0] = cmdpacket0(r300->radeon.radeonScreen, R300_SU_REG_DEST, 1);
r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_0] = R300_RASTER_PIPE_SELECT_ALL;
}
r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_CMD_1] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZPASS_DATA, 1);
r300->radeon.query.queryobj.cmd[R300_QUERYOBJ_DATA_1] = 0;
r300->radeon.hw.is_dirty = GL_TRUE;
r300->radeon.hw.all_dirty = GL_TRUE;
rcommonInitCmdBuf(&r300->radeon);
}

69
src/mesa/drivers/dri/r300/r300_cmdbuf.h
View file

@ -1,69 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file
*
* \author Nicolai Haehnle <prefect_@gmx.net>
*/
#ifndef __R300_CMDBUF_H__
#define __R300_CMDBUF_H__
#include "r300_context.h"
#define CACHE_FLUSH_BUFSZ (4*2)
#define PRE_EMIT_STATE_BUFSZ (2+2)
#define AOS_BUFSZ(nr) (3+(nr >>1)*3 + (nr&1)*2 + (nr*2))
#define FIREAOS_BUFSZ (3)
#define SCISSORS_BUFSZ (3)
void r300InitCmdBuf(r300ContextPtr r300);
void r300_emit_scissor(struct gl_context *ctx);
void r300_emit_vpu(struct r300_context *ctx,
uint32_t *data,
unsigned len,
uint32_t addr);
void r500_emit_fp(struct r300_context *r300,
uint32_t *data,
unsigned len,
uint32_t addr,
unsigned type,
unsigned clamp);
void r300_emit_cb_setup(struct r300_context *r300,
struct radeon_bo *bo,
uint32_t offset,
GLuint format,
unsigned cpp,
unsigned pitch);
#endif /* __R300_CMDBUF_H__ */

526
src/mesa/drivers/dri/r300/r300_context.c
View file

@ -1,526 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*
* \author Nicolai Haehnle <prefect_@gmx.net>
*/
#include <stdbool.h>
#include "main/glheader.h"
#include "main/api_arrayelt.h"
#include "main/context.h"
#include "main/simple_list.h"
#include "main/imports.h"
#include "main/extensions.h"
#include "main/bufferobj.h"
#include "main/texobj.h"
#include "main/mfeatures.h"
#include "swrast/swrast.h"
#include "swrast_setup/swrast_setup.h"
#include "vbo/vbo.h"
#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
#include "drivers/common/driverfuncs.h"
#include "drivers/common/meta.h"
#include "r300_context.h"
#include "radeon_span.h"
#include "r300_blit.h"
#include "r300_cmdbuf.h"
#include "r300_state.h"
#include "r300_tex.h"
#include "r300_emit.h"
#include "r300_render.h"
#include "r300_swtcl.h"
#include "radeon_bocs_wrapper.h"
#include "radeon_buffer_objects.h"
#include "radeon_queryobj.h"
#include "utils.h"
#include "xmlpool.h" /* for symbolic values of enum-type options */
static const struct tnl_pipeline_stage *r300_pipeline[] = {
/* Catch any t&l fallbacks
*/
&_tnl_vertex_transform_stage,
&_tnl_normal_transform_stage,
&_tnl_lighting_stage,
&_tnl_fog_coordinate_stage,
&_tnl_texgen_stage,
&_tnl_texture_transform_stage,
&_tnl_point_attenuation_stage,
&_tnl_vertex_program_stage,
&_tnl_render_stage,
0,
};
static void r300_get_lock(radeonContextPtr rmesa)
{
drm_radeon_sarea_t *sarea = rmesa->sarea;
if (sarea->ctx_owner != rmesa->dri.hwContext) {
sarea->ctx_owner = rmesa->dri.hwContext;
if (!rmesa->radeonScreen->kernel_mm)
radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
}
}
static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
/* please flush pipe do all pending work */
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_SC_SCREENDOOR, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_SC_SCREENDOOR, 1));
radeon_cs_write_dword(cs, 0x00FFFFFF);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_SC_HYPERZ, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_US_CONFIG, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_ZB_CNTL, 1));
radeon_cs_write_dword(cs, 0x0);
radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen, R300_WAIT_3D));
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_RB3D_DSTCACHE_CTLSTAT, 1));
radeon_cs_write_dword(cs, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
radeon_cs_write_dword(cs, cmdpacket0(rmesa->radeonScreen,
R300_ZB_ZCACHE_CTLSTAT, 1));
radeon_cs_write_dword(cs, R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE);
radeon_cs_write_dword(cs, cmdwait(rmesa->radeonScreen,
R300_WAIT_3D | R300_WAIT_3D_CLEAN));
}
static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
{
BATCH_LOCALS(radeon);
cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);
END_BATCH();
end_3d(radeon);
}
static void r300_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
if (mode)
r300->radeon.Fallback |= bit;
else
r300->radeon.Fallback &= ~bit;
r300SwitchFallback(ctx, R300_FALLBACK_RADEON_COMMON, mode);
}
static void r300_emit_query_finish(radeonContextPtr radeon)
{
r300ContextPtr r300 = (r300ContextPtr)radeon;
struct radeon_query_object *query = radeon->query.current;
BATCH_LOCALS(radeon);
BEGIN_BATCH_NO_AUTOSTATE(3 * 2 *r300->radeon.radeonScreen->num_gb_pipes + 2);
switch (r300->radeon.radeonScreen->num_gb_pipes) {
case 4:
OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_BATCH_RELOC(0, query->bo, query->curr_offset+3*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
case 3:
OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_2);
OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_BATCH_RELOC(0, query->bo, query->curr_offset+2*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
case 2:
if (r300->radeon.radeonScreen->chip_family <= CHIP_FAMILY_RV380) {
OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_3);
} else {
OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_1);
}
OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_BATCH_RELOC(0, query->bo, query->curr_offset+1*sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
case 1:
default:
OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_0);
OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
break;
}
OUT_BATCH_REGVAL(R300_SU_REG_DEST, R300_RASTER_PIPE_SELECT_ALL);
END_BATCH();
query->curr_offset += r300->radeon.radeonScreen->num_gb_pipes * sizeof(uint32_t);
assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
query->emitted_begin = GL_FALSE;
}
static void rv530_emit_query_finish_single_z(radeonContextPtr radeon)
{
BATCH_LOCALS(radeon);
struct radeon_query_object *query = radeon->query.current;
BEGIN_BATCH_NO_AUTOSTATE(8);
OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
END_BATCH();
query->curr_offset += sizeof(uint32_t);
assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
query->emitted_begin = GL_FALSE;
}
static void rv530_emit_query_finish_double_z(radeonContextPtr radeon)
{
BATCH_LOCALS(radeon);
struct radeon_query_object *query = radeon->query.current;
BEGIN_BATCH_NO_AUTOSTATE(14);
OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_0);
OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_BATCH_RELOC(0, query->bo, query->curr_offset, 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_1);
OUT_BATCH_REGSEQ(R300_ZB_ZPASS_ADDR, 1);
OUT_BATCH_RELOC(0, query->bo, query->curr_offset + sizeof(uint32_t), 0, RADEON_GEM_DOMAIN_GTT, 0);
OUT_BATCH_REGVAL(RV530_FG_ZBREG_DEST, RV530_FG_ZBREG_DEST_PIPE_SELECT_ALL);
END_BATCH();
query->curr_offset += 2 * sizeof(uint32_t);
assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
query->emitted_begin = GL_FALSE;
}
static void r300_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = r300_get_lock;
radeon->vtbl.update_viewport_offset = r300UpdateViewportOffset;
radeon->vtbl.emit_cs_header = r300_vtbl_emit_cs_header;
radeon->vtbl.swtcl_flush = r300_swtcl_flush;
radeon->vtbl.pre_emit_atoms = r300_vtbl_pre_emit_atoms;
radeon->vtbl.fallback = r300_fallback;
if (radeon->radeonScreen->chip_family == CHIP_FAMILY_RV530) {
if (radeon->radeonScreen->num_z_pipes == 2)
radeon->vtbl.emit_query_finish = rv530_emit_query_finish_double_z;
else
radeon->vtbl.emit_query_finish = rv530_emit_query_finish_single_z;
} else
radeon->vtbl.emit_query_finish = r300_emit_query_finish;
radeon->vtbl.check_blit = r300_check_blit;
radeon->vtbl.blit = r300_blit;
if (radeon->radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
radeon->vtbl.is_format_renderable = r500IsFormatRenderable;
} else {
radeon->vtbl.is_format_renderable = r300IsFormatRenderable;
}
}
static void r300InitConstValues(struct gl_context *ctx, radeonScreenPtr screen)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
ctx->Const.MaxTextureImageUnits =
driQueryOptioni(&r300->radeon.optionCache, "texture_image_units");
ctx->Const.MaxTextureCoordUnits =
driQueryOptioni(&r300->radeon.optionCache, "texture_coord_units");
ctx->Const.MaxTextureUnits = MIN2(ctx->Const.MaxTextureImageUnits,
ctx->Const.MaxTextureCoordUnits);
ctx->Const.MaxCombinedTextureImageUnits =
ctx->Const.MaxVertexTextureImageUnits +
ctx->Const.MaxTextureImageUnits;
ctx->Const.MaxTextureMaxAnisotropy = 16.0;
ctx->Const.MaxTextureLodBias = 16.0;
if (screen->chip_family >= CHIP_FAMILY_RV515) {
ctx->Const.MaxTextureLevels = 13;
ctx->Const.MaxCubeTextureLevels = 13;
ctx->Const.MaxTextureRectSize = 4096;
ctx->Const.MaxRenderbufferSize = 4096;
}
else {
ctx->Const.MaxTextureLevels = 12;
ctx->Const.MaxCubeTextureLevels = 12;
ctx->Const.MaxTextureRectSize = 2048;
ctx->Const.MaxRenderbufferSize = 2048;
}
ctx->Const.MinPointSize = 1.0;
ctx->Const.MinPointSizeAA = 1.0;
ctx->Const.MaxPointSize = R300_POINTSIZE_MAX;
ctx->Const.MaxPointSizeAA = R300_POINTSIZE_MAX;
ctx->Const.MinLineWidth = 1.0;
ctx->Const.MinLineWidthAA = 1.0;
ctx->Const.MaxLineWidth = R300_LINESIZE_MAX;
ctx->Const.MaxLineWidthAA = R300_LINESIZE_MAX;
ctx->Const.MaxDrawBuffers = 1;
ctx->Const.MaxColorAttachments = 1;
if (r300->options.hw_tcl_enabled) {
ctx->Const.VertexProgram.MaxNativeInstructions = 255;
ctx->Const.VertexProgram.MaxNativeAluInstructions = 255;
ctx->Const.VertexProgram.MaxNativeAttribs = 16;
ctx->Const.VertexProgram.MaxNativeTemps = 32;
ctx->Const.VertexProgram.MaxNativeParameters = 256;
ctx->Const.VertexProgram.MaxNativeAddressRegs = 1;
}
if (screen->chip_family >= CHIP_FAMILY_RV515) {
ctx->Const.FragmentProgram.MaxNativeTemps = R500_PFS_NUM_TEMP_REGS;
ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */
/* The hardware limits are higher than this,
* but the non-KMS DRM interface artificially limits us
* to this many instructions.
*
* We could of course work around it in the KMS path,
* but it would be a mess, so it seems wiser
* to leave it as is. Going forward, the Gallium driver
* will not be subject to these limitations.
*/
ctx->Const.FragmentProgram.MaxNativeParameters = 255;
ctx->Const.FragmentProgram.MaxNativeAluInstructions = 255;
ctx->Const.FragmentProgram.MaxNativeTexInstructions = 255;
ctx->Const.FragmentProgram.MaxNativeInstructions = 255;
ctx->Const.FragmentProgram.MaxNativeTexIndirections = 255;
ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
} else {
ctx->Const.FragmentProgram.MaxNativeTemps = R300_PFS_NUM_TEMP_REGS;
ctx->Const.FragmentProgram.MaxNativeAttribs = 11; /* copy i915... */
ctx->Const.FragmentProgram.MaxNativeParameters = R300_PFS_NUM_CONST_REGS;
ctx->Const.FragmentProgram.MaxNativeAluInstructions = R300_PFS_MAX_ALU_INST;
ctx->Const.FragmentProgram.MaxNativeTexInstructions = R300_PFS_MAX_TEX_INST;
ctx->Const.FragmentProgram.MaxNativeInstructions = R300_PFS_MAX_ALU_INST + R300_PFS_MAX_TEX_INST;
ctx->Const.FragmentProgram.MaxNativeTexIndirections = R300_PFS_MAX_TEX_INDIRECT;
ctx->Const.FragmentProgram.MaxNativeAddressRegs = 0;
}
}
static void r300ParseOptions(r300ContextPtr r300, radeonScreenPtr screen)
{
struct r300_options options = { 0 };
driParseConfigFiles(&r300->radeon.optionCache, &screen->optionCache,
screen->driScreen->myNum, "r300");
r300->radeon.initialMaxAnisotropy = driQueryOptionf(&r300->radeon.optionCache, "def_max_anisotropy");
options.stencil_two_side_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_stencil_two_side");
options.s3tc_force_enabled = driQueryOptionb(&r300->radeon.optionCache, "force_s3tc_enable");
options.s3tc_force_disabled = driQueryOptionb(&r300->radeon.optionCache, "disable_s3tc");
if (!(screen->chip_flags & RADEON_CHIPSET_TCL) || driQueryOptioni(&r300->radeon.optionCache, "tcl_mode") == DRI_CONF_TCL_SW)
options.hw_tcl_enabled = 0;
else
options.hw_tcl_enabled = 1;
options.conformance_mode = !driQueryOptionb(&r300->radeon.optionCache, "disable_lowimpact_fallback");
r300->options = options;
}
static void r300InitGLExtensions(struct gl_context *ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
ctx->Extensions.ARB_depth_texture = true;
ctx->Extensions.ARB_fragment_program = true;
ctx->Extensions.ARB_shadow = true;
ctx->Extensions.ARB_shadow_ambient = true;
ctx->Extensions.ARB_texture_border_clamp = true;
ctx->Extensions.ARB_texture_cube_map = true;
ctx->Extensions.ARB_texture_env_combine = true;
ctx->Extensions.ARB_texture_env_crossbar = true;
ctx->Extensions.ARB_texture_env_dot3 = true;
ctx->Extensions.ARB_vertex_program = true;
ctx->Extensions.EXT_blend_color = true;
ctx->Extensions.EXT_blend_equation_separate = true;
ctx->Extensions.EXT_blend_func_separate = true;
ctx->Extensions.EXT_blend_minmax = true;
ctx->Extensions.EXT_fog_coord = true;
ctx->Extensions.EXT_gpu_program_parameters = true;
ctx->Extensions.EXT_point_parameters = true;
ctx->Extensions.EXT_provoking_vertex = true;
ctx->Extensions.EXT_secondary_color = true;
ctx->Extensions.EXT_shadow_funcs = true;
ctx->Extensions.EXT_texture_env_dot3 = true;
ctx->Extensions.EXT_texture_filter_anisotropic = true;
ctx->Extensions.EXT_texture_mirror_clamp = true;
ctx->Extensions.EXT_texture_sRGB = true;
ctx->Extensions.EXT_vertex_array_bgra = true;
ctx->Extensions.ATI_separate_stencil = true;
ctx->Extensions.ATI_texture_env_combine3 = true;
ctx->Extensions.ATI_texture_mirror_once = true;
ctx->Extensions.MESA_pack_invert = true;
ctx->Extensions.MESA_ycbcr_texture = true;
ctx->Extensions.NV_blend_square = true;
ctx->Extensions.NV_texture_rectangle = true;
ctx->Extensions.NV_vertex_program = true;
#if FEATURE_OES_EGL_image
ctx->Extensions.OES_EGL_image = true;
#endif
if (r300->radeon.radeonScreen->kernel_mm) {
ctx->Extensions.EXT_framebuffer_blit = true;
ctx->Extensions.EXT_framebuffer_object = true;
}
ctx->Extensions.EXT_stencil_two_side =
!r300->options.stencil_two_side_disabled;
if (r300->options.s3tc_force_disabled) {
ctx->Extensions.EXT_texture_compression_s3tc = false;
} else if (ctx->Mesa_DXTn || r300->options.s3tc_force_enabled) {
ctx->Extensions.EXT_texture_compression_s3tc = true;
ctx->Extensions.S3_s3tc = true;
}
ctx->Extensions.ARB_occlusion_query =
r300->radeon.radeonScreen->drmSupportsOcclusionQueries;
ctx->Extensions.ARB_half_float_vertex =
(r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_R420);
ctx->Extensions.EXT_packed_depth_stencil =
(r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515);
}
static void r300InitIoctlFuncs(struct dd_function_table *functions)
{
functions->Clear = _mesa_meta_Clear;
functions->Finish = radeonFinish;
functions->Flush = radeonFlush;
}
/* Create the device specific rendering context.
*/
GLboolean r300CreateContext(gl_api api,
const struct gl_config * glVisual,
__DRIcontext * driContextPriv,
void *sharedContextPrivate)
{
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
struct dd_function_table functions;
r300ContextPtr r300;
struct gl_context *ctx;
assert(glVisual);
assert(driContextPriv);
assert(screen);
r300 = (r300ContextPtr) CALLOC(sizeof(*r300));
if (!r300)
return GL_FALSE;
r300ParseOptions(r300, screen);
r300->radeon.radeonScreen = screen;
r300_init_vtbl(&r300->radeon);
_mesa_init_driver_functions(&functions);
r300InitIoctlFuncs(&functions);
r300InitStateFuncs(&r300->radeon, &functions);
r300InitTextureFuncs(&r300->radeon, &functions);
r300InitShaderFuncs(&functions);
radeonInitQueryObjFunctions(&functions);
radeonInitBufferObjectFuncs(&functions);
if (!radeonInitContext(&r300->radeon, &functions,
glVisual, driContextPriv,
sharedContextPrivate)) {
FREE(r300);
return GL_FALSE;
}
ctx = r300->radeon.glCtx;
r300->fallback = 0;
if (r300->options.hw_tcl_enabled)
ctx->VertexProgram._MaintainTnlProgram = GL_TRUE;
ctx->FragmentProgram._MaintainTexEnvProgram = GL_TRUE;
r300InitConstValues(ctx, screen);
_mesa_set_mvp_with_dp4( ctx, GL_TRUE );
/* Initialize the software rasterizer and helper modules.
*/
_swrast_CreateContext(ctx);
_vbo_CreateContext(ctx);
_tnl_CreateContext(ctx);
_swsetup_CreateContext(ctx);
_swsetup_Wakeup(ctx);
/* Install the customized pipeline:
*/
_tnl_destroy_pipeline(ctx);
_tnl_install_pipeline(ctx, r300_pipeline);
TNL_CONTEXT(ctx)->Driver.RunPipeline = _tnl_run_pipeline;
/* Configure swrast and TNL to match hardware characteristics:
*/
_swrast_allow_pixel_fog(ctx, GL_FALSE);
_swrast_allow_vertex_fog(ctx, GL_TRUE);
_tnl_allow_pixel_fog(ctx, GL_FALSE);
_tnl_allow_vertex_fog(ctx, GL_TRUE);
if (r300->options.hw_tcl_enabled) {
r300InitDraw(ctx);
} else {
r300InitSwtcl(ctx);
}
r300_blit_init(r300);
radeon_fbo_init(&r300->radeon);
radeonInitSpanFuncs( ctx );
r300InitCmdBuf(r300);
r300InitState(r300);
r300InitShaderFunctions(r300);
r300InitGLExtensions(ctx);
return GL_TRUE;
}

560
src/mesa/drivers/dri/r300/r300_context.h
View file

@ -1,560 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file
*
* \author Keith Whitwell <keith@tungstengraphics.com>
* \author Nicolai Haehnle <prefect_@gmx.net>
*/
#ifndef __R300_CONTEXT_H__
#define __R300_CONTEXT_H__
#include "drm.h"
#include "radeon_drm.h"
#include "dri_util.h"
#include "radeon_common.h"
#include "main/mtypes.h"
#include "program/prog_instruction.h"
#include "compiler/radeon_code.h"
struct r300_context;
typedef struct r300_context r300ContextRec;
typedef struct r300_context *r300ContextPtr;
#include "r300_vertprog.h"
/* The blit width for texture uploads
*/
#define R300_BLIT_WIDTH_BYTES 1024
#define R300_MAX_TEXTURE_UNITS 8
#define R300_VPT_CMD_0 0
#define R300_VPT_XSCALE 1
#define R300_VPT_XOFFSET 2
#define R300_VPT_YSCALE 3
#define R300_VPT_YOFFSET 4
#define R300_VPT_ZSCALE 5
#define R300_VPT_ZOFFSET 6
#define R300_VPT_CMDSIZE 7
#define R300_VIR_CMD_0 0 /* vir is variable size (at least 1) */
#define R300_VIR_CNTL_0 1
#define R300_VIR_CNTL_1 2
#define R300_VIR_CNTL_2 3
#define R300_VIR_CNTL_3 4
#define R300_VIR_CNTL_4 5
#define R300_VIR_CNTL_5 6
#define R300_VIR_CNTL_6 7
#define R300_VIR_CNTL_7 8
#define R300_VIR_CMDSIZE 9
#define R300_VIC_CMD_0 0
#define R300_VIC_CNTL_0 1
#define R300_VIC_CNTL_1 2
#define R300_VIC_CMDSIZE 3
#define R300_VOF_CMD_0 0
#define R300_VOF_CNTL_0 1
#define R300_VOF_CNTL_1 2
#define R300_VOF_CMDSIZE 3
#define R300_PVS_CMD_0 0
#define R300_PVS_CNTL_1 1
#define R300_PVS_CNTL_2 2
#define R300_PVS_CNTL_3 3
#define R300_PVS_CMDSIZE 4
#define R300_GB_MISC_CMD_0 0
#define R300_GB_MISC_MSPOS_0 1
#define R300_GB_MISC_MSPOS_1 2
#define R300_GB_MISC_TILE_CONFIG 3
#define R300_GB_MISC_CMDSIZE 4
#define R300_GB_MISC2_CMD_0 0
#define R300_GB_MISC2_SELECT 1
#define R300_GB_MISC2_AA_CONFIG 2
#define R300_GB_MISC2_CMDSIZE 3
#define R300_TXE_CMD_0 0
#define R300_TXE_ENABLE 1
#define R300_TXE_CMDSIZE 2
#define R300_PS_CMD_0 0
#define R300_PS_POINTSIZE 1
#define R300_PS_CMDSIZE 2
#define R300_ZBS_CMD_0 0
#define R300_ZBS_T_FACTOR 1
#define R300_ZBS_T_CONSTANT 2
#define R300_ZBS_W_FACTOR 3
#define R300_ZBS_W_CONSTANT 4
#define R300_ZBS_CMDSIZE 5
#define R300_CUL_CMD_0 0
#define R300_CUL_CULL 1
#define R300_CUL_CMDSIZE 2
#define R300_RC_CMD_0 0
#define R300_RC_CNTL_0 1
#define R300_RC_CNTL_1 2
#define R300_RC_CMDSIZE 3
#define R300_RI_CMD_0 0
#define R300_RI_INTERP_0 1
#define R300_RI_INTERP_1 2
#define R300_RI_INTERP_2 3
#define R300_RI_INTERP_3 4
#define R300_RI_INTERP_4 5
#define R300_RI_INTERP_5 6
#define R300_RI_INTERP_6 7
#define R300_RI_INTERP_7 8
#define R300_RI_CMDSIZE 9
#define R500_RI_CMDSIZE 17
#define R300_RR_CMD_0 0 /* rr is variable size (at least 1) */
#define R300_RR_INST_0 1
#define R300_RR_INST_1 2
#define R300_RR_INST_2 3
#define R300_RR_INST_3 4
#define R300_RR_INST_4 5
#define R300_RR_INST_5 6
#define R300_RR_INST_6 7
#define R300_RR_INST_7 8
#define R300_RR_CMDSIZE 9
#define R300_FP_CMD_0 0
#define R300_FP_CNTL0 1
#define R300_FP_CNTL1 2
#define R300_FP_CNTL2 3
#define R300_FP_CMD_1 4
#define R300_FP_NODE0 5
#define R300_FP_NODE1 6
#define R300_FP_NODE2 7
#define R300_FP_NODE3 8
#define R300_FP_CMDSIZE 9
#define R500_FP_CMD_0 0
#define R500_FP_CNTL 1
#define R500_FP_PIXSIZE 2
#define R500_FP_CMD_1 3
#define R500_FP_CODE_ADDR 4
#define R500_FP_CODE_RANGE 5
#define R500_FP_CODE_OFFSET 6
#define R500_FP_CMD_2 7
#define R500_FP_FC_CNTL 8
#define R500_FP_CMDSIZE 9
#define R300_FPT_CMD_0 0
#define R300_FPT_INSTR_0 1
#define R300_FPT_CMDSIZE 65
#define R300_FPI_CMD_0 0
#define R300_FPI_INSTR_0 1
#define R300_FPI_CMDSIZE 65
/* R500 has space for 512 instructions - 6 dwords per instruction */
#define R500_FPI_CMDSIZE (512*6+1)
#define R300_FPP_CMD_0 0
#define R300_FPP_PARAM_0 1
#define R300_FPP_CMDSIZE (32*4+1)
/* R500 has spcae for 256 constants - 4 dwords per constant */
#define R500_FPP_CMDSIZE (256*4+1)
#define R300_FOGS_CMD_0 0
#define R300_FOGS_STATE 1
#define R300_FOGS_CMDSIZE 2
#define R300_FOGC_CMD_0 0
#define R300_FOGC_R 1
#define R300_FOGC_G 2
#define R300_FOGC_B 3
#define R300_FOGC_CMDSIZE 4
#define R300_FOGP_CMD_0 0
#define R300_FOGP_SCALE 1
#define R300_FOGP_START 2
#define R300_FOGP_CMDSIZE 3
#define R300_AT_CMD_0 0
#define R300_AT_ALPHA_TEST 1
#define R300_AT_UNKNOWN 2
#define R300_AT_CMDSIZE 3
#define R300_BLD_CMD_0 0
#define R300_BLD_CBLEND 1
#define R300_BLD_ABLEND 2
#define R300_BLD_CMDSIZE 3
#define R300_CMK_CMD_0 0
#define R300_CMK_COLORMASK 1
#define R300_CMK_CMDSIZE 2
#define R300_CB_CMD_0 0
#define R300_CB_OFFSET 1
#define R300_CB_CMD_1 2
#define R300_CB_PITCH 3
#define R300_CB_CMDSIZE 4
#define R300_ZS_CMD_0 0
#define R300_ZS_CNTL_0 1
#define R300_ZS_CNTL_1 2
#define R300_ZS_CNTL_2 3
#define R300_ZS_CMDSIZE 4
#define R300_ZSB_CMD_0 0
#define R300_ZSB_CNTL_0 1
#define R300_ZSB_CMDSIZE 2
#define R300_ZB_CMD_0 0
#define R300_ZB_OFFSET 1
#define R300_ZB_PITCH 2
#define R300_ZB_CMDSIZE 3
#define R300_VAP_CNTL_FLUSH 0
#define R300_VAP_CNTL_FLUSH_1 1
#define R300_VAP_CNTL_CMD 2
#define R300_VAP_CNTL_INSTR 3
#define R300_VAP_CNTL_SIZE 4
#define R300_VPI_CMD_0 0
#define R300_VPI_INSTR_0 1
#define R300_VPI_CMDSIZE 1025 /* 256 16 byte instructions */
#define R300_VPP_CMD_0 0
#define R300_VPP_PARAM_0 1
#define R300_VPP_CMDSIZE 1025 /* 256 4-component parameters */
#define R300_VPUCP_CMD_0 0
#define R300_VPUCP_X 1
#define R300_VPUCP_Y 2
#define R300_VPUCP_Z 3
#define R300_VPUCP_W 4
#define R300_VPUCP_CMDSIZE 5 /* 256 4-component parameters */
#define R300_VPS_CMD_0 0
#define R300_VPS_ZERO_0 1
#define R300_VPS_ZERO_1 2
#define R300_VPS_POINTSIZE 3
#define R300_VPS_ZERO_3 4
#define R300_VPS_CMDSIZE 5
/* the layout is common for all fields inside tex */
#define R300_TEX_CMD_0 0
#define R300_TEX_VALUE_0 1
/* We don't really use this, instead specify mtu+1 dynamically
#define R300_TEX_CMDSIZE (MAX_TEXTURE_UNITS+1)
*/
#define R300_QUERYOBJ_CMD_0 0
#define R300_QUERYOBJ_DATA_0 1
#define R300_QUERYOBJ_CMD_1 2
#define R300_QUERYOBJ_DATA_1 3
#define R300_QUERYOBJ_CMDSIZE 4
/**
* Cache for hardware register state.
*/
struct r300_hw_state {
struct radeon_state_atom vpt; /* viewport (1D98) */
struct radeon_state_atom vap_cntl;
struct radeon_state_atom vap_index_offset; /* 0x208c r5xx only */
struct radeon_state_atom vof; /* VAP output format register 0x2090 */
struct radeon_state_atom vte; /* (20B0) */
struct radeon_state_atom vap_vf_max_vtx_indx; /* Maximum Vertex Indx Clamp (2134) */
struct radeon_state_atom vap_cntl_status;
struct radeon_state_atom vir[2]; /* vap input route (2150/21E0) */
struct radeon_state_atom vic; /* vap input control (2180) */
struct radeon_state_atom vap_psc_sgn_norm_cntl; /* Programmable Stream Control Signed Normalize Control (21DC) */
struct radeon_state_atom vap_clip_cntl;
struct radeon_state_atom vap_clip;
struct radeon_state_atom vap_pvs_vtx_timeout_reg; /* Vertex timeout register (2288) */
struct radeon_state_atom pvs; /* pvs_cntl (22D0) */
struct radeon_state_atom gb_enable; /* (4008) */
struct radeon_state_atom gb_misc; /* Multisampling position shifts ? (4010) */
struct radeon_state_atom gb_misc2; /* Multisampling position shifts ? (4010) */
struct radeon_state_atom ga_point_s0; /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) (4200) */
struct radeon_state_atom ga_triangle_stipple; /* (4214) */
struct radeon_state_atom ps; /* pointsize (421C) */
struct radeon_state_atom ga_point_minmax; /* (4230) */
struct radeon_state_atom lcntl; /* line control */
struct radeon_state_atom ga_line_stipple; /* (4260) */
struct radeon_state_atom shade;
struct radeon_state_atom shade2;
struct radeon_state_atom polygon_mode;
struct radeon_state_atom fogp; /* fog parameters (4294) */
struct radeon_state_atom ga_soft_reset; /* (429C) */
struct radeon_state_atom zbias_cntl;
struct radeon_state_atom zbs; /* zbias (42A4) */
struct radeon_state_atom occlusion_cntl;
struct radeon_state_atom cul; /* cull cntl (42B8) */
struct radeon_state_atom su_depth_scale; /* (42C0) */
struct radeon_state_atom rc; /* rs control (4300) */
struct radeon_state_atom ri; /* rs interpolators (4310) */
struct radeon_state_atom rr; /* rs route (4330) */
struct radeon_state_atom sc_hyperz; /* (43A4) */
struct radeon_state_atom sc_screendoor; /* (43E8) */
struct radeon_state_atom fp; /* fragment program cntl + nodes (4600) */
struct radeon_state_atom fpt; /* texi - (4620) */
struct radeon_state_atom us_out_fmt; /* (46A4) */
struct radeon_state_atom r500fp; /* r500 fp instructions */
struct radeon_state_atom r500fp_const; /* r500 fp constants */
struct radeon_state_atom fpi[4]; /* fp instructions (46C0/47C0/48C0/49C0) */
struct radeon_state_atom fogs; /* fog state (4BC0) */
struct radeon_state_atom fogc; /* fog color (4BC8) */
struct radeon_state_atom at; /* alpha test (4BD4) */
struct radeon_state_atom fg_depth_src; /* (4BD8) */
struct radeon_state_atom fpp; /* 0x4C00 and following */
struct radeon_state_atom rb3d_cctl; /* (4E00) */
struct radeon_state_atom bld; /* blending (4E04) */
struct radeon_state_atom cmk; /* colormask (4E0C) */
struct radeon_state_atom blend_color; /* constant blend color */
struct radeon_state_atom rop; /* ropcntl */
struct radeon_state_atom cb; /* colorbuffer (4E28) */
struct radeon_state_atom rb3d_dither_ctl; /* (4E50) */
struct radeon_state_atom rb3d_aaresolve_ctl; /* (4E88) */
struct radeon_state_atom rb3d_discard_src_pixel_lte_threshold; /* (4E88) I saw it only written on RV350 hardware.. */
struct radeon_state_atom zs; /* zstencil control (4F00) */
struct radeon_state_atom zsb; /* zstencil bf */
struct radeon_state_atom zstencil_format;
struct radeon_state_atom zb; /* z buffer (4F20) */
struct radeon_state_atom zb_depthclearvalue; /* (4F28) */
struct radeon_state_atom zb_zmask; /* (4F30) */
struct radeon_state_atom zb_hiz_offset; /* (4F44) */
struct radeon_state_atom zb_hiz_pitch; /* (4F54) */
struct radeon_state_atom vpi; /* vp instructions */
struct radeon_state_atom vpp; /* vp parameters */
struct radeon_state_atom vps; /* vertex point size (?) */
struct radeon_state_atom vpucp[6]; /* vp user clip plane - 6 */
/* 8 texture units */
/* the state is grouped by function and not by
texture unit. This makes single unit updates
really awkward - we are much better off
updating the whole thing at once */
struct {
struct radeon_state_atom filter;
struct radeon_state_atom filter_1;
struct radeon_state_atom size;
struct radeon_state_atom format;
struct radeon_state_atom pitch;
struct radeon_state_atom offset;
struct radeon_state_atom chroma_key;
struct radeon_state_atom border_color;
} tex;
struct radeon_state_atom txe; /* tex enable (4104) */
radeonTexObj *textures[R300_MAX_TEXTURE_UNITS];
};
/**
* State cache
*/
/* Vertex shader state */
#define COLOR_IS_RGBA
#define TAG(x) r300##x
#include "tnl_dd/t_dd_vertex.h"
#undef TAG
struct r300_vertex_program_key {
GLbitfield FpReads;
GLuint FogAttr;
GLuint WPosAttr;
};
struct r300_vertex_program {
struct gl_vertex_program *Base;
struct r300_vertex_program *next;
struct r300_vertex_program_key key;
struct r300_vertex_program_code code;
GLboolean error;
};
struct r300_vertex_program_cont {
/* This is the unmodified vertex program mesa provided us with.
* We need to keep it unchanged because we may need to create another
* hw specific vertex program based on this.
*/
struct gl_vertex_program mesa_program;
/* This is the list of hw specific vertex programs derived from mesa_program */
struct r300_vertex_program *progs;
};
/**
* Store everything about a fragment program that is needed
* to render with that program.
*/
struct r300_fragment_program {
GLboolean error;
struct r300_fragment_program *next;
struct r300_fragment_program_external_state state;
struct rX00_fragment_program_code code;
GLbitfield InputsRead;
/* attribute that we are sending the WPOS in */
gl_frag_attrib wpos_attr;
/* attribute that we are sending the fog coordinate in */
gl_frag_attrib fog_attr;
};
struct r300_fragment_program_cont {
/* This is the unmodified fragment program mesa provided us with.
* We need to keep it unchanged because we may need to create another
* hw specific fragment program based on this.
*/
struct gl_fragment_program Base;
/* This is the list of hw specific fragment programs derived from Base */
struct r300_fragment_program *progs;
};
#define R300_MAX_AOS_ARRAYS 16
/* r300_swtcl.c
*/
struct r300_swtcl_info {
/*
* Offset of the 4UB color data within a hardware (swtcl) vertex.
*/
GLuint coloroffset;
/**
* Offset of the 3UB specular color data within a hardware (swtcl) vertex.
*/
GLuint specoffset;
};
struct r300_vtable {
void (* SetupRSUnit)(struct gl_context *ctx);
void (* SetupFragmentShaderTextures)(struct gl_context *ctx, int *tmu_mappings);
void (* SetupPixelShader)(struct gl_context *ctx);
};
struct r300_vertex_buffer {
struct vertex_attribute {
/* generic */
GLubyte element;
GLuint stride;
GLuint dwords;
GLubyte size; /* number of components */
GLboolean is_named_bo;
struct radeon_bo *bo;
GLint bo_offset;
/* hw specific */
uint32_t data_type:4;
uint32_t dst_loc:5;
uint32_t _signed:1;
uint32_t normalize:1;
uint32_t swizzle:12;
uint32_t write_mask:4;
} attribs[VERT_ATTRIB_MAX];
GLubyte num_attribs;
};
struct r300_index_buffer {
struct radeon_bo *bo;
int bo_offset;
GLboolean is_32bit;
GLuint count;
};
/**
* \brief R300 context structure.
*/
struct r300_context {
struct radeon_context radeon; /* parent class, must be first */
struct r300_vtable vtbl;
struct r300_hw_state hw;
struct r300_vertex_program *selected_vp;
struct r300_fragment_program *selected_fp;
/* Vertex buffers
*/
GLvector4f dummy_attrib[_TNL_ATTRIB_MAX];
GLvector4f *temp_attrib[_TNL_ATTRIB_MAX];
struct r300_options {
uint32_t conformance_mode:1;
uint32_t hw_tcl_enabled:1;
uint32_t s3tc_force_enabled:1;
uint32_t s3tc_force_disabled:1;
uint32_t stencil_two_side_disabled:1;
} options;
struct r300_swtcl_info swtcl;
struct r300_vertex_buffer vbuf;
struct r300_index_buffer ind_buf;
uint32_t fallback;
struct {
struct r300_vertex_program_code vp_code;
struct rX00_fragment_program_code fp_code;
} blit;
DECLARE_RENDERINPUTS(render_inputs_bitset);
};
#define R300_CONTEXT(ctx) ((r300ContextPtr)(ctx->DriverCtx))
extern void r300DestroyContext(__DRIcontext * driContextPriv);
extern GLboolean r300CreateContext(gl_api api,
const struct gl_config * glVisual,
__DRIcontext * driContextPriv,
void *sharedContextPrivate);
extern void r300InitShaderFuncs(struct dd_function_table *functions);
extern void r300InitShaderFunctions(r300ContextPtr r300);
extern void r300InitDraw(struct gl_context *ctx);
#define r300PackFloat32 radeonPackFloat32
#define r300PackFloat24 radeonPackFloat24
#endif /* __R300_CONTEXT_H__ */

759
src/mesa/drivers/dri/r300/r300_draw.c
View file

@ -1,759 +0,0 @@
/**************************************************************************
*
* Copyright 2009 Maciej Cencora
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL THE AUTHOR(S) AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#include <stdlib.h>
#include "main/glheader.h"
#include "main/context.h"
#include "main/state.h"
#include "main/enums.h"
#include "main/simple_list.h"
#include "r300_reg.h"
#include "r300_context.h"
#include "r300_emit.h"
#include "r300_render.h"
#include "r300_state.h"
#include "r300_tex.h"
#include "r300_cmdbuf.h"
#include "radeon_buffer_objects.h"
#include "radeon_common_context.h"
#include "tnl/tnl.h"
#include "tnl/t_vp_build.h"
#include "vbo/vbo_context.h"
static int getTypeSize(GLenum type)
{
switch (type) {
case GL_DOUBLE:
return sizeof(GLdouble);
case GL_HALF_FLOAT:
return sizeof(GLhalfARB);
case GL_FLOAT:
return sizeof(GLfloat);
case GL_INT:
return sizeof(GLint);
case GL_UNSIGNED_INT:
return sizeof(GLuint);
case GL_SHORT:
return sizeof(GLshort);
case GL_UNSIGNED_SHORT:
return sizeof(GLushort);
case GL_BYTE:
return sizeof(GLbyte);
case GL_UNSIGNED_BYTE:
return sizeof(GLubyte);
default:
assert(0);
return 0;
}
}
static void r300FixupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
GLvoid *src_ptr;
GLuint *out;
int i;
GLboolean mapped_named_bo = GL_FALSE;
if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) {
ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
GL_MAP_READ_BIT, mesa_ind_buf->obj);
mapped_named_bo = GL_TRUE;
assert(mesa_ind_buf->obj->Pointer != NULL);
}
src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
"%s: Fixing index buffer format. type %d\n",
__func__, mesa_ind_buf->type);
if (mesa_ind_buf->type == GL_UNSIGNED_BYTE) {
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
GLubyte *in = (GLubyte *)src_ptr;
radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4);
radeon_bo_map(r300->ind_buf.bo, 1);
assert(r300->ind_buf.bo->ptr != NULL);
out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset);
for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) {
*out++ = in[i] | in[i + 1] << 16;
}
if (i < mesa_ind_buf->count) {
*out++ = in[i];
}
radeon_bo_unmap(r300->ind_buf.bo);
#if MESA_BIG_ENDIAN
} else { /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
GLushort *in = (GLushort *)src_ptr;
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo,
&r300->ind_buf.bo_offset, size, 4);
radeon_bo_map(r300->ind_buf.bo, 1);
assert(r300->ind_buf.bo->ptr != NULL);
out = (GLuint *)ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset);
for (i = 0; i + 1 < mesa_ind_buf->count; i += 2) {
*out++ = in[i] | in[i + 1] << 16;
}
if (i < mesa_ind_buf->count) {
*out++ = in[i];
}
radeon_bo_unmap(r300->ind_buf.bo);
#endif
}
r300->ind_buf.is_32bit = GL_FALSE;
r300->ind_buf.count = mesa_ind_buf->count;
if (mapped_named_bo) {
ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
}
}
static void r300SetupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
if (!mesa_ind_buf) {
r300->ind_buf.bo = NULL;
return;
}
radeon_print(RADEON_RENDER, RADEON_TRACE, "%s\n", __func__);
#if MESA_BIG_ENDIAN
if (mesa_ind_buf->type == GL_UNSIGNED_INT) {
#else
if (mesa_ind_buf->type != GL_UNSIGNED_BYTE) {
#endif
const GLvoid *src_ptr;
GLvoid *dst_ptr;
GLboolean mapped_named_bo = GL_FALSE;
if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer) {
ctx->Driver.MapBufferRange(ctx, 0,
mesa_ind_buf->obj->Size,
GL_MAP_READ_BIT,
mesa_ind_buf->obj);
assert(mesa_ind_buf->obj->Pointer != NULL);
mapped_named_bo = GL_TRUE;
}
src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
radeonAllocDmaRegion(&r300->radeon, &r300->ind_buf.bo, &r300->ind_buf.bo_offset, size, 4);
radeon_bo_map(r300->ind_buf.bo, 1);
assert(r300->ind_buf.bo->ptr != NULL);
dst_ptr = ADD_POINTERS(r300->ind_buf.bo->ptr, r300->ind_buf.bo_offset);
memcpy(dst_ptr, src_ptr, size);
radeon_bo_unmap(r300->ind_buf.bo);
r300->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
r300->ind_buf.count = mesa_ind_buf->count;
if (mapped_named_bo) {
ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
}
} else {
r300FixupIndexBuffer(ctx, mesa_ind_buf);
}
}
#define CONVERT( TYPE, MACRO ) do { \
GLuint i, j, sz; \
sz = input->Size; \
if (input->Normalized) { \
for (i = 0; i < count; i++) { \
const TYPE *in = (TYPE *)src_ptr; \
for (j = 0; j < sz; j++) { \
*dst_ptr++ = MACRO(*in); \
in++; \
} \
src_ptr += stride; \
} \
} else { \
for (i = 0; i < count; i++) { \
const TYPE *in = (TYPE *)src_ptr; \
for (j = 0; j < sz; j++) { \
*dst_ptr++ = (GLfloat)(*in); \
in++; \
} \
src_ptr += stride; \
} \
} \
} while (0)
/**
* Convert attribute data type to float
* If the attribute uses named buffer object replace the bo with newly allocated bo
*/
static void r300ConvertAttrib(struct gl_context *ctx, int count, const struct gl_client_array *input, struct vertex_attribute *attr)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
const GLvoid *src_ptr;
GLboolean mapped_named_bo = GL_FALSE;
GLfloat *dst_ptr;
GLuint stride;
stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB;
/* Convert value for first element only */
if (input->StrideB == 0)
count = 1;
if (input->BufferObj->Name) {
if (!input->BufferObj->Pointer) {
ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
GL_MAP_READ_BIT, input->BufferObj);
mapped_named_bo = GL_TRUE;
}
src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
} else {
src_ptr = input->Ptr;
}
radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, sizeof(GLfloat) * input->Size * count, 32);
radeon_bo_map(attr->bo, 1);
dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
"%s: Converting vertex attributes, attribute data format %x,"
"stride %d, components %d\n"
, __FUNCTION__, input->Type
, stride, input->Size);
assert(src_ptr != NULL);
switch (input->Type) {
case GL_DOUBLE:
CONVERT(GLdouble, (GLfloat));
break;
case GL_UNSIGNED_INT:
CONVERT(GLuint, UINT_TO_FLOAT);
break;
case GL_INT:
CONVERT(GLint, INT_TO_FLOAT);
break;
case GL_UNSIGNED_SHORT:
CONVERT(GLushort, USHORT_TO_FLOAT);
break;
case GL_SHORT:
CONVERT(GLshort, SHORT_TO_FLOAT);
break;
case GL_UNSIGNED_BYTE:
assert(input->Format != GL_BGRA);
CONVERT(GLubyte, UBYTE_TO_FLOAT);
break;
case GL_BYTE:
CONVERT(GLbyte, BYTE_TO_FLOAT);
break;
default:
assert(0);
break;
}
radeon_bo_unmap(attr->bo);
if (mapped_named_bo) {
ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
}
}
static void r300AlignDataToDword(struct gl_context *ctx, const struct gl_client_array *input, int count, struct vertex_attribute *attr)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
const int dst_stride = (input->StrideB + 3) & ~3;
const int size = getTypeSize(input->Type) * input->Size * count;
GLboolean mapped_named_bo = GL_FALSE;
radeonAllocDmaRegion(&r300->radeon, &attr->bo, &attr->bo_offset, size, 32);
radeon_bo_map(attr->bo, 1);
if (!input->BufferObj->Pointer) {
ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
GL_MAP_READ_BIT, input->BufferObj);
mapped_named_bo = GL_TRUE;
}
radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT, "%s. Vertex alignment doesn't match hw requirements.\n", __func__);
{
GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
int i;
for (i = 0; i < count; ++i) {
memcpy(dst_ptr, src_ptr, input->StrideB);
src_ptr += input->StrideB;
dst_ptr += dst_stride;
}
}
if (mapped_named_bo) {
ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
}
radeon_bo_unmap(attr->bo);
attr->stride = dst_stride;
}
static void r300TranslateAttrib(struct gl_context *ctx, GLuint attr, int count, const struct gl_client_array *input)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
struct r300_vertex_buffer *vbuf = &r300->vbuf;
struct vertex_attribute r300_attr = { 0 };
GLenum type;
GLuint stride;
radeon_print(RADEON_RENDER, RADEON_TRACE, "%s\n", __func__);
stride = (input->StrideB == 0) ? getTypeSize(input->Type) * input->Size : input->StrideB;
if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT ||
#if MESA_BIG_ENDIAN
getTypeSize(input->Type) != 4 ||
#endif
stride < 4) {
type = GL_FLOAT;
if (input->StrideB == 0) {
r300_attr.stride = 0;
} else {
r300_attr.stride = sizeof(GLfloat) * input->Size;
}
r300_attr.dwords = input->Size;
r300_attr.is_named_bo = GL_FALSE;
} else {
type = input->Type;
r300_attr.dwords = (getTypeSize(type) * input->Size + 3)/ 4;
if (!input->BufferObj->Name) {
if (input->StrideB == 0) {
r300_attr.stride = 0;
} else {
r300_attr.stride = (getTypeSize(type) * input->Size + 3) & ~3;
}
r300_attr.is_named_bo = GL_FALSE;
}
}
r300_attr.size = input->Size;
r300_attr.element = attr;
r300_attr.dst_loc = vbuf->num_attribs;
switch (type) {
case GL_FLOAT:
switch (input->Size) {
case 1: r300_attr.data_type = R300_DATA_TYPE_FLOAT_1; break;
case 2: r300_attr.data_type = R300_DATA_TYPE_FLOAT_2; break;
case 3: r300_attr.data_type = R300_DATA_TYPE_FLOAT_3; break;
case 4: r300_attr.data_type = R300_DATA_TYPE_FLOAT_4; break;
}
r300_attr._signed = 0;
r300_attr.normalize = 0;
break;
case GL_HALF_FLOAT:
switch (input->Size) {
case 1:
case 2:
r300_attr.data_type = R300_DATA_TYPE_FLT16_2;
break;
case 3:
case 4:
r300_attr.data_type = R300_DATA_TYPE_FLT16_4;
break;
}
break;
case GL_SHORT:
r300_attr._signed = 1;
r300_attr.normalize = input->Normalized;
switch (input->Size) {
case 1:
case 2:
r300_attr.data_type = R300_DATA_TYPE_SHORT_2;
break;
case 3:
case 4:
r300_attr.data_type = R300_DATA_TYPE_SHORT_4;
break;
}
break;
case GL_BYTE:
r300_attr._signed = 1;
r300_attr.normalize = input->Normalized;
r300_attr.data_type = R300_DATA_TYPE_BYTE;
break;
case GL_UNSIGNED_SHORT:
r300_attr._signed = 0;
r300_attr.normalize = input->Normalized;
switch (input->Size) {
case 1:
case 2:
r300_attr.data_type = R300_DATA_TYPE_SHORT_2;
break;
case 3:
case 4:
r300_attr.data_type = R300_DATA_TYPE_SHORT_4;
break;
}
break;
case GL_UNSIGNED_BYTE:
r300_attr._signed = 0;
r300_attr.normalize = input->Normalized;
if (input->Format == GL_BGRA)
r300_attr.data_type = R300_DATA_TYPE_D3DCOLOR;
else
r300_attr.data_type = R300_DATA_TYPE_BYTE;
break;
default:
case GL_DOUBLE:
case GL_INT:
case GL_UNSIGNED_INT:
assert(0);
break;
}
switch (input->Size) {
case 4:
r300_attr.swizzle = SWIZZLE_XYZW;
break;
case 3:
r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
break;
case 2:
r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE);
break;
case 1:
r300_attr.swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE);
break;
}
r300_attr.write_mask = MASK_XYZW;
vbuf->attribs[vbuf->num_attribs] = r300_attr;
++vbuf->num_attribs;
}
static void r300SetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
struct r300_vertex_buffer *vbuf = &r300->vbuf;
radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s\n", __func__);
{
int i, tmp;
tmp = r300->selected_vp->code.InputsRead;
i = 0;
vbuf->num_attribs = 0;
while (tmp) {
/* find first enabled bit */
while (!(tmp & 1)) {
tmp >>= 1;
++i;
}
r300TranslateAttrib(ctx, i, count, arrays[i]);
tmp >>= 1;
++i;
}
}
r300SwitchFallback(ctx, R300_FALLBACK_AOS_LIMIT, vbuf->num_attribs > R300_MAX_AOS_ARRAYS);
if (r300->fallback)
return;
}
static void r300AllocDmaRegions(struct gl_context *ctx, const struct gl_client_array *input[], int count)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
struct r300_vertex_buffer *vbuf = &r300->vbuf;
GLuint stride;
int ret;
int i, index;
radeon_print(RADEON_RENDER, RADEON_VERBOSE,
"%s: count %d num_attribs %d\n",
__func__, count, vbuf->num_attribs);
for (index = 0; index < vbuf->num_attribs; index++) {
struct radeon_aos *aos = &r300->radeon.tcl.aos[index];
i = vbuf->attribs[index].element;
stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT ||
#if MESA_BIG_ENDIAN
getTypeSize(input[i]->Type) != 4 ||
#endif
stride < 4) {
r300ConvertAttrib(ctx, count, input[i], &vbuf->attribs[index]);
} else {
if (input[i]->BufferObj->Name) {
if (stride % 4 != 0 || (intptr_t)input[i]->Ptr % 4 != 0) {
r300AlignDataToDword(ctx, input[i], count, &vbuf->attribs[index]);
vbuf->attribs[index].is_named_bo = GL_FALSE;
} else {
vbuf->attribs[index].stride = input[i]->StrideB;
vbuf->attribs[index].bo_offset = (intptr_t) input[i]->Ptr;
vbuf->attribs[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
vbuf->attribs[index].is_named_bo = GL_TRUE;
}
} else {
int size;
int local_count = count;
uint32_t *dst;
if (input[i]->StrideB == 0) {
size = getTypeSize(input[i]->Type) * input[i]->Size;
local_count = 1;
} else {
size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
}
radeonAllocDmaRegion(&r300->radeon, &vbuf->attribs[index].bo, &vbuf->attribs[index].bo_offset, size, 32);
radeon_bo_map(vbuf->attribs[index].bo, 1);
assert(vbuf->attribs[index].bo->ptr != NULL);
dst = (uint32_t *)ADD_POINTERS(vbuf->attribs[index].bo->ptr, vbuf->attribs[index].bo_offset);
switch (vbuf->attribs[index].dwords) {
case 1: radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
case 2: radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
case 3: radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
case 4: radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count); break;
default: assert(0); break;
}
radeon_bo_unmap(vbuf->attribs[index].bo);
}
}
aos->count = vbuf->attribs[index].stride == 0 ? 1 : count;
aos->stride = vbuf->attribs[index].stride / sizeof(float);
aos->components = vbuf->attribs[index].dwords;
aos->bo = vbuf->attribs[index].bo;
aos->offset = vbuf->attribs[index].bo_offset;
if (vbuf->attribs[index].is_named_bo) {
radeon_cs_space_add_persistent_bo(r300->radeon.cmdbuf.cs, r300->vbuf.attribs[index].bo, RADEON_GEM_DOMAIN_GTT, 0);
}
}
r300->radeon.tcl.aos_count = vbuf->num_attribs;
ret = radeon_cs_space_check_with_bo(r300->radeon.cmdbuf.cs, first_elem(&r300->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, ret);
}
static void r300FreeData(struct gl_context *ctx)
{
/* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
* to prevent double unref in radeonReleaseArrays
* called during context destroy
*/
radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s\n", __func__);
r300ContextPtr r300 = R300_CONTEXT(ctx);
{
int i;
for (i = 0; i < r300->vbuf.num_attribs; i++) {
if (!r300->vbuf.attribs[i].is_named_bo) {
radeon_bo_unref(r300->vbuf.attribs[i].bo);
}
r300->radeon.tcl.aos[i].bo = NULL;
}
}
{
if (r300->ind_buf.bo != NULL) {
radeon_bo_unref(r300->ind_buf.bo);
}
}
}
static GLuint r300PredictTryDrawPrimsSize(struct gl_context *ctx,
GLuint nr_prims, const struct _mesa_prim *prim)
{
struct r300_context *r300 = R300_CONTEXT(ctx);
struct r300_vertex_buffer *vbuf = &r300->vbuf;
GLboolean flushed;
GLuint dwords;
GLuint state_size;
int i;
GLuint extra_prims = 0;
/* Check for primitive splitting. */
for (i = 0; i < nr_prims; ++i) {
const GLuint num_verts = r300NumVerts(r300, prim[i].count, prim[i].mode);
extra_prims += num_verts/(65535 - 32);
}
nr_prims += extra_prims;
dwords = 2*CACHE_FLUSH_BUFSZ;
dwords += PRE_EMIT_STATE_BUFSZ;
dwords += (AOS_BUFSZ(vbuf->num_attribs)
+ SCISSORS_BUFSZ*2
+ FIREAOS_BUFSZ )*nr_prims;
state_size = radeonCountStateEmitSize(&r300->radeon);
flushed = rcommonEnsureCmdBufSpace(&r300->radeon,
dwords + state_size,
__FUNCTION__);
if (flushed)
dwords += radeonCountStateEmitSize(&r300->radeon);
else
dwords += state_size;
radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
return dwords;
}
static GLboolean r300TryDrawPrims(struct gl_context *ctx,
const struct gl_client_array *arrays[],
const struct _mesa_prim *prim,
GLuint nr_prims,
const struct _mesa_index_buffer *ib,
GLuint min_index,
GLuint max_index )
{
struct r300_context *r300 = R300_CONTEXT(ctx);
GLuint i;
radeon_print(RADEON_RENDER, RADEON_NORMAL, "%s: %u (%d-%d) cs begin at %d\n",
__FUNCTION__, nr_prims, min_index, max_index, r300->radeon.cmdbuf.cs->cdw );
if (ctx->NewState)
_mesa_update_state( ctx );
if (r300->options.hw_tcl_enabled)
_tnl_UpdateFixedFunctionProgram(ctx);
r300UpdateShaders(r300);
r300SwitchFallback(ctx, R300_FALLBACK_INVALID_BUFFERS, !r300ValidateBuffers(ctx));
r300SetVertexFormat(ctx, arrays, max_index + 1);
if (r300->fallback)
return GL_FALSE;
r300SetupVAP(ctx, r300->selected_vp->code.InputsRead, r300->selected_vp->code.OutputsWritten);
r300UpdateShaderStates(r300);
/* ensure we have the cmd buf space in advance to cover
* the state + DMA AOS pointers */
GLuint emit_end = r300PredictTryDrawPrimsSize(ctx, nr_prims, prim)
+ r300->radeon.cmdbuf.cs->cdw;
r300SetupIndexBuffer(ctx, ib);
r300AllocDmaRegions(ctx, arrays, max_index + 1);
if (r300->fallback)
return GL_FALSE;
r300EmitCacheFlush(r300);
radeonEmitState(&r300->radeon);
for (i = 0; i < nr_prims; ++i) {
r300RunRenderPrimitive(ctx, prim[i].start, prim[i].start + prim[i].count, prim[i].mode);
}
r300EmitCacheFlush(r300);
r300FreeData(ctx);
radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: %u (%d-%d) cs ending at %d\n",
__FUNCTION__, nr_prims, min_index, max_index, r300->radeon.cmdbuf.cs->cdw );
if (emit_end < r300->radeon.cmdbuf.cs->cdw)
WARN_ONCE("Rendering was %d commands larger than predicted size."
" We might overflow command buffer.\n", r300->radeon.cmdbuf.cs->cdw - emit_end);
return GL_TRUE;
}
static void r300DrawPrims(struct gl_context *ctx,
const struct gl_client_array *arrays[],
const struct _mesa_prim *prim,
GLuint nr_prims,
const struct _mesa_index_buffer *ib,
GLboolean index_bounds_valid,
GLuint min_index,
GLuint max_index)
{
GLboolean retval;
struct r300_context *r300 = R300_CONTEXT(ctx);
radeonContextPtr radeon = &r300->radeon;
radeon_prepare_render(radeon);
/* This check should get folded into just the places that
* min/max index are really needed.
*/
if (!index_bounds_valid) {
vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
}
if (min_index) {
radeon_print(RADEON_FALLBACKS, RADEON_IMPORTANT,
"%s: Rebasing primitives. %p nr_prims %d min_index %u max_index %u\n",
__func__, prim, nr_prims, min_index, max_index);
vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, r300DrawPrims );
return;
}
/* Make an attempt at drawing */
retval = r300TryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
/* If failed run tnl pipeline - it should take care of fallbacks */
if (!retval)
_tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
}
void r300InitDraw(struct gl_context *ctx)
{
struct vbo_context *vbo = vbo_context(ctx);
vbo->draw_prims = r300DrawPrims;
}

135
src/mesa/drivers/dri/r300/r300_emit.c
View file

@ -1,135 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file
*
* \author Keith Whitwell <keith@tungstengraphics.com>
* \author Maciej Cencora <m.cencora@gmail.com>
*/
#include "main/glheader.h"
#include "main/mtypes.h"
#include "main/colormac.h"
#include "main/imports.h"
#include "main/macros.h"
#include "swrast_setup/swrast_setup.h"
#include "tnl/tnl.h"
#include "tnl/t_context.h"
#include "r300_context.h"
#include "r300_emit.h"
GLuint r300VAPInputCntl0(struct gl_context * ctx, GLuint InputsRead)
{
/* No idea what this value means. I have seen other values written to
* this register... */
return 0x5555;
}
GLuint r300VAPInputCntl1(struct gl_context * ctx, GLuint InputsRead)
{
GLuint i, vic_1 = 0;
if (InputsRead & (1 << VERT_ATTRIB_POS))
vic_1 |= R300_INPUT_CNTL_POS;
if (InputsRead & (1 << VERT_ATTRIB_NORMAL))
vic_1 |= R300_INPUT_CNTL_NORMAL;
if (InputsRead & (1 << VERT_ATTRIB_COLOR0))
vic_1 |= R300_INPUT_CNTL_COLOR;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++)
if (InputsRead & (1 << (VERT_ATTRIB_TEX0 + i))) {
vic_1 |= R300_INPUT_CNTL_TC0 << i;
}
return vic_1;
}
GLuint r300VAPOutputCntl0(struct gl_context * ctx, GLuint vp_writes)
{
GLuint ret = 0;
if (vp_writes & (1 << VERT_RESULT_HPOS))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT;
if (vp_writes & (1 << VERT_RESULT_COL0))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT;
if (vp_writes & (1 << VERT_RESULT_COL1))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT;
/* Two sided lighting works only if all 4 colors are written */
if (vp_writes & (1 << VERT_RESULT_BFC0) || vp_writes & (1 << VERT_RESULT_BFC1))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__COLOR_0_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT |
R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT | R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT;
if (vp_writes & (1 << VERT_RESULT_PSIZ))
ret |= R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT;
return ret;
}
GLuint r300VAPOutputCntl1(struct gl_context * ctx, GLuint vp_writes)
{
GLuint i, ret = 0, first_free_texcoord = 0;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (vp_writes & (1 << (VERT_RESULT_TEX0 + i))) {
ret |= (4 << (3 * first_free_texcoord));
++first_free_texcoord;
}
}
if (first_free_texcoord > 8) {
fprintf(stderr, "\tout of free texcoords\n");
exit(-1);
}
return ret;
}
void r300EmitCacheFlush(r300ContextPtr rmesa)
{
BATCH_LOCALS(&rmesa->radeon);
BEGIN_BATCH_NO_AUTOSTATE(4);
OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT,
R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
OUT_BATCH_REGVAL(R300_ZB_ZCACHE_CTLSTAT,
R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
END_BATCH();
COMMIT_BATCH();
}

228
src/mesa/drivers/dri/r300/r300_emit.h
View file

@ -1,228 +0,0 @@
/*
* Copyright (C) 2005 Vladimir Dergachev.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/*
* Authors:
* Vladimir Dergachev <volodya@mindspring.com>
* Nicolai Haehnle <prefect_@gmx.net>
* Aapo Tahkola <aet@rasterburn.org>
* Ben Skeggs <darktama@iinet.net.au>
* Jerome Glisse <j.glisse@gmail.com>
*/
/* This files defines functions for accessing R300 hardware.
*/
#ifndef __R300_EMIT_H__
#define __R300_EMIT_H__
#include "main/glheader.h"
#include "r300_context.h"
#include "r300_cmdbuf.h"
static INLINE uint32_t cmdpacket0(struct radeon_screen *rscrn,
int reg, int count)
{
if (!rscrn->kernel_mm) {
drm_r300_cmd_header_t cmd;
cmd.u = 0;
cmd.packet0.cmd_type = R300_CMD_PACKET0;
cmd.packet0.count = count;
cmd.packet0.reghi = ((unsigned int)reg & 0xFF00) >> 8;
cmd.packet0.reglo = ((unsigned int)reg & 0x00FF);
return cmd.u;
}
if (count) {
return CP_PACKET0(reg, count - 1);
}
return CP_PACKET2;
}
static INLINE uint32_t cmdvpu(struct radeon_screen *rscrn, int addr, int count)
{
drm_r300_cmd_header_t cmd;
cmd.u = 0;
cmd.vpu.cmd_type = R300_CMD_VPU;
cmd.vpu.count = count;
cmd.vpu.adrhi = ((unsigned int)addr & 0xFF00) >> 8;
cmd.vpu.adrlo = ((unsigned int)addr & 0x00FF);
return cmd.u;
}
static INLINE uint32_t cmdr500fp(struct radeon_screen *rscrn,
int addr, int count, int type, int clamp)
{
drm_r300_cmd_header_t cmd;
cmd.u = 0;
cmd.r500fp.cmd_type = R300_CMD_R500FP;
cmd.r500fp.count = count;
cmd.r500fp.adrhi_flags = ((unsigned int)addr & 0x100) >> 8;
cmd.r500fp.adrhi_flags |= type ? R500FP_CONSTANT_TYPE : 0;
cmd.r500fp.adrhi_flags |= clamp ? R500FP_CONSTANT_CLAMP : 0;
cmd.r500fp.adrlo = ((unsigned int)addr & 0x00FF);
return cmd.u;
}
static INLINE uint32_t cmdpacket3(struct radeon_screen *rscrn, int packet)
{
drm_r300_cmd_header_t cmd;
cmd.u = 0;
cmd.packet3.cmd_type = R300_CMD_PACKET3;
cmd.packet3.packet = packet;
return cmd.u;
}
static INLINE uint32_t cmdcpdelay(struct radeon_screen *rscrn,
unsigned short count)
{
drm_r300_cmd_header_t cmd;
cmd.u = 0;
cmd.delay.cmd_type = R300_CMD_CP_DELAY;
cmd.delay.count = count;
return cmd.u;
}
static INLINE uint32_t cmdwait(struct radeon_screen *rscrn,
unsigned char flags)
{
drm_r300_cmd_header_t cmd;
cmd.u = 0;
cmd.wait.cmd_type = R300_CMD_WAIT;
cmd.wait.flags = flags;
return cmd.u;
}
static INLINE uint32_t cmdpacify(struct radeon_screen *rscrn)
{
drm_r300_cmd_header_t cmd;
cmd.u = 0;
cmd.header.cmd_type = R300_CMD_END3D;
return cmd.u;
}
/**
* Write the header of a packet3 to the command buffer.
* Outputs 2 dwords and expects (num_extra+1) additional dwords afterwards.
*/
#define OUT_BATCH_PACKET3(packet, num_extra) do {\
if (!b_l_rmesa->radeonScreen->kernel_mm) { \
OUT_BATCH(cmdpacket3(b_l_rmesa->radeonScreen,\
R300_CMD_PACKET3_RAW)); \
} else b_l_rmesa->cmdbuf.cs->section_cdw++;\
OUT_BATCH(CP_PACKET3((packet), (num_extra))); \
} while(0)
/**
* Must be sent to switch to 2d commands
*/
void static INLINE end_3d(radeonContextPtr radeon)
{
BATCH_LOCALS(radeon);
if (!radeon->radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdpacify(radeon->radeonScreen));
END_BATCH();
}
}
void static INLINE cp_delay(r300ContextPtr rmesa, unsigned short count)
{
BATCH_LOCALS(&rmesa->radeon);
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdcpdelay(rmesa->radeon.radeonScreen, count));
END_BATCH();
}
}
void static INLINE cp_wait(radeonContextPtr radeon, unsigned char flags)
{
BATCH_LOCALS(radeon);
uint32_t wait_until;
if (!radeon->radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(1);
OUT_BATCH(cmdwait(radeon->radeonScreen, flags));
END_BATCH();
} else {
switch(flags) {
case R300_WAIT_2D:
wait_until = (1 << 14);
break;
case R300_WAIT_3D:
wait_until = (1 << 15);
break;
case R300_NEW_WAIT_2D_3D:
wait_until = (1 << 14) | (1 << 15);
break;
case R300_NEW_WAIT_2D_2D_CLEAN:
wait_until = (1 << 14) | (1 << 16) | (1 << 18);
break;
case R300_NEW_WAIT_3D_3D_CLEAN:
wait_until = (1 << 15) | (1 << 17) | (1 << 18);
break;
case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
wait_until = (1 << 14) | (1 << 16) | (1 << 18);
wait_until |= (1 << 15) | (1 << 17) | (1 << 18);
break;
default:
return;
}
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
OUT_BATCH(wait_until);
END_BATCH();
}
}
extern int r300PrimitiveType(r300ContextPtr rmesa, int prim);
extern int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim);
extern void r300EmitCacheFlush(r300ContextPtr rmesa);
extern GLuint r300VAPInputCntl0(struct gl_context * ctx, GLuint InputsRead);
extern GLuint r300VAPInputCntl1(struct gl_context * ctx, GLuint InputsRead);
extern GLuint r300VAPOutputCntl0(struct gl_context * ctx, GLuint vp_writes);
extern GLuint r300VAPOutputCntl1(struct gl_context * ctx, GLuint vp_writes);
#endif

310
src/mesa/drivers/dri/r300/r300_fragprog_common.c
View file

@ -1,310 +0,0 @@
/*
* Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/**
* \file
*
* Fragment program compiler. Perform transformations on the intermediate
* representation until the program is in a form where we can translate
* it more or less directly into machine-readable form.
*
* \author Ben Skeggs <darktama@iinet.net.au>
* \author Jerome Glisse <j.glisse@gmail.com>
*/
#include "r300_fragprog_common.h"
#include "program/prog_print.h"
#include "compiler/radeon_compiler.h"
#include "radeon_mesa_to_rc.h"
static GLuint build_dts(GLuint depthmode)
{
switch(depthmode) {
default:
case GL_LUMINANCE: return RC_SWIZZLE_XYZZ;
case GL_INTENSITY: return RC_SWIZZLE_XYZW;
case GL_ALPHA: return RC_SWIZZLE_WWWW;
}
}
static GLuint build_func(GLuint comparefunc)
{
return comparefunc - GL_NEVER;
}
/**
* Collect all external state that is relevant for compiling the given
* fragment program.
*/
static void build_state(
r300ContextPtr r300,
struct gl_fragment_program *fp,
struct r300_fragment_program_external_state *state)
{
int unit;
memset(state, 0, sizeof(*state));
for(unit = 0; unit < 16; ++unit) {
if (fp->Base.ShadowSamplers & (1 << unit)) {
struct gl_texture_object* tex = r300->radeon.glCtx->Texture.Unit[unit]._Current;
state->unit[unit].texture_swizzle = build_dts(tex->Sampler.DepthMode);
state->unit[unit].texture_compare_func = build_func(tex->Sampler.CompareFunc);
}
}
}
/**
* Transform the program to support fragment.position.
*
* Introduce a small fragment at the start of the program that will be
* the only code that directly reads the FRAG_ATTRIB_WPOS input.
* All other code pieces that reference that input will be rewritten
* to read from a newly allocated temporary.
*
*/
static void insert_WPOS_trailer(struct r300_fragment_program_compiler *compiler, struct r300_fragment_program * fp)
{
int i;
fp->wpos_attr = FRAG_ATTRIB_MAX;
if (!(compiler->Base.Program.InputsRead & FRAG_BIT_WPOS)) {
return;
}
for (i = FRAG_ATTRIB_TEX0; i <= FRAG_ATTRIB_TEX7; ++i)
{
if (!(compiler->Base.Program.InputsRead & (1 << i))) {
fp->wpos_attr = i;
break;
}
}
/* No free texcoord found, fall-back to software rendering */
if (fp->wpos_attr == FRAG_ATTRIB_MAX)
{
compiler->Base.Error = 1;
return;
}
rc_transform_fragment_wpos(&compiler->Base, FRAG_ATTRIB_WPOS, fp->wpos_attr, GL_FALSE);
}
/**
* Rewrite fragment.fogcoord to use a texture coordinate slot.
* Note that fogcoord is forced into an X001 pattern, and this enforcement
* is done here.
*
* See also the counterpart rewriting for vertex programs.
*/
static void rewriteFog(struct r300_fragment_program_compiler *compiler, struct r300_fragment_program * fp)
{
struct rc_src_register src;
int i;
fp->fog_attr = FRAG_ATTRIB_MAX;
if (!(compiler->Base.Program.InputsRead & FRAG_BIT_FOGC)) {
return;
}
for (i = FRAG_ATTRIB_TEX0; i <= FRAG_ATTRIB_TEX7; ++i)
{
if (!(compiler->Base.Program.InputsRead & (1 << i))) {
fp->fog_attr = i;
break;
}
}
/* No free texcoord found, fall-back to software rendering */
if (fp->fog_attr == FRAG_ATTRIB_MAX)
{
compiler->Base.Error = 1;
return;
}
memset(&src, 0, sizeof(src));
src.File = RC_FILE_INPUT;
src.Index = fp->fog_attr;
src.Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE);
rc_move_input(&compiler->Base, FRAG_ATTRIB_FOGC, src);
}
/**
* Reserve hardware temporary registers for the program inputs.
*
* @note This allocation is performed explicitly, because the order of inputs
* is determined by the RS hardware.
*/
static void allocate_hw_inputs(
struct r300_fragment_program_compiler * c,
void (*allocate)(void * data, unsigned input, unsigned hwreg),
void * mydata)
{
GLuint InputsRead = c->Base.Program.InputsRead;
int i;
GLuint hwindex = 0;
/* Primary colour */
if (InputsRead & FRAG_BIT_COL0)
allocate(mydata, FRAG_ATTRIB_COL0, hwindex++);
InputsRead &= ~FRAG_BIT_COL0;
/* Secondary color */
if (InputsRead & FRAG_BIT_COL1)
allocate(mydata, FRAG_ATTRIB_COL1, hwindex++);
InputsRead &= ~FRAG_BIT_COL1;
/* Texcoords */
for (i = 0; i < 8; i++) {
if (InputsRead & (FRAG_BIT_TEX0 << i))
allocate(mydata, FRAG_ATTRIB_TEX0+i, hwindex++);
}
InputsRead &= ~FRAG_BITS_TEX_ANY;
/* Fogcoords treated as a texcoord */
if (InputsRead & FRAG_BIT_FOGC)
allocate(mydata, FRAG_ATTRIB_FOGC, hwindex++);
InputsRead &= ~FRAG_BIT_FOGC;
/* fragment position treated as a texcoord */
if (InputsRead & FRAG_BIT_WPOS)
allocate(mydata, FRAG_ATTRIB_WPOS, hwindex++);
InputsRead &= ~FRAG_BIT_WPOS;
/* Anything else */
if (InputsRead)
rc_error(&c->Base, "Don't know how to handle inputs 0x%x\n", InputsRead);
}
static void translate_fragment_program(struct gl_context *ctx, struct r300_fragment_program_cont *cont, struct r300_fragment_program *fp)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
struct r300_fragment_program_compiler compiler;
memset(&compiler, 0, sizeof(compiler));
rc_init(&compiler.Base);
compiler.Base.Debug = (RADEON_DEBUG & RADEON_PIXEL) ? GL_TRUE : GL_FALSE;
compiler.code = &fp->code;
compiler.state = fp->state;
compiler.enable_shadow_ambient = GL_TRUE;
compiler.Base.is_r500 = (r300->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) ? GL_TRUE : GL_FALSE;
compiler.Base.disable_optimizations = 0;
compiler.Base.has_half_swizzles = 1;
compiler.Base.max_temp_regs = (compiler.Base.is_r500) ? 128 : 32;
compiler.Base.max_constants = compiler.Base.is_r500 ? 256 : 32;
compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 512 : 64;
compiler.Base.max_tex_insts = compiler.Base.is_r500 ? 512 : 32;
compiler.OutputDepth = FRAG_RESULT_DEPTH;
memset(compiler.OutputColor, 0, 4 * sizeof(unsigned));
compiler.OutputColor[0] = FRAG_RESULT_COLOR;
compiler.AllocateHwInputs = &allocate_hw_inputs;
if (compiler.Base.Debug) {
fflush(stderr);
printf("Fragment Program: Initial program:\n");
_mesa_print_program(&cont->Base.Base);
fflush(stderr);
}
radeon_mesa_to_rc_program(&compiler.Base, &cont->Base.Base);
insert_WPOS_trailer(&compiler, fp);
rewriteFog(&compiler, fp);
r3xx_compile_fragment_program(&compiler);
if (compiler.Base.is_r500) {
/* We need to support the non-KMS DRM interface, which
* artificially limits the number of instructions and
* constants which are available to us.
*
* See also the comment in r300_context.c where we
* set the MAX_NATIVE_xxx values.
*/
if (fp->code.code.r500.inst_end >= 255 || fp->code.constants.Count > 255)
rc_error(&compiler.Base, "Program is too big (upgrade to r300g to avoid this limitation).\n");
}
fp->error = compiler.Base.Error;
fp->InputsRead = compiler.Base.Program.InputsRead;
/* Clear the fog/wpos_attr if code accessing these
* attributes has been removed during compilation
*/
if (fp->fog_attr != FRAG_ATTRIB_MAX) {
if (!(fp->InputsRead & (1 << fp->fog_attr)))
fp->fog_attr = FRAG_ATTRIB_MAX;
}
if (fp->wpos_attr != FRAG_ATTRIB_MAX) {
if (!(fp->InputsRead & (1 << fp->wpos_attr)))
fp->wpos_attr = FRAG_ATTRIB_MAX;
}
rc_destroy(&compiler.Base);
}
struct r300_fragment_program *r300SelectAndTranslateFragmentShader(struct gl_context *ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
struct r300_fragment_program_cont *fp_list;
struct r300_fragment_program *fp;
struct r300_fragment_program_external_state state;
fp_list = (struct r300_fragment_program_cont *)ctx->FragmentProgram._Current;
build_state(r300, ctx->FragmentProgram._Current, &state);
fp = fp_list->progs;
while (fp) {
if (memcmp(&fp->state, &state, sizeof(state)) == 0) {
return r300->selected_fp = fp;
}
fp = fp->next;
}
fp = calloc(1, sizeof(struct r300_fragment_program));
fp->state = state;
fp->next = fp_list->progs;
fp_list->progs = fp;
translate_fragment_program(ctx, fp_list, fp);
return r300->selected_fp = fp;
}

37
src/mesa/drivers/dri/r300/r300_fragprog_common.h
View file

@ -1,37 +0,0 @@
/*
* Copyright (C) 2009 Maciej Cencora <m.cencora@gmail.com>
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __R300_FRAGPROG_COMMON_H_
#define __R300_FRAGPROG_COMMON_H_
#include "main/mtypes.h"
#include "r300_context.h"
struct r300_fragment_program *r300SelectAndTranslateFragmentShader(struct gl_context *ctx);
#endif

3378
src/mesa/drivers/dri/r300/r300_reg.h
View file

File diff suppressed because it is too large Load diff

505
src/mesa/drivers/dri/r300/r300_render.c
View file

@ -1,505 +0,0 @@
/**************************************************************************
Copyright (C) 2004 Nicolai Haehnle.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file
*
* \brief R300 Render (Vertex Buffer Implementation)
*
* The immediate implementation has been removed from CVS in favor of the vertex
* buffer implementation.
*
* The render functions are called by the pipeline manager to render a batch of
* primitives. They return TRUE to pass on to the next stage (i.e. software
* rasterization) or FALSE to indicate that the pipeline has finished after
* rendering something.
*
* When falling back to software TCL still attempt to use hardware
* rasterization.
*
* I am not sure that the cache related registers are setup correctly, but
* obviously this does work... Further investigation is needed.
*
* \author Nicolai Haehnle <prefect_@gmx.net>
*
* \todo Add immediate implementation back? Perhaps this is useful if there are
* no bugs...
*/
#include "r300_render.h"
#include "main/glheader.h"
#include "main/imports.h"
#include "main/enums.h"
#include "main/macros.h"
#include "main/context.h"
#include "main/dd.h"
#include "main/simple_list.h"
#include "main/api_arrayelt.h"
#include "swrast/swrast.h"
#include "swrast_setup/swrast_setup.h"
#include "vbo/vbo.h"
#include "vbo/vbo_split.h"
#include "r300_context.h"
#include "r300_state.h"
#include "r300_reg.h"
#include "r300_emit.h"
#include "r300_swtcl.h"
/**
* \brief Convert a OpenGL primitive type into a R300 primitive type.
*/
int r300PrimitiveType(r300ContextPtr rmesa, int prim)
{
switch (prim & PRIM_MODE_MASK) {
case GL_POINTS:
return R300_VAP_VF_CNTL__PRIM_POINTS;
break;
case GL_LINES:
return R300_VAP_VF_CNTL__PRIM_LINES;
break;
case GL_LINE_STRIP:
return R300_VAP_VF_CNTL__PRIM_LINE_STRIP;
break;
case GL_LINE_LOOP:
return R300_VAP_VF_CNTL__PRIM_LINE_LOOP;
break;
case GL_TRIANGLES:
return R300_VAP_VF_CNTL__PRIM_TRIANGLES;
break;
case GL_TRIANGLE_STRIP:
return R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP;
break;
case GL_TRIANGLE_FAN:
return R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN;
break;
case GL_QUADS:
return R300_VAP_VF_CNTL__PRIM_QUADS;
break;
case GL_QUAD_STRIP:
return R300_VAP_VF_CNTL__PRIM_QUAD_STRIP;
break;
case GL_POLYGON:
return R300_VAP_VF_CNTL__PRIM_POLYGON;
break;
default:
assert(0);
return -1;
break;
}
}
int r300NumVerts(r300ContextPtr rmesa, int num_verts, int prim)
{
int verts_off = 0;
switch (prim & PRIM_MODE_MASK) {
case GL_POINTS:
verts_off = 0;
break;
case GL_LINES:
verts_off = num_verts % 2;
break;
case GL_LINE_STRIP:
if (num_verts < 2)
verts_off = num_verts;
break;
case GL_LINE_LOOP:
if (num_verts < 2)
verts_off = num_verts;
break;
case GL_TRIANGLES:
verts_off = num_verts % 3;
break;
case GL_TRIANGLE_STRIP:
if (num_verts < 3)
verts_off = num_verts;
break;
case GL_TRIANGLE_FAN:
if (num_verts < 3)
verts_off = num_verts;
break;
case GL_QUADS:
verts_off = num_verts % 4;
break;
case GL_QUAD_STRIP:
if (num_verts < 4)
verts_off = num_verts;
else
verts_off = num_verts % 2;
break;
case GL_POLYGON:
if (num_verts < 3)
verts_off = num_verts;
break;
default:
assert(0);
return -1;
break;
}
return num_verts - verts_off;
}
static void r300FireEB(r300ContextPtr rmesa, int vertex_count, int type, int offset)
{
BATCH_LOCALS(&rmesa->radeon);
int size;
/* offset is in indices */
BEGIN_BATCH(10);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_INDX_2, 0);
if (rmesa->ind_buf.is_32bit) {
/* convert to bytes */
offset *= 4;
size = vertex_count;
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
(vertex_count << 16) | type |
R300_VAP_VF_CNTL__INDEX_SIZE_32bit);
} else {
/* convert to bytes */
offset *= 2;
size = (vertex_count + 1) >> 1;
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_INDICES |
(vertex_count << 16) | type);
}
if (!rmesa->radeon.radeonScreen->kernel_mm) {
OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
(R300_VAP_PORT_IDX0 >> 2));
OUT_BATCH_RELOC(0, rmesa->ind_buf.bo, rmesa->ind_buf.bo_offset + offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
OUT_BATCH(size);
} else {
OUT_BATCH_PACKET3(R300_PACKET3_INDX_BUFFER, 2);
OUT_BATCH(R300_INDX_BUFFER_ONE_REG_WR | (0 << R300_INDX_BUFFER_SKIP_SHIFT) |
(R300_VAP_PORT_IDX0 >> 2));
OUT_BATCH(rmesa->ind_buf.bo_offset + offset);
OUT_BATCH(size);
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
rmesa->ind_buf.bo, RADEON_GEM_DOMAIN_GTT, 0, 0);
}
END_BATCH();
}
static void r300EmitAOS(r300ContextPtr rmesa, GLuint nr, GLuint offset)
{
BATCH_LOCALS(&rmesa->radeon);
uint32_t voffset;
int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2;
int i;
if (RADEON_DEBUG & RADEON_VERTS)
fprintf(stderr, "%s: nr=%d, ofs=0x%08x\n", __FUNCTION__, nr,
offset);
if (!rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH(sz+2+(nr * 2));
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
(rmesa->radeon.tcl.aos[i].stride << 8) |
(rmesa->radeon.tcl.aos[i + 1].components << 16) |
(rmesa->radeon.tcl.aos[i + 1].stride << 24));
voffset = rmesa->radeon.tcl.aos[i + 0].offset +
offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH_RELOC(voffset,
rmesa->radeon.tcl.aos[i].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
voffset = rmesa->radeon.tcl.aos[i + 1].offset +
offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH_RELOC(voffset,
rmesa->radeon.tcl.aos[i+1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
(rmesa->radeon.tcl.aos[nr - 1].stride << 8));
voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH_RELOC(voffset,
rmesa->radeon.tcl.aos[nr - 1].bo,
voffset,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
END_BATCH();
} else {
BEGIN_BATCH(sz+2+(nr * 2));
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, sz - 1);
OUT_BATCH(nr);
for (i = 0; i + 1 < nr; i += 2) {
OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
(rmesa->radeon.tcl.aos[i].stride << 8) |
(rmesa->radeon.tcl.aos[i + 1].components << 16) |
(rmesa->radeon.tcl.aos[i + 1].stride << 24));
voffset = rmesa->radeon.tcl.aos[i + 0].offset +
offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
OUT_BATCH(voffset);
voffset = rmesa->radeon.tcl.aos[i + 1].offset +
offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
OUT_BATCH(voffset);
}
if (nr & 1) {
OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
(rmesa->radeon.tcl.aos[nr - 1].stride << 8));
voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
OUT_BATCH(voffset);
}
for (i = 0; i + 1 < nr; i += 2) {
voffset = rmesa->radeon.tcl.aos[i + 0].offset +
offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
rmesa->radeon.tcl.aos[i+0].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
voffset = rmesa->radeon.tcl.aos[i + 1].offset +
offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
rmesa->radeon.tcl.aos[i+1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
if (nr & 1) {
voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
rmesa->radeon.tcl.aos[nr-1].bo,
RADEON_GEM_DOMAIN_GTT,
0, 0);
}
END_BATCH();
}
}
static void r300FireAOS(r300ContextPtr rmesa, int vertex_count, int type)
{
BATCH_LOCALS(&rmesa->radeon);
r300_emit_scissor(rmesa->radeon.glCtx);
BEGIN_BATCH(3);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (vertex_count << 16) | type);
END_BATCH();
}
void r300RunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
BATCH_LOCALS(&rmesa->radeon);
int type, num_verts;
type = r300PrimitiveType(rmesa, prim);
num_verts = r300NumVerts(rmesa, end - start, prim);
if (type < 0 || num_verts <= 0)
return;
if (rmesa->ind_buf.bo) {
GLuint first, incr, offset = 0;
if (!split_prim_inplace(prim & PRIM_MODE_MASK, &first, &incr) &&
num_verts > 65500) {
WARN_ONCE("Fixme: can't handle spliting prim %d\n", prim);
return;
}
r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, 0);
if (rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1);
OUT_BATCH(rmesa->radeon.tcl.aos[0].count);
END_BATCH();
}
r300_emit_scissor(rmesa->radeon.glCtx);
while (num_verts > 0) {
int nr;
int align;
nr = MIN2(num_verts, 65535);
nr -= (nr - first) % incr;
/* get alignment for IB correct */
if (nr != num_verts) {
do {
align = nr * (rmesa->ind_buf.is_32bit ? 4 : 2);
if (align % 4)
nr -= incr;
} while(align % 4);
if (nr <= 0) {
WARN_ONCE("did the impossible happen? we never aligned nr to dword\n");
return;
}
}
r300FireEB(rmesa, nr, type, offset);
num_verts -= nr;
offset += nr;
}
} else {
GLuint first, incr, offset = 0;
if (!split_prim_inplace(prim & PRIM_MODE_MASK, &first, &incr) &&
num_verts > 65535) {
WARN_ONCE("Fixme: can't handle spliting prim %d\n", prim);
return;
}
if (rmesa->radeon.radeonScreen->kernel_mm) {
BEGIN_BATCH_NO_AUTOSTATE(2);
OUT_BATCH_REGSEQ(R300_VAP_VF_MAX_VTX_INDX, 1);
OUT_BATCH(rmesa->radeon.tcl.aos[0].count);
END_BATCH();
}
r300_emit_scissor(rmesa->radeon.glCtx);
while (num_verts > 0) {
int nr;
nr = MIN2(num_verts, 65535);
nr -= (nr - first) % incr;
r300EmitAOS(rmesa, rmesa->radeon.tcl.aos_count, start + offset);
r300FireAOS(rmesa, nr, type);
num_verts -= nr;
offset += nr;
}
}
COMMIT_BATCH();
}
static const char *getFallbackString(r300ContextPtr rmesa, uint32_t bit)
{
static char common_fallback_str[32];
switch (bit) {
case R300_FALLBACK_VERTEX_PROGRAM :
return "vertex program";
case R300_FALLBACK_LINE_SMOOTH:
return "smooth lines";
case R300_FALLBACK_POINT_SMOOTH:
return "smooth points";
case R300_FALLBACK_POLYGON_SMOOTH:
return "smooth polygons";
case R300_FALLBACK_LINE_STIPPLE:
return "line stipple";
case R300_FALLBACK_POLYGON_STIPPLE:
return "polygon stipple";
case R300_FALLBACK_STENCIL_TWOSIDE:
return "two-sided stencil";
case R300_FALLBACK_RENDER_MODE:
return "render mode != GL_RENDER";
case R300_FALLBACK_FRAGMENT_PROGRAM:
return "fragment program";
case R300_FALLBACK_RADEON_COMMON:
snprintf(common_fallback_str, 32, "radeon common 0x%08x", rmesa->radeon.Fallback);
return common_fallback_str;
case R300_FALLBACK_AOS_LIMIT:
return "aos limit";
case R300_FALLBACK_INVALID_BUFFERS:
return "invalid buffers";
default:
return "unknown";
}
}
void r300SwitchFallback(struct gl_context *ctx, uint32_t bit, GLboolean mode)
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
uint32_t old_fallback = rmesa->fallback;
static uint32_t fallback_warn = 0;
if (mode) {
if ((fallback_warn & bit) == 0) {
if (RADEON_DEBUG & RADEON_FALLBACKS)
fprintf(stderr, "WARNING! Falling back to software for %s\n", getFallbackString(rmesa, bit));
fallback_warn |= bit;
}
rmesa->fallback |= bit;
/* update only if we change from no tcl fallbacks to some tcl fallbacks */
if (rmesa->options.hw_tcl_enabled) {
if (((old_fallback & R300_TCL_FALLBACK_MASK) == 0) &&
((bit & R300_TCL_FALLBACK_MASK) > 0)) {
R300_STATECHANGE(rmesa, vap_cntl_status);
rmesa->hw.vap_cntl_status.cmd[1] |= R300_VAP_TCL_BYPASS;
}
}
/* update only if we change from no raster fallbacks to some raster fallbacks */
if (((old_fallback & R300_RASTER_FALLBACK_MASK) == 0) &&
((bit & R300_RASTER_FALLBACK_MASK) > 0)) {
radeon_firevertices(&rmesa->radeon);
rmesa->radeon.swtcl.RenderIndex = ~0;
_swsetup_Wakeup( ctx );
}
} else {
rmesa->fallback &= ~bit;
/* update only if we have disabled all tcl fallbacks */
if (rmesa->options.hw_tcl_enabled) {
if ((old_fallback & R300_TCL_FALLBACK_MASK) == bit) {
R300_STATECHANGE(rmesa, vap_cntl_status);
rmesa->hw.vap_cntl_status.cmd[1] &= ~R300_VAP_TCL_BYPASS;
}
}
/* update only if we have disabled all raster fallbacks */
if ((old_fallback & R300_RASTER_FALLBACK_MASK) == bit) {
_swrast_flush( ctx );
tnl->Driver.Render.Start = r300RenderStart;
tnl->Driver.Render.Finish = r300RenderFinish;
tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive;
tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple;
tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
tnl->Driver.Render.CopyPV = _tnl_copy_pv;
tnl->Driver.Render.Interp = _tnl_interp;
_tnl_invalidate_vertex_state( ctx, ~0 );
_tnl_invalidate_vertices( ctx, ~0 );
}
}
}

70
src/mesa/drivers/dri/r300/r300_render.h
View file

@ -1,70 +0,0 @@
/*
* Copyright 2009 Maciej Cencora <m.cencora@gmail.com>
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __R300_RENDER_H__
#define __R300_RENDER_H__
#include "main/mtypes.h"
#define R300_FALLBACK_VERTEX_PROGRAM (1 << 0)
#define R300_TCL_FALLBACK_MASK 0x0000ffff
#define R300_FALLBACK_LINE_SMOOTH (1 << 16)
#define R300_FALLBACK_POINT_SMOOTH (1 << 17)
#define R300_FALLBACK_POLYGON_SMOOTH (1 << 18)
#define R300_FALLBACK_LINE_STIPPLE (1 << 19)
#define R300_FALLBACK_POLYGON_STIPPLE (1 << 20)
#define R300_FALLBACK_STENCIL_TWOSIDE (1 << 21)
#define R300_FALLBACK_RENDER_MODE (1 << 22)
#define R300_FALLBACK_FRAGMENT_PROGRAM (1 << 23)
#define R300_FALLBACK_RADEON_COMMON (1 << 29)
#define R300_FALLBACK_AOS_LIMIT (1 << 30)
#define R300_FALLBACK_INVALID_BUFFERS (1 << 31)
#define R300_RASTER_FALLBACK_MASK 0xffff0000
#define MASK_XYZW (R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W)
#define MASK_X R300_WRITE_ENA_X
#define MASK_Y R300_WRITE_ENA_Y
#define MASK_Z R300_WRITE_ENA_Z
#define MASK_W R300_WRITE_ENA_W
#if SWIZZLE_X != R300_INPUT_ROUTE_SELECT_X || \
SWIZZLE_Y != R300_INPUT_ROUTE_SELECT_Y || \
SWIZZLE_Z != R300_INPUT_ROUTE_SELECT_Z || \
SWIZZLE_W != R300_INPUT_ROUTE_SELECT_W || \
SWIZZLE_ZERO != R300_INPUT_ROUTE_SELECT_ZERO || \
SWIZZLE_ONE != R300_INPUT_ROUTE_SELECT_ONE
#error Cannot change these!
#endif
extern const struct tnl_pipeline_stage _r300_render_stage;
extern void r300SwitchFallback(struct gl_context *ctx, uint32_t bit, GLboolean mode);
extern void r300RunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim);
#endif

145
src/mesa/drivers/dri/r300/r300_shader.c
View file

@ -1,145 +0,0 @@
/*
* Copyright 2009 Maciej Cencora <m.cencora@gmail.com>
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "main/glheader.h"
#include "program/program.h"
#include "tnl/tnl.h"
#include "r300_context.h"
#include "r300_fragprog_common.h"
static void freeFragProgCache(struct gl_context *ctx, struct r300_fragment_program_cont *cache)
{
struct r300_fragment_program *tmp, *fp = cache->progs;
while (fp) {
tmp = fp->next;
rc_constants_destroy(&fp->code.constants);
free(fp);
fp = tmp;
}
}
static void freeVertProgCache(struct gl_context *ctx, struct r300_vertex_program_cont *cache)
{
struct r300_vertex_program *tmp, *vp = cache->progs;
while (vp) {
tmp = vp->next;
rc_constants_destroy(&vp->code.constants);
_mesa_reference_vertprog(ctx, &vp->Base, NULL);
free(vp);
vp = tmp;
}
}
static struct gl_program *r300NewProgram(struct gl_context * ctx, GLenum target,
GLuint id)
{
struct r300_vertex_program_cont *vp;
struct r300_fragment_program_cont *fp;
switch (target) {
case GL_VERTEX_STATE_PROGRAM_NV:
case GL_VERTEX_PROGRAM_ARB:
vp = CALLOC_STRUCT(r300_vertex_program_cont);
return _mesa_init_vertex_program(ctx, &vp->mesa_program, target, id);
case GL_FRAGMENT_PROGRAM_NV:
case GL_FRAGMENT_PROGRAM_ARB:
fp = CALLOC_STRUCT(r300_fragment_program_cont);
return _mesa_init_fragment_program(ctx, &fp->Base, target, id);
default:
_mesa_problem(ctx, "Bad target in r300NewProgram");
}
return NULL;
}
static void r300DeleteProgram(struct gl_context * ctx, struct gl_program *prog)
{
struct r300_vertex_program_cont *vp = (struct r300_vertex_program_cont *)prog;
struct r300_fragment_program_cont *fp = (struct r300_fragment_program_cont *)prog;
switch (prog->Target) {
case GL_VERTEX_PROGRAM_ARB:
freeVertProgCache(ctx, vp);
break;
case GL_FRAGMENT_PROGRAM_ARB:
freeFragProgCache(ctx, fp);
break;
}
_mesa_delete_program(ctx, prog);
}
static GLboolean
r300ProgramStringNotify(struct gl_context * ctx, GLenum target, struct gl_program *prog)
{
struct r300_vertex_program_cont *vp = (struct r300_vertex_program_cont *)prog;
struct r300_fragment_program_cont *fp = (struct r300_fragment_program_cont *)prog;
switch (target) {
case GL_VERTEX_PROGRAM_ARB:
freeVertProgCache(ctx, vp);
vp->progs = NULL;
break;
case GL_FRAGMENT_PROGRAM_ARB:
freeFragProgCache(ctx, fp);
fp->progs = NULL;
break;
}
/* need this for tcl fallbacks */
(void) _tnl_program_string(ctx, target, prog);
/* XXX check if program is legal, within limits */
return GL_TRUE;
}
static GLboolean
r300IsProgramNative(struct gl_context * ctx, GLenum target, struct gl_program *prog)
{
if (target == GL_FRAGMENT_PROGRAM_ARB) {
struct r300_fragment_program *fp = r300SelectAndTranslateFragmentShader(ctx);
return !fp->error;
} else {
struct r300_vertex_program *vp = r300SelectAndTranslateVertexShader(ctx);
return !vp->error;
}
}
void r300InitShaderFuncs(struct dd_function_table *functions)
{
functions->NewProgram = r300NewProgram;
functions->DeleteProgram = r300DeleteProgram;
functions->ProgramStringNotify = r300ProgramStringNotify;
functions->IsProgramNative = r300IsProgramNative;
}

2416
src/mesa/drivers/dri/r300/r300_state.c
View file

File diff suppressed because it is too large Load diff

62
src/mesa/drivers/dri/r300/r300_state.h
View file

@ -1,62 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Nicolai Haehnle <prefect_@gmx.net>
*/
#ifndef __R300_STATE_H__
#define __R300_STATE_H__
#include "r300_context.h"
#define R300_NEWPRIM( rmesa ) \
do { \
if ( rmesa->radeon.dma.flush ) \
rmesa->radeon.dma.flush( rmesa->radeon.glCtx ); \
} while (0)
#define R300_STATECHANGE(r300, atom) \
do { \
R300_NEWPRIM(r300); \
r300->hw.atom.dirty = GL_TRUE; \
r300->radeon.hw.is_dirty = GL_TRUE; \
} while(0)
void r300UpdateViewportOffset (struct gl_context * ctx);
void r300UpdateDrawBuffer (struct gl_context * ctx);
void r300UpdateShaders (r300ContextPtr rmesa);
void r300UpdateShaderStates (r300ContextPtr rmesa);
void r300InitState (r300ContextPtr r300);
void r300InitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
void r300VapCntl(r300ContextPtr rmesa, GLuint input_count, GLuint output_count, GLuint temp_count);
void r300SetupVAP(struct gl_context *ctx, GLuint InputsRead, GLuint OutputsWritten);
#endif /* __R300_STATE_H__ */

683
src/mesa/drivers/dri/r300/r300_swtcl.c
View file

@ -1,683 +0,0 @@
/**************************************************************************
Copyright (C) 2007 Dave Airlie
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Dave Airlie <airlied@linux.ie>
* Maciej Cencora <m.cencora@gmail.com>
*/
#include "tnl/tnl.h"
#include "tnl/t_pipeline.h"
#include "r300_state.h"
#include "r300_swtcl.h"
#include "r300_emit.h"
#include "r300_tex.h"
#include "r300_render.h"
#include "main/simple_list.h"
#define EMIT_ATTR( ATTR, STYLE ) \
do { \
rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
rmesa->radeon.swtcl.vertex_attr_count++; \
} while (0)
#define EMIT_PAD( N ) \
do { \
rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
rmesa->radeon.swtcl.vertex_attr_count++; \
} while (0)
#define ADD_ATTR(_attr, _format, _dst_loc, _swizzle, _write_mask, _normalize) \
do { \
attrs[num_attrs].element = (_attr); \
attrs[num_attrs].data_type = (_format); \
attrs[num_attrs].dst_loc = (_dst_loc); \
attrs[num_attrs].swizzle = (_swizzle); \
attrs[num_attrs].write_mask = (_write_mask); \
attrs[num_attrs]._signed = 0; \
attrs[num_attrs].normalize = (_normalize); \
++num_attrs; \
} while (0)
void r300ChooseSwtclVertexFormat(struct gl_context *ctx, GLuint *_InputsRead, GLuint *_OutputsWritten)
{
r300ContextPtr rmesa = R300_CONTEXT( ctx );
TNLcontext *tnl = TNL_CONTEXT(ctx);
struct vertex_buffer *VB = &tnl->vb;
int first_free_tex = 0;
GLuint InputsRead = 0;
GLuint OutputsWritten = 0;
int num_attrs = 0;
GLuint fp_reads = rmesa->selected_fp->InputsRead;
struct vertex_attribute *attrs = rmesa->vbuf.attribs;
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__);
rmesa->swtcl.coloroffset = rmesa->swtcl.specoffset = 0;
rmesa->radeon.swtcl.vertex_attr_count = 0;
if (RADEON_DEBUG & RADEON_VERTS)
fprintf(stderr, "%s\n", __func__);
/* We always want non Ndc coords format */
VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
/* Always write position vector */
InputsRead |= 1 << VERT_ATTRIB_POS;
OutputsWritten |= 1 << VERT_RESULT_HPOS;
EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F );
ADD_ATTR(VERT_ATTRIB_POS, R300_DATA_TYPE_FLOAT_4, SWTCL_OVM_POS, SWIZZLE_XYZW, MASK_XYZW, 0);
rmesa->swtcl.coloroffset = 4;
if (fp_reads & FRAG_BIT_COL0) {
InputsRead |= 1 << VERT_ATTRIB_COLOR0;
OutputsWritten |= 1 << VERT_RESULT_COL0;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_COLOR0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR0, SWIZZLE_XYZW, MASK_XYZW, 1);
#endif
}
if (fp_reads & FRAG_BIT_COL1) {
GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
InputsRead |= 1 << VERT_ATTRIB_COLOR1;
OutputsWritten |= 1 << VERT_RESULT_COL1;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_COLOR1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR1, swiz, MASK_XYZW, 1);
#endif
rmesa->swtcl.specoffset = rmesa->swtcl.coloroffset + 1;
}
if (ctx->Light.Enabled && ctx->Light.Model.TwoSide) {
VB->AttribPtr[VERT_ATTRIB_GENERIC0] = VB->BackfaceColorPtr;
OutputsWritten |= 1 << VERT_RESULT_BFC0;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_GENERIC0, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_GENERIC0, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR2, SWIZZLE_XYZW, MASK_XYZW, 1);
#endif
if (fp_reads & FRAG_BIT_COL1) {
VB->AttribPtr[VERT_ATTRIB_GENERIC1] = VB->BackfaceSecondaryColorPtr;
GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
OutputsWritten |= 1 << VERT_RESULT_BFC1;
#if MESA_LITTLE_ENDIAN
EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_RGBA );
ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1);
#else
EMIT_ATTR( _TNL_ATTRIB_GENERIC1, EMIT_4UB_4F_ABGR );
ADD_ATTR(VERT_ATTRIB_GENERIC1, R300_DATA_TYPE_BYTE, SWTCL_OVM_COLOR3, swiz, MASK_XYZW, 1);
#endif
}
}
if (RENDERINPUTS_TEST(tnl->render_inputs_bitset, _TNL_ATTRIB_POINTSIZE )) {
GLuint swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ZERO);
InputsRead |= 1 << VERT_ATTRIB_POINT_SIZE;
OutputsWritten |= 1 << VERT_RESULT_PSIZ;
EMIT_ATTR( _TNL_ATTRIB_POINTSIZE, EMIT_1F );
ADD_ATTR(VERT_ATTRIB_POINT_SIZE, R300_DATA_TYPE_FLOAT_1, SWTCL_OVM_POINT_SIZE, swiz, MASK_X, 0);
}
if (rmesa->selected_fp->wpos_attr != FRAG_ATTRIB_MAX) {
int tex_id = rmesa->selected_fp->wpos_attr - FRAG_ATTRIB_TEX0;
VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_POS];
VB->AttribPtr[_TNL_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_POS];
RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id);
}
if (rmesa->selected_fp->fog_attr != FRAG_ATTRIB_MAX) {
int tex_id = rmesa->selected_fp->fog_attr - FRAG_ATTRIB_TEX0;
VB->AttribPtr[VERT_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG];
VB->AttribPtr[_TNL_ATTRIB_TEX0 + tex_id] = VB->AttribPtr[VERT_ATTRIB_FOG];
RENDERINPUTS_SET(tnl->render_inputs_bitset, _TNL_ATTRIB_TEX0 + tex_id);
}
/**
* Sending only one texcoord component may lead to lock up,
* so for all textures always output 4 texcoord components to RS.
*/
{
int i;
GLuint swiz, format, hw_format;
for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
if (fp_reads & FRAG_BIT_TEX(i)) {
switch (VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size) {
case 1:
format = EMIT_1F;
hw_format = R300_DATA_TYPE_FLOAT_1;
swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_ZERO, SWIZZLE_ZERO, SWIZZLE_ONE);
break;
case 2:
format = EMIT_2F;
hw_format = R300_DATA_TYPE_FLOAT_2;
swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ONE);
break;
case 3:
format = EMIT_3F;
hw_format = R300_DATA_TYPE_FLOAT_3;
swiz = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_ONE);
break;
case 4:
format = EMIT_4F;
hw_format = R300_DATA_TYPE_FLOAT_4;
swiz = SWIZZLE_XYZW;
break;
default:
continue;
}
InputsRead |= 1 << (VERT_ATTRIB_TEX0 + i);
OutputsWritten |= 1 << (VERT_RESULT_TEX0 + i);
EMIT_ATTR(_TNL_ATTRIB_TEX(i), format);
ADD_ATTR(VERT_ATTRIB_TEX0 + i, hw_format, SWTCL_OVM_TEX(first_free_tex), swiz, MASK_XYZW, 0);
++first_free_tex;
}
}
}
if (first_free_tex >= ctx->Const.MaxTextureUnits) {
fprintf(stderr, "\tout of free texcoords to write fog coordinate\n");
exit(-1);
}
R300_NEWPRIM(rmesa);
rmesa->vbuf.num_attribs = num_attrs;
*_InputsRead = InputsRead;
*_OutputsWritten = OutputsWritten;
RENDERINPUTS_COPY(rmesa->render_inputs_bitset, tnl->render_inputs_bitset);
}
static void r300PrepareVertices(struct gl_context *ctx)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
GLuint InputsRead, OutputsWritten;
radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
r300ChooseSwtclVertexFormat(ctx, &InputsRead, &OutputsWritten);
r300SetupVAP(ctx, InputsRead, OutputsWritten);
rmesa->radeon.swtcl.vertex_size =
_tnl_install_attrs( ctx,
rmesa->radeon.swtcl.vertex_attrs,
rmesa->radeon.swtcl.vertex_attr_count,
NULL, 0 );
rmesa->radeon.swtcl.vertex_size /= 4;
}
static void r300_predict_emit_size( r300ContextPtr rmesa )
{
if (!rmesa->radeon.swtcl.emit_prediction) {
const int vertex_size = 7;
const int prim_size = 3;
const int cache_flush_size = 4;
const int pre_emit_state = 4;
const int scissor_size = 3;
const int state_size = radeonCountStateEmitSize(&rmesa->radeon);
if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
state_size + pre_emit_state + scissor_size
+ vertex_size + prim_size + cache_flush_size * 2,
__FUNCTION__))
rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize(&rmesa->radeon);
else
rmesa->radeon.swtcl.emit_prediction = state_size;
rmesa->radeon.swtcl.emit_prediction += rmesa->radeon.cmdbuf.cs->cdw
+ vertex_size + scissor_size + prim_size + cache_flush_size * 2 + pre_emit_state;
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
"%s, size %d\n",
__func__, rmesa->radeon.cmdbuf.cs->cdw
+ vertex_size + scissor_size + prim_size + cache_flush_size * 2 + pre_emit_state);
}
}
static GLuint reduced_prim[] = {
GL_POINTS,
GL_LINES,
GL_LINES,
GL_LINES,
GL_TRIANGLES,
GL_TRIANGLES,
GL_TRIANGLES,
GL_TRIANGLES,
GL_TRIANGLES,
GL_TRIANGLES,
};
static void r300RasterPrimitive( struct gl_context *ctx, GLuint prim );
/***********************************************************************
* Emit primitives as inline vertices *
***********************************************************************/
#define HAVE_POINTS 1
#define HAVE_LINES 1
#define HAVE_LINE_STRIPS 1
#define HAVE_TRIANGLES 1
#define HAVE_TRI_STRIPS 1
#define HAVE_TRI_STRIP_1 0
#define HAVE_TRI_FANS 1
#define HAVE_QUADS 0
#define HAVE_QUAD_STRIPS 0
#define HAVE_POLYGONS 1
#define HAVE_ELTS 1
static void* r300_alloc_verts(r300ContextPtr rmesa, GLuint n, GLuint size)
{
void *rv;
do {
r300_predict_emit_size( rmesa );
rv = rcommonAllocDmaLowVerts( &rmesa->radeon, n, size * 4 );
} while (!rv);
return rv;
}
#undef LOCAL_VARS
#undef ALLOC_VERTS
#define CTX_ARG r300ContextPtr rmesa
#define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
#define ALLOC_VERTS( n, size ) r300_alloc_verts(rmesa, n, size);
#define LOCAL_VARS \
r300ContextPtr rmesa = R300_CONTEXT(ctx); \
const char *r300verts = (char *)rmesa->radeon.swtcl.verts;
#define VERT(x) (r300Vertex *)(r300verts + ((x) * vertsize * sizeof(int)))
#define VERTEX r300Vertex
#undef TAG
#define TAG(x) r300_##x
#include "tnl_dd/t_dd_triemit.h"
/***********************************************************************
* Macros for t_dd_tritmp.h to draw basic primitives *
***********************************************************************/
#define QUAD( a, b, c, d ) r300_quad( rmesa, a, b, c, d )
#define TRI( a, b, c ) r300_triangle( rmesa, a, b, c )
#define LINE( a, b ) r300_line( rmesa, a, b )
#define POINT( a ) r300_point( rmesa, a )
/***********************************************************************
* Build render functions from dd templates *
***********************************************************************/
#define R300_UNFILLED_BIT 0x01
#define R300_MAX_TRIFUNC 0x02
static struct {
tnl_points_func points;
tnl_line_func line;
tnl_triangle_func triangle;
tnl_quad_func quad;
} rast_tab[R300_MAX_TRIFUNC];
#define DO_FALLBACK 0
#define DO_UNFILLED (IND & R300_UNFILLED_BIT)
#define DO_TWOSIDE 0
#define DO_FLAT 0
#define DO_OFFSET 0
#define DO_TRI 1
#define DO_QUAD 1
#define DO_LINE 1
#define DO_POINTS 1
#define DO_FULL_QUAD 1
#define HAVE_SPEC 1
#define HAVE_BACK_COLORS 0
#define HAVE_HW_FLATSHADE 1
#define TAB rast_tab
#define DEPTH_SCALE 1.0
#define UNFILLED_TRI unfilled_tri
#define UNFILLED_QUAD unfilled_quad
#define VERT_X(_v) _v->v.x
#define VERT_Y(_v) _v->v.y
#define VERT_Z(_v) _v->v.z
#define AREA_IS_CCW( a ) (a < 0)
#define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + (e*rmesa->radeon.swtcl.vertex_size*sizeof(int)))
#define VERT_SET_RGBA( v, c ) \
do { \
r300_color_t *color = (r300_color_t *)&((v)->ui[coloroffset]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
} while (0)
#define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
#define VERT_SET_SPEC( v0, c ) \
do { \
if (specoffset) { \
UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.red, (c)[0]); \
UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.green, (c)[1]); \
UNCLAMPED_FLOAT_TO_UBYTE(v0->v.specular.blue, (c)[2]); \
} \
} while (0)
#define VERT_COPY_SPEC( v0, v1 ) \
do { \
if (specoffset) { \
v0->v.specular.red = v1->v.specular.red; \
v0->v.specular.green = v1->v.specular.green; \
v0->v.specular.blue = v1->v.specular.blue; \
} \
} while (0)
#define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
#define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
#define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
#define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
#undef LOCAL_VARS
#undef TAG
#undef INIT
#define LOCAL_VARS(n) \
r300ContextPtr rmesa = R300_CONTEXT(ctx); \
GLuint color[n] = { 0, }, spec[n] = { 0, }; \
GLuint coloroffset = rmesa->swtcl.coloroffset; \
GLuint specoffset = rmesa->swtcl.specoffset; \
(void) color; (void) spec; (void) coloroffset; (void) specoffset;
/***********************************************************************
* Helpers for rendering unfilled primitives *
***********************************************************************/
#define RASTERIZE(x) r300RasterPrimitive( ctx, reduced_prim[x] )
#define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
#undef TAG
#define TAG(x) x
#include "tnl_dd/t_dd_unfilled.h"
#undef IND
/***********************************************************************
* Generate GL render functions *
***********************************************************************/
#define IND (0)
#define TAG(x) x
#include "tnl_dd/t_dd_tritmp.h"
#define IND (R300_UNFILLED_BIT)
#define TAG(x) x##_unfilled
#include "tnl_dd/t_dd_tritmp.h"
static void init_rast_tab( void )
{
init();
init_unfilled();
}
/**********************************************************************/
/* Render unclipped begin/end objects */
/**********************************************************************/
#define RENDER_POINTS( start, count ) \
for ( ; start < count ; start++) \
r300_point( rmesa, VERT(start) )
#define RENDER_LINE( v0, v1 ) \
r300_line( rmesa, VERT(v0), VERT(v1) )
#define RENDER_TRI( v0, v1, v2 ) \
r300_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
#define RENDER_QUAD( v0, v1, v2, v3 ) \
r300_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
#define INIT(x) do { \
r300RenderPrimitive( ctx, x ); \
} while (0)
#undef LOCAL_VARS
#define LOCAL_VARS \
r300ContextPtr rmesa = R300_CONTEXT(ctx); \
const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
const char *r300verts = (char *)rmesa->radeon.swtcl.verts; \
const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
const GLboolean stipple = ctx->Line.StippleFlag; \
(void) elt; (void) stipple;
#define RESET_STIPPLE //if ( stipple ) r200ResetLineStipple( ctx );
#define RESET_OCCLUSION
#define PRESERVE_VB_DEFS
#define ELT(x) (x)
#define TAG(x) r300_##x##_verts
#include "tnl/t_vb_rendertmp.h"
#undef ELT
#undef TAG
#define TAG(x) r300_##x##_elts
#define ELT(x) elt[x]
#include "tnl/t_vb_rendertmp.h"
/**********************************************************************/
/* Choose render functions */
/**********************************************************************/
static void r300ChooseRenderState( struct gl_context *ctx )
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
GLuint index = 0;
GLuint flags = ctx->_TriangleCaps;
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__);
if (flags & DD_TRI_UNFILLED) index |= R300_UNFILLED_BIT;
if (index != rmesa->radeon.swtcl.RenderIndex) {
tnl->Driver.Render.Points = rast_tab[index].points;
tnl->Driver.Render.Line = rast_tab[index].line;
tnl->Driver.Render.ClippedLine = rast_tab[index].line;
tnl->Driver.Render.Triangle = rast_tab[index].triangle;
tnl->Driver.Render.Quad = rast_tab[index].quad;
if (index == 0) {
tnl->Driver.Render.PrimTabVerts = r300_render_tab_verts;
tnl->Driver.Render.PrimTabElts = r300_render_tab_elts;
tnl->Driver.Render.ClippedPolygon = r300_fast_clipped_poly;
} else {
tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
}
rmesa->radeon.swtcl.RenderIndex = index;
}
}
void r300RenderStart(struct gl_context *ctx)
{
radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s\n", __func__);
r300ContextPtr rmesa = R300_CONTEXT( ctx );
r300ChooseRenderState(ctx);
r300UpdateShaders(rmesa);
r300PrepareVertices(ctx);
r300ValidateBuffers(ctx);
r300UpdateShaderStates(rmesa);
/* investigate if we can put back flush optimisation if needed */
if (rmesa->radeon.dma.flush != NULL) {
rmesa->radeon.dma.flush(ctx);
}
}
void r300RenderFinish(struct gl_context *ctx)
{
}
static void r300RasterPrimitive( struct gl_context *ctx, GLuint hwprim )
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
R300_NEWPRIM( rmesa );
rmesa->radeon.swtcl.hw_primitive = hwprim;
}
}
void r300RenderPrimitive(struct gl_context *ctx, GLenum prim)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
rmesa->radeon.swtcl.render_primitive = prim;
radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
if ((prim == GL_TRIANGLES) && (ctx->_TriangleCaps & DD_TRI_UNFILLED))
return;
r300RasterPrimitive( ctx, reduced_prim[prim] );
}
void r300ResetLineStipple(struct gl_context *ctx)
{
if (RADEON_DEBUG & RADEON_VERTS)
fprintf(stderr, "%s\n", __func__);
}
void r300InitSwtcl(struct gl_context *ctx)
{
TNLcontext *tnl = TNL_CONTEXT(ctx);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
static int firsttime = 1;
radeon_print(RADEON_SWRENDER, RADEON_NORMAL, "%s\n", __func__);
if (firsttime) {
init_rast_tab();
firsttime = 0;
}
rmesa->radeon.swtcl.emit_prediction = 0;
tnl->Driver.Render.Start = r300RenderStart;
tnl->Driver.Render.Finish = r300RenderFinish;
tnl->Driver.Render.PrimitiveNotify = r300RenderPrimitive;
tnl->Driver.Render.ResetLineStipple = r300ResetLineStipple;
tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
tnl->Driver.Render.CopyPV = _tnl_copy_pv;
tnl->Driver.Render.Interp = _tnl_interp;
/* FIXME: what are these numbers? */
_tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
48 * sizeof(GLfloat) );
rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
rmesa->radeon.swtcl.RenderIndex = ~0;
rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
rmesa->radeon.swtcl.hw_primitive = 0;
_tnl_invalidate_vertex_state( ctx, ~0 );
_tnl_invalidate_vertices( ctx, ~0 );
_tnl_need_projected_coords( ctx, GL_FALSE );
}
void r300DestroySwtcl(struct gl_context *ctx)
{
}
static void r300EmitVertexAOS(r300ContextPtr rmesa, GLuint vertex_size, struct radeon_bo *bo, GLuint offset)
{
BATCH_LOCALS(&rmesa->radeon);
radeon_print(RADEON_SWRENDER, RADEON_TRACE,
"%s: vertex_size %d, offset 0x%x \n",
__FUNCTION__, vertex_size, offset);
BEGIN_BATCH(7);
OUT_BATCH_PACKET3(R300_PACKET3_3D_LOAD_VBPNTR, 2);
OUT_BATCH(1);
OUT_BATCH(vertex_size | (vertex_size << 8));
OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
}
static void r300EmitVbufPrim(r300ContextPtr rmesa, GLuint primitive, GLuint vertex_nr)
{
BATCH_LOCALS(&rmesa->radeon);
int type, num_verts;
if (RADEON_DEBUG & RADEON_VERTS)
fprintf(stderr, "%s\n", __func__);
type = r300PrimitiveType(rmesa, primitive);
num_verts = r300NumVerts(rmesa, vertex_nr, primitive);
BEGIN_BATCH(3);
OUT_BATCH_PACKET3(R300_PACKET3_3D_DRAW_VBUF_2, 0);
OUT_BATCH(R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST | (num_verts << 16) | type);
END_BATCH();
}
void r300_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
{
radeon_print(RADEON_SWRENDER, RADEON_TRACE, "%s\n", __func__);
r300ContextPtr rmesa = R300_CONTEXT(ctx);
r300EmitCacheFlush(rmesa);
radeonEmitState(&rmesa->radeon);
r300_emit_scissor(ctx);
r300EmitVertexAOS(rmesa,
rmesa->radeon.swtcl.vertex_size,
rmesa->radeon.swtcl.bo,
current_offset);
r300EmitVbufPrim(rmesa,
rmesa->radeon.swtcl.hw_primitive,
rmesa->radeon.swtcl.numverts);
r300EmitCacheFlush(rmesa);
if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
WARN_ONCE("Rendering was %d commands larger than predicted size."
" We might overflow command buffer.\n",
rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
rmesa->radeon.swtcl.emit_prediction = 0;
COMMIT_BATCH();
}

65
src/mesa/drivers/dri/r300/r300_swtcl.h
View file

@ -1,65 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com> - original r200 code
* Dave Airlie <airlied@linux.ie>
*/
#ifndef __R300_SWTCL_H__
#define __R300_SWTCL_H__
#include "main/mtypes.h"
#include "swrast/swrast.h"
#include "r300_context.h"
/*
* Here are definitions of OVM locations of vertex attributes for non TCL hw
*/
#define SWTCL_OVM_POS 0
#define SWTCL_OVM_COLOR0 2
#define SWTCL_OVM_COLOR1 3
#define SWTCL_OVM_COLOR2 4
#define SWTCL_OVM_COLOR3 5
#define SWTCL_OVM_TEX(n) ((n) + 6)
#define SWTCL_OVM_POINT_SIZE 15
extern void r300ChooseSwtclVertexFormat(struct gl_context *ctx, GLuint *InputsRead, GLuint *OutputsWritten);
extern void r300InitSwtcl( struct gl_context *ctx );
extern void r300DestroySwtcl( struct gl_context *ctx );
extern void r300RenderStart(struct gl_context *ctx);
extern void r300RenderFinish(struct gl_context *ctx);
extern void r300RenderPrimitive(struct gl_context *ctx, GLenum prim);
extern void r300ResetLineStipple(struct gl_context *ctx);
extern void r300_swtcl_flush(struct gl_context *ctx, uint32_t current_offset);
#endif

369
src/mesa/drivers/dri/r300/r300_tex.c
View file

@ -1,369 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/**
* \file
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
#include "main/glheader.h"
#include "main/imports.h"
#include "main/colormac.h"
#include "main/context.h"
#include "main/enums.h"
#include "main/image.h"
#include "main/mfeatures.h"
#include "main/mipmap.h"
#include "main/simple_list.h"
#include "main/texobj.h"
#include "texmem.h"
#include "r300_context.h"
#include "radeon_mipmap_tree.h"
#include "r300_tex.h"
static unsigned int translate_wrap_mode(GLenum wrapmode)
{
switch(wrapmode) {
case GL_REPEAT: return R300_TX_REPEAT;
case GL_CLAMP: return R300_TX_CLAMP;
case GL_CLAMP_TO_EDGE: return R300_TX_CLAMP_TO_EDGE;
case GL_CLAMP_TO_BORDER: return R300_TX_CLAMP_TO_BORDER;
case GL_MIRRORED_REPEAT: return R300_TX_REPEAT | R300_TX_MIRRORED;
case GL_MIRROR_CLAMP_EXT: return R300_TX_CLAMP | R300_TX_MIRRORED;
case GL_MIRROR_CLAMP_TO_EDGE_EXT: return R300_TX_CLAMP_TO_EDGE | R300_TX_MIRRORED;
case GL_MIRROR_CLAMP_TO_BORDER_EXT: return R300_TX_CLAMP_TO_BORDER | R300_TX_MIRRORED;
default:
_mesa_problem(NULL, "bad wrap mode in %s", __FUNCTION__);
return 0;
}
}
/**
* Update the cached hardware registers based on the current texture wrap modes.
*
* \param t Texture object whose wrap modes are to be set
*/
static void r300UpdateTexWrap(radeonTexObjPtr t)
{
struct gl_texture_object *tObj = &t->base;
t->pp_txfilter &=
~(R300_TX_WRAP_S_MASK | R300_TX_WRAP_T_MASK | R300_TX_WRAP_R_MASK);
t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapS) << R300_TX_WRAP_S_SHIFT;
if (tObj->Target != GL_TEXTURE_1D) {
t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapT) << R300_TX_WRAP_T_SHIFT;
if (tObj->Target == GL_TEXTURE_3D)
t->pp_txfilter |= translate_wrap_mode(tObj->Sampler.WrapR) << R300_TX_WRAP_R_SHIFT;
}
}
static GLuint aniso_filter(GLfloat anisotropy)
{
if (anisotropy >= 16.0) {
return R300_TX_MAX_ANISO_16_TO_1;
} else if (anisotropy >= 8.0) {
return R300_TX_MAX_ANISO_8_TO_1;
} else if (anisotropy >= 4.0) {
return R300_TX_MAX_ANISO_4_TO_1;
} else if (anisotropy >= 2.0) {
return R300_TX_MAX_ANISO_2_TO_1;
} else {
return R300_TX_MAX_ANISO_1_TO_1;
}
}
/**
* Set the texture magnification and minification modes.
*
* \param t Texture whose filter modes are to be set
* \param minf Texture minification mode
* \param magf Texture magnification mode
* \param anisotropy Maximum anisotropy level
*/
static void r300SetTexFilter(radeonTexObjPtr t, GLenum minf, GLenum magf, GLfloat anisotropy)
{
/* Force revalidation to account for switches from/to mipmapping. */
t->validated = GL_FALSE;
t->pp_txfilter &= ~(R300_TX_MIN_FILTER_MASK | R300_TX_MIN_FILTER_MIP_MASK | R300_TX_MAG_FILTER_MASK | R300_TX_MAX_ANISO_MASK);
t->pp_txfilter_1 &= ~R300_EDGE_ANISO_EDGE_ONLY;
/* Note that EXT_texture_filter_anisotropic is extremely vague about
* how anisotropic filtering interacts with the "normal" filter modes.
* When anisotropic filtering is enabled, we override min and mag
* filter settings completely. This includes driconf's settings.
*/
if (anisotropy >= 2.0 && (minf != GL_NEAREST) && (magf != GL_NEAREST)) {
t->pp_txfilter |= R300_TX_MAG_FILTER_ANISO
| R300_TX_MIN_FILTER_ANISO
| R300_TX_MIN_FILTER_MIP_LINEAR
| aniso_filter(anisotropy);
if (RADEON_DEBUG & RADEON_TEXTURE)
fprintf(stderr, "Using maximum anisotropy of %f\n", anisotropy);
return;
}
switch (minf) {
case GL_NEAREST:
t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST;
break;
case GL_LINEAR:
t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR;
break;
case GL_NEAREST_MIPMAP_NEAREST:
t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_NEAREST;
break;
case GL_NEAREST_MIPMAP_LINEAR:
t->pp_txfilter |= R300_TX_MIN_FILTER_NEAREST|R300_TX_MIN_FILTER_MIP_LINEAR;
break;
case GL_LINEAR_MIPMAP_NEAREST:
t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_NEAREST;
break;
case GL_LINEAR_MIPMAP_LINEAR:
t->pp_txfilter |= R300_TX_MIN_FILTER_LINEAR|R300_TX_MIN_FILTER_MIP_LINEAR;
break;
}
/* Note we don't have 3D mipmaps so only use the mag filter setting
* to set the 3D texture filter mode.
*/
switch (magf) {
case GL_NEAREST:
t->pp_txfilter |= R300_TX_MAG_FILTER_NEAREST;
break;
case GL_LINEAR:
t->pp_txfilter |= R300_TX_MAG_FILTER_LINEAR;
break;
}
}
static void r300SetTexBorderColor(radeonTexObjPtr t, const GLfloat color[4])
{
GLubyte c[4];
CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
t->pp_border_color = PACK_COLOR_8888(c[3], c[0], c[1], c[2]);
}
/**
* Changes variables and flags for a state update, which will happen at the
* next UpdateTextureState
*/
static void r300TexParameter(struct gl_context * ctx, GLenum target,
struct gl_texture_object *texObj,
GLenum pname, const GLfloat * params)
{
radeonTexObj* t = radeon_tex_obj(texObj);
GLenum texBaseFormat;
if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) {
fprintf(stderr, "%s( %s )\n", __FUNCTION__,
_mesa_lookup_enum_by_nr(pname));
}
switch (pname) {
case GL_TEXTURE_MIN_FILTER:
case GL_TEXTURE_MAG_FILTER:
case GL_TEXTURE_MAX_ANISOTROPY_EXT:
r300SetTexFilter(t, texObj->Sampler.MinFilter, texObj->Sampler.MagFilter, texObj->Sampler.MaxAnisotropy);
break;
case GL_TEXTURE_WRAP_S:
case GL_TEXTURE_WRAP_T:
case GL_TEXTURE_WRAP_R:
r300UpdateTexWrap(t);
break;
case GL_TEXTURE_BORDER_COLOR:
r300SetTexBorderColor(t, texObj->Sampler.BorderColor.f);
break;
case GL_TEXTURE_BASE_LEVEL:
case GL_TEXTURE_MAX_LEVEL:
case GL_TEXTURE_MIN_LOD:
case GL_TEXTURE_MAX_LOD:
t->validated = GL_FALSE;
break;
case GL_DEPTH_TEXTURE_MODE:
if (!texObj->Image[0][texObj->BaseLevel])
return;
texBaseFormat = texObj->Image[0][texObj->BaseLevel]->_BaseFormat;
if (texBaseFormat == GL_DEPTH_COMPONENT ||
texBaseFormat == GL_DEPTH_STENCIL) {
r300SetDepthTexMode(texObj);
break;
} else {
/* If the texture isn't a depth texture, changing this
* state won't cause any changes to the hardware.
* Don't force a flush of texture state.
*/
return;
}
default:
return;
}
}
static void r300DeleteTexture(struct gl_context * ctx, struct gl_texture_object *texObj)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
radeonTexObj* t = radeon_tex_obj(texObj);
if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) {
fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__,
(void *)texObj,
_mesa_lookup_enum_by_nr(texObj->Target));
}
if (rmesa) {
int i;
struct radeon_bo *bo;
bo = !t->mt ? t->bo : t->mt->bo;
if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->radeon.cmdbuf.cs)) {
radeon_firevertices(&rmesa->radeon);
}
for(i = 0; i < R300_MAX_TEXTURE_UNITS; ++i)
if (rmesa->hw.textures[i] == t)
rmesa->hw.textures[i] = 0;
}
if (t->bo) {
radeon_bo_unref(t->bo);
t->bo = NULL;
}
radeon_miptree_unreference(&t->mt);
_mesa_delete_texture_object(ctx, texObj);
}
/**
* Allocate a new texture object.
* Called via ctx->Driver.NewTextureObject.
* Note: this function will be called during context creation to
* allocate the default texture objects.
* Fixup MaxAnisotropy according to user preference.
*/
static struct gl_texture_object *r300NewTextureObject(struct gl_context * ctx,
GLuint name,
GLenum target)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
if (RADEON_DEBUG & (RADEON_STATE | RADEON_TEXTURE)) {
fprintf(stderr, "%s( %p (target = %s) )\n", __FUNCTION__,
t, _mesa_lookup_enum_by_nr(target));
}
_mesa_initialize_texture_object(&t->base, name, target);
t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
/* Initialize hardware state */
r300UpdateTexWrap(t);
r300SetTexFilter(t, t->base.Sampler.MinFilter,
t->base.Sampler.MagFilter,
t->base.Sampler.MaxAnisotropy);
r300SetTexBorderColor(t, t->base.Sampler.BorderColor.f);
return &t->base;
}
unsigned r300IsFormatRenderable(gl_format mesa_format)
{
switch (mesa_format)
{
case MESA_FORMAT_RGB565:
case MESA_FORMAT_RGBA5551:
case MESA_FORMAT_RGBA8888:
case MESA_FORMAT_RGB565_REV:
case MESA_FORMAT_RGBA8888_REV:
case MESA_FORMAT_ARGB4444:
case MESA_FORMAT_ARGB1555:
case MESA_FORMAT_XRGB8888:
case MESA_FORMAT_ARGB8888:
case MESA_FORMAT_ARGB4444_REV:
case MESA_FORMAT_ARGB1555_REV:
case MESA_FORMAT_XRGB8888_REV:
case MESA_FORMAT_ARGB8888_REV:
case MESA_FORMAT_SRGBA8:
case MESA_FORMAT_SARGB8:
case MESA_FORMAT_SL8:
case MESA_FORMAT_A8:
case MESA_FORMAT_L8:
case MESA_FORMAT_I8:
case MESA_FORMAT_Z16:
return 1;
default:
return 0;
}
}
unsigned r500IsFormatRenderable(gl_format mesa_format)
{
if (mesa_format == MESA_FORMAT_S8_Z24) {
return 1;
} else {
return r300IsFormatRenderable(mesa_format);
}
}
void r300InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions)
{
/* Note: we only plug in the functions we implement in the driver
* since _mesa_init_driver_functions() was already called.
*/
radeon_init_common_texture_funcs(radeon, functions);
functions->NewTextureObject = r300NewTextureObject;
functions->DeleteTexture = r300DeleteTexture;
functions->IsTextureResident = driIsTextureResident;
functions->TexParameter = r300TexParameter;
#if FEATURE_OES_EGL_image
functions->EGLImageTargetTexture2D = radeon_image_target_texture_2d;
#endif
}

59
src/mesa/drivers/dri/r300/r300_tex.h
View file

@ -1,59 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*/
#ifndef __r300_TEX_H__
#define __r300_TEX_H__
extern void r300SetDepthTexMode(struct gl_texture_object *tObj);
extern void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target,
__DRIdrawable *dPriv);
extern void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
GLint format, __DRIdrawable *dPriv);
extern void r300SetTexOffset(__DRIcontext *pDRICtx, GLint texname,
unsigned long long offset, GLint depth,
GLuint pitch);
extern GLboolean r300ValidateBuffers(struct gl_context * ctx);
extern void r300InitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions);
int32_t r300TranslateTexFormat(gl_format mesaFormat);
unsigned r300IsFormatRenderable(gl_format mesaFormat);
unsigned r500IsFormatRenderable(gl_format mesaFormat);
#endif /* __r300_TEX_H__ */

528
src/mesa/drivers/dri/r300/r300_texstate.c
View file

@ -1,528 +0,0 @@
/*
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*
* \todo Enable R300 texture tiling code?
*/
#include "main/glheader.h"
#include "main/imports.h"
#include "main/context.h"
#include "main/macros.h"
#include "main/teximage.h"
#include "main/texobj.h"
#include "main/enums.h"
#include "main/simple_list.h"
#include "r300_context.h"
#include "radeon_mipmap_tree.h"
#include "r300_tex.h"
#include "r300_reg.h"
/*
* Note that the _REV formats are the same as the non-REV formats. This is
* because the REV and non-REV formats are identical as a byte string, but
* differ when accessed as 16-bit or 32-bit words depending on the endianness of
* the host. Since the textures are transferred to the R300 as a byte string
* (i.e. without any byte-swapping), the R300 sees the REV and non-REV formats
* identically. -- paulus
*/
int32_t r300TranslateTexFormat(gl_format mesaFormat)
{
switch (mesaFormat)
{
#ifdef MESA_LITTLE_ENDIAN
case MESA_FORMAT_RGBA8888:
return R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8);
case MESA_FORMAT_RGBA8888_REV:
return R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8);
case MESA_FORMAT_ARGB8888:
return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
case MESA_FORMAT_ARGB8888_REV:
return R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8);
#else
case MESA_FORMAT_RGBA8888:
return R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8);
case MESA_FORMAT_RGBA8888_REV:
return R300_EASY_TX_FORMAT(Y, Z, W, X, W8Z8Y8X8);
case MESA_FORMAT_ARGB8888:
return R300_EASY_TX_FORMAT(W, Z, Y, X, W8Z8Y8X8);
case MESA_FORMAT_ARGB8888_REV:
return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
#endif
case MESA_FORMAT_XRGB8888:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
case MESA_FORMAT_RGB888:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
case MESA_FORMAT_RGB565:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
case MESA_FORMAT_RGB565_REV:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
case MESA_FORMAT_ARGB4444:
return R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4);
case MESA_FORMAT_ARGB4444_REV:
return R300_EASY_TX_FORMAT(X, Y, Z, W, W4Z4Y4X4);
case MESA_FORMAT_ARGB1555:
return R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5);
case MESA_FORMAT_ARGB1555_REV:
return R300_EASY_TX_FORMAT(X, Y, Z, W, W1Z5Y5X5);
case MESA_FORMAT_AL88:
return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8);
case MESA_FORMAT_AL88_REV:
return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8);
case MESA_FORMAT_RGB332:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z3Y3X2);
case MESA_FORMAT_A8:
return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X8);
case MESA_FORMAT_L8:
return R300_EASY_TX_FORMAT(X, X, X, ONE, X8);
case MESA_FORMAT_I8:
return R300_EASY_TX_FORMAT(X, X, X, X, X8);
case MESA_FORMAT_YCBCR:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE;
case MESA_FORMAT_YCBCR_REV:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, G8R8_G8B8) | R300_TX_FORMAT_YUV_MODE;
case MESA_FORMAT_RGB_DXT1:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1);
case MESA_FORMAT_RGBA_DXT1:
return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1);
case MESA_FORMAT_RGBA_DXT3:
return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3);
case MESA_FORMAT_RGBA_DXT5:
return R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5);
case MESA_FORMAT_RGBA_FLOAT32:
return R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R32G32B32A32);
case MESA_FORMAT_RGBA_FLOAT16:
return R300_EASY_TX_FORMAT(Z, Y, X, W, FL_R16G16B16A16);
case MESA_FORMAT_ALPHA_FLOAT32:
return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I32);
case MESA_FORMAT_ALPHA_FLOAT16:
return R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, FL_I16);
case MESA_FORMAT_LUMINANCE_FLOAT32:
return R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I32);
case MESA_FORMAT_LUMINANCE_FLOAT16:
return R300_EASY_TX_FORMAT(X, X, X, ONE, FL_I16);
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
return R300_EASY_TX_FORMAT(X, X, X, Y, FL_I32A32);
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
return R300_EASY_TX_FORMAT(X, X, X, Y, FL_I16A16);
case MESA_FORMAT_INTENSITY_FLOAT32:
return R300_EASY_TX_FORMAT(X, X, X, X, FL_I32);
case MESA_FORMAT_INTENSITY_FLOAT16:
return R300_EASY_TX_FORMAT(X, X, X, X, FL_I16);
case MESA_FORMAT_Z16:
return R300_EASY_TX_FORMAT(X, X, X, X, X16);
case MESA_FORMAT_Z24_S8:
return R300_EASY_TX_FORMAT(X, X, X, X, X24_Y8);
case MESA_FORMAT_S8_Z24:
return R300_EASY_TX_FORMAT(Y, Y, Y, Y, X24_Y8);
case MESA_FORMAT_Z32:
return R300_EASY_TX_FORMAT(X, X, X, X, X32);
/* EXT_texture_sRGB */
case MESA_FORMAT_SARGB8:
return R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8) | R300_TX_FORMAT_GAMMA;
case MESA_FORMAT_SLA8:
return R300_EASY_TX_FORMAT(X, X, X, Y, Y8X8) | R300_TX_FORMAT_GAMMA;
case MESA_FORMAT_SL8:
return R300_EASY_TX_FORMAT(X, X, X, ONE, X8) | R300_TX_FORMAT_GAMMA;
case MESA_FORMAT_SRGB_DXT1:
return R300_EASY_TX_FORMAT(X, Y, Z, ONE, DXT1) | R300_TX_FORMAT_GAMMA;
case MESA_FORMAT_SRGBA_DXT1:
return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT1) | R300_TX_FORMAT_GAMMA;
case MESA_FORMAT_SRGBA_DXT3:
return R300_EASY_TX_FORMAT(X, Y, Z, W, DXT3) | R300_TX_FORMAT_GAMMA;
case MESA_FORMAT_SRGBA_DXT5:
return R300_EASY_TX_FORMAT(Y, Z, W, X, DXT5) | R300_TX_FORMAT_GAMMA;
default:
return -1;
}
};
void r300SetDepthTexMode(struct gl_texture_object *tObj)
{
static const GLuint formats[3][3] = {
{
R300_EASY_TX_FORMAT(X, X, X, ONE, X16),
R300_EASY_TX_FORMAT(X, X, X, X, X16),
R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X16),
},
{
R300_EASY_TX_FORMAT(Y, Y, Y, ONE, X24_Y8),
R300_EASY_TX_FORMAT(Y, Y, Y, Y, X24_Y8),
R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, Y, X24_Y8),
},
{
R300_EASY_TX_FORMAT(X, X, X, ONE, X32),
R300_EASY_TX_FORMAT(X, X, X, X, X32),
R300_EASY_TX_FORMAT(ZERO, ZERO, ZERO, X, X32),
},
};
const GLuint *format;
radeonTexObjPtr t;
if (!tObj)
return;
t = radeon_tex_obj(tObj);
switch (tObj->Image[0][tObj->BaseLevel]->TexFormat) {
case MESA_FORMAT_Z16:
format = formats[0];
break;
case MESA_FORMAT_S8_Z24:
format = formats[1];
break;
case MESA_FORMAT_Z32:
format = formats[2];
break;
default:
/* Error...which should have already been caught by higher
* levels of Mesa.
*/
ASSERT(0);
return;
}
switch (tObj->Sampler.DepthMode) {
case GL_LUMINANCE:
t->pp_txformat = format[0];
break;
case GL_INTENSITY:
t->pp_txformat = format[1];
break;
case GL_ALPHA:
t->pp_txformat = format[2];
break;
default:
/* Error...which should have already been caught by higher
* levels of Mesa.
*/
ASSERT(0);
return;
}
}
/**
* Compute the cached hardware register values for the given texture object.
*
* \param rmesa Context pointer
* \param t the r300 texture object
*/
static void setup_hardware_state(r300ContextPtr rmesa, radeonTexObj *t)
{
const struct gl_texture_image *firstImage;
firstImage = t->base.Image[0][t->minLod];
if (!t->image_override) {
if (firstImage->_BaseFormat == GL_DEPTH_COMPONENT) {
r300SetDepthTexMode(&t->base);
} else {
int32_t txformat = r300TranslateTexFormat(firstImage->TexFormat);
if (txformat < 0) {
_mesa_problem(rmesa->radeon.glCtx, "%s: Invalid format %s",
__FUNCTION__, _mesa_get_format_name(firstImage->TexFormat));
exit(1);
}
t->pp_txformat = (uint32_t) txformat;
}
}
if (t->image_override && t->bo)
return;
t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((firstImage->Width - 1) << R300_TX_WIDTHMASK_SHIFT)))
| ((R300_TX_HEIGHTMASK_MASK & ((firstImage->Height - 1) << R300_TX_HEIGHTMASK_SHIFT)))
| ((R300_TX_DEPTHMASK_MASK & ((firstImage->DepthLog2) << R300_TX_DEPTHMASK_SHIFT)))
| ((R300_TX_MAX_MIP_LEVEL_MASK & ((t->maxLod - t->minLod) << R300_TX_MAX_MIP_LEVEL_SHIFT))));
t->tile_bits = 0;
if (t->base.Target == GL_TEXTURE_CUBE_MAP)
t->pp_txformat |= R300_TX_FORMAT_CUBIC_MAP;
if (t->base.Target == GL_TEXTURE_3D)
t->pp_txformat |= R300_TX_FORMAT_3D;
if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
unsigned int align = (64 / _mesa_get_format_bytes(firstImage->TexFormat)) - 1;
t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
if (!t->image_override)
t->pp_txpitch = ((firstImage->Width + align) & ~align) - 1;
}
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (firstImage->Width > 2048)
t->pp_txpitch |= R500_TXWIDTH_BIT11;
else
t->pp_txpitch &= ~R500_TXWIDTH_BIT11;
if (firstImage->Height > 2048)
t->pp_txpitch |= R500_TXHEIGHT_BIT11;
else
t->pp_txpitch &= ~R500_TXHEIGHT_BIT11;
}
}
/**
* Ensure the given texture is ready for rendering.
*
* Mostly this means populating the texture object's mipmap tree.
*/
static GLboolean r300_validate_texture(struct gl_context * ctx, struct gl_texture_object *texObj)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
radeonTexObj *t = radeon_tex_obj(texObj);
if (!radeon_validate_texture_miptree(ctx, texObj))
return GL_FALSE;
/* Configure the hardware registers (more precisely, the cached version
* of the hardware registers). */
setup_hardware_state(rmesa, t);
t->validated = GL_TRUE;
return GL_TRUE;
}
/**
* Ensure all enabled and complete textures are uploaded along with any buffers being used.
*/
GLboolean r300ValidateBuffers(struct gl_context * ctx)
{
r300ContextPtr rmesa = R300_CONTEXT(ctx);
struct radeon_renderbuffer *rrb;
int i;
int ret;
radeon_cs_space_reset_bos(rmesa->radeon.cmdbuf.cs);
rrb = radeon_get_colorbuffer(&rmesa->radeon);
/* color buffer */
if (rrb && rrb->bo) {
radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
rrb->bo, 0,
RADEON_GEM_DOMAIN_VRAM);
}
/* depth buffer */
rrb = radeon_get_depthbuffer(&rmesa->radeon);
if (rrb && rrb->bo) {
radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
rrb->bo, 0,
RADEON_GEM_DOMAIN_VRAM);
}
for (i = 0; i < ctx->Const.MaxTextureImageUnits; ++i) {
radeonTexObj *t;
if (!ctx->Texture.Unit[i]._ReallyEnabled)
continue;
if (!r300_validate_texture(ctx, ctx->Texture.Unit[i]._Current)) {
_mesa_warning(ctx,
"failed to validate texture for unit %d.\n",
i);
}
t = radeon_tex_obj(ctx->Texture.Unit[i]._Current);
if (t->image_override && t->bo)
radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
t->bo,
RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
else if (t->mt->bo)
radeon_cs_space_add_persistent_bo(rmesa->radeon.cmdbuf.cs,
t->mt->bo,
RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM, 0);
}
ret = radeon_cs_space_check_with_bo(rmesa->radeon.cmdbuf.cs, first_elem(&rmesa->radeon.dma.reserved)->bo, RADEON_GEM_DOMAIN_GTT, 0);
if (ret)
return GL_FALSE;
return GL_TRUE;
}
void r300SetTexOffset(__DRIcontext * pDRICtx, GLint texname,
unsigned long long offset, GLint depth, GLuint pitch)
{
r300ContextPtr rmesa = pDRICtx->driverPrivate;
struct gl_texture_object *tObj =
_mesa_lookup_texture(rmesa->radeon.glCtx, texname);
radeonTexObjPtr t = radeon_tex_obj(tObj);
uint32_t pitch_val;
if (!tObj)
return;
t->image_override = GL_TRUE;
if (!offset)
return;
t->bo = NULL;
t->override_offset = offset;
t->pp_txpitch &= (1 << 13) -1;
pitch_val = pitch;
switch (depth) {
case 32:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
pitch_val /= 4;
break;
case 24:
default:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
pitch_val /= 4;
break;
case 16:
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
pitch_val /= 2;
break;
}
pitch_val--;
t->pp_txpitch |= pitch_val;
}
void r300SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format, __DRIdrawable *dPriv)
{
struct gl_texture_unit *texUnit;
struct gl_texture_object *texObj;
struct gl_texture_image *texImage;
struct radeon_renderbuffer *rb;
radeon_texture_image *rImage;
radeonContextPtr radeon;
r300ContextPtr rmesa;
struct radeon_framebuffer *rfb;
radeonTexObjPtr t;
uint32_t pitch_val;
gl_format texFormat;
radeon = pDRICtx->driverPrivate;
rmesa = pDRICtx->driverPrivate;
rfb = dPriv->driverPrivate;
texUnit = &radeon->glCtx->Texture.Unit[radeon->glCtx->Texture.CurrentUnit];
texObj = _mesa_select_tex_object(radeon->glCtx, texUnit, target);
texImage = _mesa_get_tex_image(radeon->glCtx, texObj, target, 0);
rImage = get_radeon_texture_image(texImage);
t = radeon_tex_obj(texObj);
if (t == NULL) {
return;
}
radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE);
rb = rfb->color_rb[0];
if (rb->bo == NULL) {
/* Failed to BO for the buffer */
return;
}
_mesa_lock_texture(radeon->glCtx, texObj);
if (t->bo) {
radeon_bo_unref(t->bo);
t->bo = NULL;
}
if (rImage->bo) {
radeon_bo_unref(rImage->bo);
rImage->bo = NULL;
}
radeon_miptree_unreference(&t->mt);
radeon_miptree_unreference(&rImage->mt);
rImage->bo = rb->bo;
radeon_bo_ref(rImage->bo);
t->bo = rb->bo;
radeon_bo_ref(t->bo);
t->tile_bits = 0;
t->image_override = GL_TRUE;
t->override_offset = 0;
t->pp_txpitch &= (1 << 13) -1;
pitch_val = rb->pitch;
switch (rb->cpp) {
case 4:
if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
texFormat = MESA_FORMAT_RGB888;
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
}
else {
texFormat = MESA_FORMAT_ARGB8888;
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8);
}
pitch_val /= 4;
break;
case 3:
default:
texFormat = MESA_FORMAT_RGB888;
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, W8Z8Y8X8);
pitch_val /= 4;
break;
case 2:
texFormat = MESA_FORMAT_RGB565;
t->pp_txformat = R300_EASY_TX_FORMAT(X, Y, Z, ONE, Z5Y6X5);
pitch_val /= 2;
break;
}
_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
rb->base.Width, rb->base.Height, 1, 0,
rb->cpp, texFormat);
rImage->base.RowStride = rb->pitch / rb->cpp;
pitch_val--;
t->pp_txsize = (((R300_TX_WIDTHMASK_MASK & ((rb->base.Width - 1) << R300_TX_WIDTHMASK_SHIFT)))
| ((R300_TX_HEIGHTMASK_MASK & ((rb->base.Height - 1) << R300_TX_HEIGHTMASK_SHIFT))));
t->pp_txsize |= R300_TX_SIZE_TXPITCH_EN;
t->pp_txpitch |= pitch_val;
if (rmesa->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515) {
if (rb->base.Width > 2048)
t->pp_txpitch |= R500_TXWIDTH_BIT11;
else
t->pp_txpitch &= ~R500_TXWIDTH_BIT11;
if (rb->base.Height > 2048)
t->pp_txpitch |= R500_TXHEIGHT_BIT11;
else
t->pp_txpitch &= ~R500_TXHEIGHT_BIT11;
}
t->validated = GL_TRUE;
_mesa_unlock_texture(radeon->glCtx, texObj);
return;
}
void r300SetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
{
r300SetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv);
}

421
src/mesa/drivers/dri/r300/r300_vertprog.c
View file

@ -1,421 +0,0 @@
/**************************************************************************
Copyright (C) 2005 Aapo Tahkola <aet@rasterburn.org>
Copyright (C) 2008 Oliver McFadden <z3ro.geek@gmail.com>
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/* Radeon R5xx Acceleration, Revision 1.2 */
#include "main/glheader.h"
#include "main/macros.h"
#include "main/enums.h"
#include "program/program.h"
#include "program/programopt.h"
#include "program/prog_instruction.h"
#include "program/prog_parameter.h"
#include "program/prog_print.h"
#include "program/prog_statevars.h"
#include "tnl/tnl.h"
#include "compiler/radeon_compiler.h"
#include "radeon_mesa_to_rc.h"
#include "r300_context.h"
#include "r300_fragprog_common.h"
#include "r300_state.h"
/**
* Write parameter array for the given vertex program into dst.
* Return the total number of components written.
*/
static int r300VertexProgUpdateParams(struct gl_context * ctx, struct r300_vertex_program *vp, float *dst)
{
int i;
if (vp->Base->IsNVProgram) {
_mesa_load_tracked_matrices(ctx);
} else {
if (vp->Base->Base.Parameters) {
_mesa_load_state_parameters(ctx, vp->Base->Base.Parameters);
}
}
for(i = 0; i < vp->code.constants.Count; ++i) {
const float * src = 0;
const struct rc_constant * constant = &vp->code.constants.Constants[i];
switch(constant->Type) {
case RC_CONSTANT_EXTERNAL:
if (vp->Base->IsNVProgram) {
src = ctx->VertexProgram.Parameters[constant->u.External];
} else {
src = &vp->Base->Base.Parameters->ParameterValues[constant->u.External][0].f;
}
break;
case RC_CONSTANT_IMMEDIATE:
src = constant->u.Immediate;
break;
}
assert(src);
dst[4*i] = src[0];
dst[4*i + 1] = src[1];
dst[4*i + 2] = src[2];
dst[4*i + 3] = src[3];
}
return 4 * vp->code.constants.Count;
}
static GLbitfield compute_required_outputs(struct gl_vertex_program * vp, GLbitfield fpreads)
{
GLbitfield outputs = 0;
int i;
#define ADD_OUTPUT(fp_attr, vp_result) \
do { \
if (fpreads & (1 << (fp_attr))) \
outputs |= (1 << (vp_result)); \
} while (0)
ADD_OUTPUT(FRAG_ATTRIB_COL0, VERT_RESULT_COL0);
ADD_OUTPUT(FRAG_ATTRIB_COL1, VERT_RESULT_COL1);
for (i = 0; i <= 7; ++i) {
ADD_OUTPUT(FRAG_ATTRIB_TEX0 + i, VERT_RESULT_TEX0 + i);
}
#undef ADD_OUTPUT
if ((fpreads & (1 << FRAG_ATTRIB_COL0)) &&
(vp->Base.OutputsWritten & (1 << VERT_RESULT_BFC0)))
outputs |= 1 << VERT_RESULT_BFC0;
if ((fpreads & (1 << FRAG_ATTRIB_COL1)) &&
(vp->Base.OutputsWritten & (1 << VERT_RESULT_BFC1)))
outputs |= 1 << VERT_RESULT_BFC1;
outputs |= 1 << VERT_RESULT_HPOS;
if (vp->Base.OutputsWritten & (1 << VERT_RESULT_PSIZ))
outputs |= 1 << VERT_RESULT_PSIZ;
return outputs;
}
static void t_inputs_outputs(struct r300_vertex_program_compiler * c)
{
int i;
int cur_reg;
GLuint OutputsWritten, InputsRead;
OutputsWritten = c->Base.Program.OutputsWritten;
InputsRead = c->Base.Program.InputsRead;
cur_reg = -1;
for (i = 0; i < VERT_ATTRIB_MAX; i++) {
if (InputsRead & (1 << i))
c->code->inputs[i] = ++cur_reg;
else
c->code->inputs[i] = -1;
}
cur_reg = 0;
for (i = 0; i < VERT_RESULT_MAX; i++)
c->code->outputs[i] = -1;
assert(OutputsWritten & (1 << VERT_RESULT_HPOS));
if (OutputsWritten & (1 << VERT_RESULT_HPOS)) {
c->code->outputs[VERT_RESULT_HPOS] = cur_reg++;
}
if (OutputsWritten & (1 << VERT_RESULT_PSIZ)) {
c->code->outputs[VERT_RESULT_PSIZ] = cur_reg++;
}
/* If we're writing back facing colors we need to send
* four colors to make front/back face colors selection work.
* If the vertex program doesn't write all 4 colors, lets
* pretend it does by skipping output index reg so the colors
* get written into appropriate output vectors.
*/
if (OutputsWritten & (1 << VERT_RESULT_COL0)) {
c->code->outputs[VERT_RESULT_COL0] = cur_reg++;
} else if (OutputsWritten & (1 << VERT_RESULT_BFC0) ||
OutputsWritten & (1 << VERT_RESULT_BFC1)) {
cur_reg++;
}
if (OutputsWritten & (1 << VERT_RESULT_COL1)) {
c->code->outputs[VERT_RESULT_COL1] = cur_reg++;
} else if (OutputsWritten & (1 << VERT_RESULT_BFC0) ||
OutputsWritten & (1 << VERT_RESULT_BFC1)) {
cur_reg++;
}
if (OutputsWritten & (1 << VERT_RESULT_BFC0)) {
c->code->outputs[VERT_RESULT_BFC0] = cur_reg++;
} else if (OutputsWritten & (1 << VERT_RESULT_BFC1)) {
cur_reg++;
}
if (OutputsWritten & (1 << VERT_RESULT_BFC1)) {
c->code->outputs[VERT_RESULT_BFC1] = cur_reg++;
} else if (OutputsWritten & (1 << VERT_RESULT_BFC0)) {
cur_reg++;
}
for (i = VERT_RESULT_TEX0; i <= VERT_RESULT_TEX7; i++) {
if (OutputsWritten & (1 << i)) {
c->code->outputs[i] = cur_reg++;
}
}
if (OutputsWritten & (1 << VERT_RESULT_FOGC)) {
c->code->outputs[VERT_RESULT_FOGC] = cur_reg++;
}
}
/**
* The NV_vertex_program spec mandates that all registers be
* initialized to zero. We do this here unconditionally.
*
* \note We rely on dead-code elimination in the compiler.
*/
static void initialize_NV_registers(struct radeon_compiler * compiler)
{
unsigned int reg;
struct rc_instruction * inst;
for(reg = 0; reg < 12; ++reg) {
inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
inst->U.I.Opcode = RC_OPCODE_MOV;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = reg;
inst->U.I.SrcReg[0].File = RC_FILE_NONE;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
}
inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
inst->U.I.Opcode = RC_OPCODE_ARL;
inst->U.I.DstReg.File = RC_FILE_ADDRESS;
inst->U.I.DstReg.Index = 0;
inst->U.I.DstReg.WriteMask = WRITEMASK_X;
inst->U.I.SrcReg[0].File = RC_FILE_NONE;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
}
static struct r300_vertex_program *build_program(struct gl_context *ctx,
struct r300_vertex_program_key *wanted_key,
const struct gl_vertex_program *mesa_vp)
{
struct r300_vertex_program *vp;
struct r300_vertex_program_compiler compiler;
vp = calloc(1, sizeof(*vp));
vp->Base = _mesa_clone_vertex_program(ctx, mesa_vp);
memcpy(&vp->key, wanted_key, sizeof(vp->key));
memset(&compiler, 0, sizeof(compiler));
rc_init(&compiler.Base);
compiler.Base.Debug = (RADEON_DEBUG & RADEON_VERTS) ? GL_TRUE : GL_FALSE;
compiler.code = &vp->code;
compiler.RequiredOutputs = compute_required_outputs(vp->Base, vp->key.FpReads);
compiler.SetHwInputOutput = &t_inputs_outputs;
compiler.Base.is_r500 = R300_CONTEXT(ctx)->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV515;
compiler.Base.disable_optimizations = 0;
compiler.Base.has_half_swizzles = 0;
compiler.Base.max_temp_regs = 32;
compiler.Base.max_constants = 256;
compiler.Base.max_alu_insts = compiler.Base.is_r500 ? 1024 : 256;
if (compiler.Base.Debug) {
fprintf(stderr, "Initial vertex program:\n");
_mesa_print_program(&vp->Base->Base);
fflush(stderr);
}
if (mesa_vp->IsPositionInvariant) {
_mesa_insert_mvp_code(ctx, vp->Base);
}
radeon_mesa_to_rc_program(&compiler.Base, &vp->Base->Base);
if (mesa_vp->IsNVProgram)
initialize_NV_registers(&compiler.Base);
rc_move_output(&compiler.Base, VERT_RESULT_PSIZ, VERT_RESULT_PSIZ, WRITEMASK_X);
if (vp->key.WPosAttr != FRAG_ATTRIB_MAX) {
unsigned int vp_wpos_attr = vp->key.WPosAttr - FRAG_ATTRIB_TEX0 + VERT_RESULT_TEX0;
/* Set empty writemask for instructions writing to vp_wpos_attr
* before moving the wpos attr there.
* Such instructions will be removed by DCE.
*/
rc_move_output(&compiler.Base, vp_wpos_attr, vp->key.WPosAttr, 0);
rc_copy_output(&compiler.Base, VERT_RESULT_HPOS, vp_wpos_attr);
}
if (vp->key.FogAttr != FRAG_ATTRIB_MAX) {
unsigned int vp_fog_attr = vp->key.FogAttr - FRAG_ATTRIB_TEX0 + VERT_RESULT_TEX0;
/* Set empty writemask for instructions writing to vp_fog_attr
* before moving the fog attr there.
* Such instructions will be removed by DCE.
*/
rc_move_output(&compiler.Base, vp_fog_attr, vp->key.FogAttr, 0);
rc_move_output(&compiler.Base, VERT_RESULT_FOGC, vp_fog_attr, WRITEMASK_X);
}
r3xx_compile_vertex_program(&compiler);
if (vp->code.constants.Count > ctx->Const.VertexProgram.MaxParameters) {
rc_error(&compiler.Base, "Program exceeds constant buffer size limit\n");
}
vp->error = compiler.Base.Error;
vp->Base->Base.InputsRead = vp->code.InputsRead;
vp->Base->Base.OutputsWritten = vp->code.OutputsWritten;
rc_destroy(&compiler.Base);
return vp;
}
struct r300_vertex_program * r300SelectAndTranslateVertexShader(struct gl_context *ctx)
{
r300ContextPtr r300 = R300_CONTEXT(ctx);
struct r300_vertex_program_key wanted_key = { 0 };
struct r300_vertex_program_cont *vpc;
struct r300_vertex_program *vp;
vpc = (struct r300_vertex_program_cont *)ctx->VertexProgram._Current;
if (!r300->selected_fp) {
/* This can happen when GetProgramiv is called to check
* whether the program runs natively.
*
* To be honest, this is not a very good solution,
* but solving the problem of reporting good values
* for those queries is tough anyway considering that
* we recompile vertex programs based on the precise
* fragment program that is in use.
*/
r300SelectAndTranslateFragmentShader(ctx);
}
assert(r300->selected_fp);
wanted_key.FpReads = r300->selected_fp->InputsRead;
wanted_key.FogAttr = r300->selected_fp->fog_attr;
wanted_key.WPosAttr = r300->selected_fp->wpos_attr;
for (vp = vpc->progs; vp; vp = vp->next) {
if (memcmp(&vp->key, &wanted_key, sizeof(wanted_key)) == 0) {
return r300->selected_vp = vp;
}
}
vp = build_program(ctx, &wanted_key, &vpc->mesa_program);
vp->next = vpc->progs;
vpc->progs = vp;
return r300->selected_vp = vp;
}
#define bump_vpu_count(ptr, new_count) do { \
drm_r300_cmd_header_t* _p=((drm_r300_cmd_header_t*)(ptr)); \
int _nc=(new_count)/4; \
if(_nc>_p->vpu.count)_p->vpu.count=_nc; \
} while(0)
static void r300EmitVertexProgram(r300ContextPtr r300, int dest, struct r300_vertex_program_code *code)
{
int i;
assert((code->length > 0) && (code->length % 4 == 0));
switch ((dest >> 8) & 0xf) {
case 0:
R300_STATECHANGE(r300, vpi);
for (i = 0; i < code->length; i++)
r300->hw.vpi.cmd[R300_VPI_INSTR_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]);
bump_vpu_count(r300->hw.vpi.cmd, code->length + 4 * (dest & 0xff));
break;
case 2:
R300_STATECHANGE(r300, vpp);
for (i = 0; i < code->length; i++)
r300->hw.vpp.cmd[R300_VPP_PARAM_0 + i + 4 * (dest & 0xff)] = (code->body.d[i]);
bump_vpu_count(r300->hw.vpp.cmd, code->length + 4 * (dest & 0xff));
break;
case 4:
R300_STATECHANGE(r300, vps);
for (i = 0; i < code->length; i++)
r300->hw.vps.cmd[1 + i + 4 * (dest & 0xff)] = (code->body.d[i]);
bump_vpu_count(r300->hw.vps.cmd, code->length + 4 * (dest & 0xff));
break;
default:
fprintf(stderr, "%s:%s don't know how to handle dest %04x\n", __FILE__, __FUNCTION__, dest);
exit(-1);
}
}
void r300SetupVertexProgram(r300ContextPtr rmesa)
{
struct gl_context *ctx = rmesa->radeon.glCtx;
struct r300_vertex_program *prog = rmesa->selected_vp;
int inst_count = 0;
int param_count = 0;
/* Reset state, in case we don't use something */
((drm_r300_cmd_header_t *) rmesa->hw.vpp.cmd)->vpu.count = 0;
((drm_r300_cmd_header_t *) rmesa->hw.vpi.cmd)->vpu.count = 0;
((drm_r300_cmd_header_t *) rmesa->hw.vps.cmd)->vpu.count = 0;
R300_STATECHANGE(rmesa, vap_cntl);
R300_STATECHANGE(rmesa, vpp);
param_count = r300VertexProgUpdateParams(ctx, prog, (float *)&rmesa->hw.vpp.cmd[R300_VPP_PARAM_0]);
if (!rmesa->radeon.radeonScreen->kernel_mm && param_count > 255 * 4) {
WARN_ONCE("Too many VP params, expect rendering errors\n");
}
/* Prevent the overflow (vpu.count is u8) */
bump_vpu_count(rmesa->hw.vpp.cmd, MIN2(255 * 4, param_count));
param_count /= 4;
r300EmitVertexProgram(rmesa, R300_PVS_CODE_START, &(prog->code));
inst_count = (prog->code.length / 4) - 1;
r300VapCntl(rmesa, _mesa_bitcount(prog->code.InputsRead),
_mesa_bitcount(prog->code.OutputsWritten), prog->code.num_temporaries);
R300_STATECHANGE(rmesa, pvs);
rmesa->hw.pvs.cmd[R300_PVS_CNTL_1] = (0 << R300_PVS_FIRST_INST_SHIFT) | (inst_count << R300_PVS_XYZW_VALID_INST_SHIFT) |
(inst_count << R300_PVS_LAST_INST_SHIFT);
rmesa->hw.pvs.cmd[R300_PVS_CNTL_2] = (0 << R300_PVS_CONST_BASE_OFFSET_SHIFT) | ((param_count - 1) << R300_PVS_MAX_CONST_ADDR_SHIFT);
rmesa->hw.pvs.cmd[R300_PVS_CNTL_3] = (inst_count << R300_PVS_LAST_VTX_SRC_INST_SHIFT);
}

11
src/mesa/drivers/dri/r300/r300_vertprog.h
View file

@ -1,11 +0,0 @@
#ifndef __R300_VERTPROG_H_
#define __R300_VERTPROG_H_
#include "r300_reg.h"
void r300SetupVertexProgram(r300ContextPtr rmesa);
struct r300_vertex_program * r300SelectAndTranslateVertexShader(struct gl_context *ctx);
#endif

1
src/mesa/drivers/dri/r300/radeon_bo.c
View file

@ -1 +0,0 @@
../radeon/radeon_bo.c

1
src/mesa/drivers/dri/r300/radeon_bo_int_drm.h
View file

@ -1 +0,0 @@
../radeon/radeon_bo_int_drm.h

1
src/mesa/drivers/dri/r300/radeon_bo_legacy.c
View file

@ -1 +0,0 @@
../radeon/radeon_bo_legacy.c

1
src/mesa/drivers/dri/r300/radeon_bo_legacy.h
View file

@ -1 +0,0 @@
../radeon/radeon_bo_legacy.h

1
src/mesa/drivers/dri/r300/radeon_bocs_wrapper.h
View file

@ -1 +0,0 @@
../radeon/radeon_bocs_wrapper.h

1
src/mesa/drivers/dri/r300/radeon_buffer_objects.c
View file

@ -1 +0,0 @@
../radeon/radeon_buffer_objects.c

1
src/mesa/drivers/dri/r300/radeon_buffer_objects.h
View file

@ -1 +0,0 @@
../radeon/radeon_buffer_objects.h

1
src/mesa/drivers/dri/r300/radeon_chipset.h
View file

@ -1 +0,0 @@
../radeon/radeon_chipset.h

1
src/mesa/drivers/dri/r300/radeon_cmdbuf.h
View file

@ -1 +0,0 @@
../radeon/radeon_cmdbuf.h

1
src/mesa/drivers/dri/r300/radeon_common.c
View file

@ -1 +0,0 @@
../radeon/radeon_common.c

1
src/mesa/drivers/dri/r300/radeon_common.h
View file

@ -1 +0,0 @@
../radeon/radeon_common.h

1
src/mesa/drivers/dri/r300/radeon_common_context.c
View file

@ -1 +0,0 @@
../radeon/radeon_common_context.c

1
src/mesa/drivers/dri/r300/radeon_common_context.h
View file

@ -1 +0,0 @@
../radeon/radeon_common_context.h

60
src/mesa/drivers/dri/r300/radeon_context.h
View file

@ -1,60 +0,0 @@
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
The Weather Channel (TM) funded Tungsten Graphics to develop the
initial release of the Radeon 8500 driver under the XFree86 license.
This notice must be preserved.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Gareth Hughes <gareth@valinux.com>
* Keith Whitwell <keith@tungstengraphics.com>
* Kevin E. Martin <martin@valinux.com>
* Nicolai Haehnle <prefect_@gmx.net>
*/
#ifndef __RADEON_CONTEXT_H__
#define __RADEON_CONTEXT_H__
#include "main/mtypes.h"
#include "main/colormac.h"
#include "radeon_screen.h"
#include "drm.h"
#include "dri_util.h"
#define FALLBACK( radeon, bit, mode ) fprintf(stderr, "%s:%s\n", __LINE__, __FILE__);
/* TCL fallbacks */
extern void radeonTclFallback(struct gl_context * ctx, GLuint bit, GLboolean mode);
#define TCL_FALLBACK( ctx, bit, mode ) ;
#endif /* __RADEON_CONTEXT_H__ */

1
src/mesa/drivers/dri/r300/radeon_cs.c
View file

@ -1 +0,0 @@
../radeon/radeon_cs.c

1
src/mesa/drivers/dri/r300/radeon_cs_int_drm.h
View file

@ -1 +0,0 @@
../radeon/radeon_cs_int_drm.h

1
src/mesa/drivers/dri/r300/radeon_cs_legacy.c
View file

@ -1 +0,0 @@
../radeon/radeon_cs_legacy.c

1
src/mesa/drivers/dri/r300/radeon_cs_legacy.h
View file

@ -1 +0,0 @@
../radeon/radeon_cs_legacy.h

1
src/mesa/drivers/dri/r300/radeon_cs_space_drm.c
View file

@ -1 +0,0 @@
../radeon/radeon_cs_space_drm.c

1
src/mesa/drivers/dri/r300/radeon_debug.c
View file

@ -1 +0,0 @@
../radeon/radeon_debug.c

1
src/mesa/drivers/dri/r300/radeon_debug.h
View file

@ -1 +0,0 @@
../radeon/radeon_debug.h

1
src/mesa/drivers/dri/r300/radeon_dma.c
View file

@ -1 +0,0 @@
../radeon/radeon_dma.c

1
src/mesa/drivers/dri/r300/radeon_dma.h
View file

@ -1 +0,0 @@
../radeon/radeon_dma.h

1
src/mesa/drivers/dri/r300/radeon_fbo.c
View file

@ -1 +0,0 @@
../radeon/radeon_fbo.c

1
src/mesa/drivers/dri/r300/radeon_lock.c
View file

@ -1 +0,0 @@
../radeon/radeon_lock.c

1
src/mesa/drivers/dri/r300/radeon_lock.h
View file

@ -1 +0,0 @@
../radeon/radeon_lock.h

223
src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c
View file

@ -1,223 +0,0 @@
/*
* Copyright (C) 2009 Nicolai Haehnle.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include "radeon_mesa_to_rc.h"
#include "main/mtypes.h"
#include "program/prog_instruction.h"
#include "program/prog_parameter.h"
#include "compiler/radeon_compiler.h"
#include "compiler/radeon_program.h"
static rc_opcode translate_opcode(gl_inst_opcode opcode)
{
switch(opcode) {
case OPCODE_NOP: return RC_OPCODE_NOP;
case OPCODE_ABS: return RC_OPCODE_ABS;
case OPCODE_ADD: return RC_OPCODE_ADD;
case OPCODE_ARL: return RC_OPCODE_ARL;
case OPCODE_CMP: return RC_OPCODE_CMP;
case OPCODE_COS: return RC_OPCODE_COS;
case OPCODE_DDX: return RC_OPCODE_DDX;
case OPCODE_DDY: return RC_OPCODE_DDY;
case OPCODE_DP3: return RC_OPCODE_DP3;
case OPCODE_DP4: return RC_OPCODE_DP4;
case OPCODE_DPH: return RC_OPCODE_DPH;
case OPCODE_DST: return RC_OPCODE_DST;
case OPCODE_EX2: return RC_OPCODE_EX2;
case OPCODE_EXP: return RC_OPCODE_EXP;
case OPCODE_FLR: return RC_OPCODE_FLR;
case OPCODE_FRC: return RC_OPCODE_FRC;
case OPCODE_KIL: return RC_OPCODE_KIL;
case OPCODE_LG2: return RC_OPCODE_LG2;
case OPCODE_LIT: return RC_OPCODE_LIT;
case OPCODE_LOG: return RC_OPCODE_LOG;
case OPCODE_LRP: return RC_OPCODE_LRP;
case OPCODE_MAD: return RC_OPCODE_MAD;
case OPCODE_MAX: return RC_OPCODE_MAX;
case OPCODE_MIN: return RC_OPCODE_MIN;
case OPCODE_MOV: return RC_OPCODE_MOV;
case OPCODE_MUL: return RC_OPCODE_MUL;
case OPCODE_POW: return RC_OPCODE_POW;
case OPCODE_RCP: return RC_OPCODE_RCP;
case OPCODE_RSQ: return RC_OPCODE_RSQ;
case OPCODE_SCS: return RC_OPCODE_SCS;
case OPCODE_SEQ: return RC_OPCODE_SEQ;
case OPCODE_SFL: return RC_OPCODE_SFL;
case OPCODE_SGE: return RC_OPCODE_SGE;
case OPCODE_SGT: return RC_OPCODE_SGT;
case OPCODE_SIN: return RC_OPCODE_SIN;
case OPCODE_SLE: return RC_OPCODE_SLE;
case OPCODE_SLT: return RC_OPCODE_SLT;
case OPCODE_SNE: return RC_OPCODE_SNE;
case OPCODE_SUB: return RC_OPCODE_SUB;
case OPCODE_SWZ: return RC_OPCODE_SWZ;
case OPCODE_TEX: return RC_OPCODE_TEX;
case OPCODE_TXB: return RC_OPCODE_TXB;
case OPCODE_TXD: return RC_OPCODE_TXD;
case OPCODE_TXL: return RC_OPCODE_TXL;
case OPCODE_TXP: return RC_OPCODE_TXP;
case OPCODE_XPD: return RC_OPCODE_XPD;
default: return RC_OPCODE_ILLEGAL_OPCODE;
}
}
static rc_saturate_mode translate_saturate(unsigned int saturate)
{
switch(saturate) {
default:
case SATURATE_OFF: return RC_SATURATE_NONE;
case SATURATE_ZERO_ONE: return RC_SATURATE_ZERO_ONE;
}
}
static rc_register_file translate_register_file(unsigned int file)
{
switch(file) {
case PROGRAM_TEMPORARY: return RC_FILE_TEMPORARY;
case PROGRAM_INPUT: return RC_FILE_INPUT;
case PROGRAM_OUTPUT: return RC_FILE_OUTPUT;
case PROGRAM_LOCAL_PARAM:
case PROGRAM_ENV_PARAM:
case PROGRAM_STATE_VAR:
case PROGRAM_NAMED_PARAM:
case PROGRAM_CONSTANT:
case PROGRAM_UNIFORM: return RC_FILE_CONSTANT;
case PROGRAM_ADDRESS: return RC_FILE_ADDRESS;
default: return RC_FILE_NONE;
}
}
static void translate_srcreg(struct rc_src_register * dest, struct prog_src_register * src)
{
dest->File = translate_register_file(src->File);
dest->Index = src->Index;
dest->RelAddr = src->RelAddr;
dest->Swizzle = src->Swizzle;
dest->Abs = src->Abs;
dest->Negate = src->Negate;
}
static void translate_dstreg(struct rc_dst_register * dest, struct prog_dst_register * src)
{
dest->File = translate_register_file(src->File);
dest->Index = src->Index;
dest->WriteMask = src->WriteMask;
}
static rc_texture_target translate_tex_target(gl_texture_index target)
{
switch(target) {
case TEXTURE_2D_ARRAY_INDEX: return RC_TEXTURE_2D_ARRAY;
case TEXTURE_1D_ARRAY_INDEX: return RC_TEXTURE_1D_ARRAY;
case TEXTURE_CUBE_INDEX: return RC_TEXTURE_CUBE;
case TEXTURE_3D_INDEX: return RC_TEXTURE_3D;
case TEXTURE_RECT_INDEX: return RC_TEXTURE_RECT;
default:
case TEXTURE_2D_INDEX: return RC_TEXTURE_2D;
case TEXTURE_1D_INDEX: return RC_TEXTURE_1D;
}
}
static void translate_instruction(struct radeon_compiler * c,
struct rc_instruction * dest, struct prog_instruction * src)
{
const struct rc_opcode_info * opcode;
unsigned int i;
dest->U.I.Opcode = translate_opcode(src->Opcode);
if (dest->U.I.Opcode == RC_OPCODE_ILLEGAL_OPCODE) {
rc_error(c, "Unsupported opcode %i\n", src->Opcode);
return;
}
dest->U.I.SaturateMode = translate_saturate(src->SaturateMode);
opcode = rc_get_opcode_info(dest->U.I.Opcode);
for(i = 0; i < opcode->NumSrcRegs; ++i)
translate_srcreg(&dest->U.I.SrcReg[i], &src->SrcReg[i]);
if (opcode->HasDstReg)
translate_dstreg(&dest->U.I.DstReg, &src->DstReg);
if (opcode->HasTexture) {
dest->U.I.TexSrcUnit = src->TexSrcUnit;
dest->U.I.TexSrcTarget = translate_tex_target(src->TexSrcTarget);
dest->U.I.TexShadow = src->TexShadow;
dest->U.I.TexSwizzle = RC_SWIZZLE_XYZW;
}
}
void radeon_mesa_to_rc_program(struct radeon_compiler * c, struct gl_program * program)
{
struct prog_instruction *source;
unsigned int i;
for(source = program->Instructions; source->Opcode != OPCODE_END; ++source) {
struct rc_instruction * dest = rc_insert_new_instruction(c, c->Program.Instructions.Prev);
translate_instruction(c, dest, source);
}
c->Program.ShadowSamplers = program->ShadowSamplers;
c->Program.InputsRead = program->InputsRead;
c->Program.OutputsWritten = program->OutputsWritten;
int isNVProgram = 0;
if (program->Target == GL_VERTEX_PROGRAM_ARB) {
struct gl_vertex_program * vp = (struct gl_vertex_program *) program;
isNVProgram = vp->IsNVProgram;
}
if (isNVProgram) {
/* NV_vertex_program has a fixed-sized constant environment.
* This could be handled more efficiently for programs that
* do not use relative addressing.
*/
for(i = 0; i < 96; ++i) {
struct rc_constant constant;
constant.Type = RC_CONSTANT_EXTERNAL;
constant.Size = 4;
constant.u.External = i;
rc_constants_add(&c->Program.Constants, &constant);
}
} else {
for(i = 0; i < program->Parameters->NumParameters; ++i) {
struct rc_constant constant;
constant.Type = RC_CONSTANT_EXTERNAL;
constant.Size = 4;
constant.u.External = i;
rc_constants_add(&c->Program.Constants, &constant);
}
}
}

36
src/mesa/drivers/dri/r300/radeon_mesa_to_rc.h
View file

@ -1,36 +0,0 @@
/*
* Copyright (C) 2009 Nicolai Haehnle.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef RADEON_MESA_TO_RC_H
#define RADEON_MESA_TO_RC_H
struct gl_program;
struct radeon_compiler;
void radeon_mesa_to_rc_program(struct radeon_compiler * c, struct gl_program * program);
#endif /* RADEON_MESA_TO_RC_H */

1
src/mesa/drivers/dri/r300/radeon_mipmap_tree.c
View file

@ -1 +0,0 @@
../radeon/radeon_mipmap_tree.c

1
src/mesa/drivers/dri/r300/radeon_mipmap_tree.h
View file

@ -1 +0,0 @@
../radeon/radeon_mipmap_tree.h

1
src/mesa/drivers/dri/r300/radeon_pixel_read.c
View file

@ -1 +0,0 @@
../radeon/radeon_pixel_read.c

1
src/mesa/drivers/dri/r300/radeon_queryobj.c
View file

@ -1 +0,0 @@
../radeon/radeon_queryobj.c

1
src/mesa/drivers/dri/r300/radeon_queryobj.h
View file

@ -1 +0,0 @@
../radeon/radeon_queryobj.h

1
src/mesa/drivers/dri/r300/radeon_screen.c
View file

@ -1 +0,0 @@
../radeon/radeon_screen.c

1
src/mesa/drivers/dri/r300/radeon_screen.h
View file

@ -1 +0,0 @@
../radeon/radeon_screen.h

1
src/mesa/drivers/dri/r300/radeon_span.c
View file

@ -1 +0,0 @@
../radeon/radeon_span.c

1
src/mesa/drivers/dri/r300/radeon_span.h
View file

@ -1 +0,0 @@
../radeon/radeon_span.h

1
src/mesa/drivers/dri/r300/radeon_tex_copy.c
View file

@ -1 +0,0 @@
../radeon/radeon_tex_copy.c

1
src/mesa/drivers/dri/r300/radeon_texture.c
View file

@ -1 +0,0 @@
../radeon/radeon_texture.c

1
src/mesa/drivers/dri/r300/radeon_texture.h
View file

@ -1 +0,0 @@
../radeon/radeon_texture.h

1
src/mesa/drivers/dri/r300/radeon_tile.c
View file

@ -1 +0,0 @@
../radeon/radeon_tile.c

1
src/mesa/drivers/dri/r300/radeon_tile.h
View file

@ -1 +0,0 @@
../radeon/radeon_tile.h

1
src/mesa/drivers/dri/r300/server/radeon.h
View file

@ -1 +0,0 @@
../../radeon/server/radeon.h

1
src/mesa/drivers/dri/r300/server/radeon_dri.h
View file

@ -1 +0,0 @@
../../radeon/server/radeon_dri.h

1
src/mesa/drivers/dri/r300/server/radeon_macros.h
View file

@ -1 +0,0 @@
../../radeon/server/radeon_macros.h

1
src/mesa/drivers/dri/r300/server/radeon_reg.h
View file

@ -1 +0,0 @@
../../radeon/server/radeon_reg.h

2
src/mesa/drivers/dri/r600/Lindent
View file

@ -1,2 +0,0 @@
#!/bin/sh
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs "$@"

77
src/mesa/drivers/dri/r600/Makefile
View file

@ -1,77 +0,0 @@
# src/mesa/drivers/dri/r300/Makefile
TOP = ../../../../..
include $(TOP)/configs/current
LIBNAME = r600_dri.so
include ../Makefile.defines
ifeq ($(RADEON_LDFLAGS),)
CS_SOURCES = radeon_cs_space_drm.c radeon_bo.c radeon_cs.c
endif
RADEON_COMMON_SOURCES = \
radeon_bo_legacy.c \
radeon_common_context.c \
radeon_buffer_objects.c \
radeon_common.c \
radeon_cs_legacy.c \
radeon_dma.c \
radeon_debug.c \
radeon_fbo.c \
radeon_lock.c \
radeon_mipmap_tree.c \
radeon_pixel_read.c \
radeon_queryobj.c \
radeon_span.c \
radeon_texture.c \
radeon_tex_copy.c \
radeon_tile.c
DRIVER_SOURCES = \
radeon_screen.c \
r600_context.c \
r600_cmdbuf.c \
r600_emit.c \
r700_assembler.c \
r700_fragprog.c \
r700_vertprog.c \
r700_shader.c \
r700_shaderinst.c \
r700_ioctl.c \
r700_oglprog.c \
r700_chip.c \
r700_state.c \
r700_clear.c \
r700_render.c \
r600_tex.c \
r600_texstate.c \
r600_blit.c \
r700_debug.c \
evergreen_context.c \
evergreen_state.c \
evergreen_tex.c \
evergreen_ioctl.c \
evergreen_render.c \
evergreen_chip.c \
evergreen_vertprog.c \
evergreen_fragprog.c \
evergreen_oglprog.c \
evergreen_blit.c \
$(RADEON_COMMON_SOURCES) \
$(EGL_SOURCES) \
$(CS_SOURCES)
C_SOURCES = $(COMMON_SOURCES) $(DRIVER_SOURCES)
DRIVER_DEFINES = -DRADEON_R600
# -DRADEON_BO_TRACK \
INCLUDES += $(RADEON_CFLAGS)
DRI_LIB_DEPS += $(RADEON_LDFLAGS)
##### TARGETS #####
include ../Makefile.targets

38
src/mesa/drivers/dri/r600/defaultendian.h
View file

@ -1,38 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _DEFINEENDIAN_H_
#define _DEFINEENDIAN_H_
//We have to choose a reg bits orientation if there is no compile flag for it.
#ifdef MESA_BIG_ENDIAN
#define BIGENDIAN_CPU
#else
#define LITTLEENDIAN_CPU
#endif
#endif //_DEFINEENDIAN_H_

2014
src/mesa/drivers/dri/r600/evergreen_blit.c
View file

File diff suppressed because it is too large Load diff

54
src/mesa/drivers/dri/r600/evergreen_blit.h
View file

@ -1,54 +0,0 @@
/*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef EVERGREEN_BLIT_H
#define EVERGREEN_BLIT_H
unsigned evergreen_check_blit(gl_format mesa_format);
unsigned evergreen_blit(struct gl_context *ctx,
struct radeon_bo *src_bo,
intptr_t src_offset,
gl_format src_mesaformat,
unsigned src_pitch,
unsigned src_width,
unsigned src_height,
unsigned src_x_offset,
unsigned src_y_offset,
struct radeon_bo *dst_bo,
intptr_t dst_offset,
gl_format dst_mesaformat,
unsigned dst_pitch,
unsigned dst_width,
unsigned dst_height,
unsigned dst_x_offset,
unsigned dst_y_offset,
unsigned w,
unsigned h,
unsigned flip_y);
#endif // EVERGREEN_BLIT_H

79
src/mesa/drivers/dri/r600/evergreen_blit_shaders.h
View file

@ -1,79 +0,0 @@
/*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
const uint32_t evergreen_vs[] =
{
0x00000004,
0x80800400,
0x0000a03c,
0x95000688,
0x00004000,
0x15200688,
0x00000000,
0x00000000,
0x3c000000,
0x67961001,
#ifdef MESA_BIG_ENDIAN
0x000a0000,
#else
0x00080000,
#endif
0x00000000,
0x1c000000,
0x67961000,
#ifdef MESA_BIG_ENDIAN
0x00020008,
#else
0x00000008,
#endif
0x00000000,
};
const uint32_t evergreen_ps[] =
{
0x00000003,
0xa00c0000,
0x00000008,
0x80400000,
0x00000000,
0x95200688,
0x00380400,
0x00146b10,
0x00380000,
0x20146b10,
0x00380400,
0x40146b00,
0x80380000,
0x60146b00,
0x00000000,
0x00000000,
0x00000010,
0x000d1000,
0xb0800000,
0x00000000,
};

1552
src/mesa/drivers/dri/r600/evergreen_chip.c
View file

File diff suppressed because it is too large Load diff

516
src/mesa/drivers/dri/r600/evergreen_chip.h
View file

@ -1,516 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_CHIP_H_
#define _EVERGREEN_CHIP_H_
#include "r700_chip.h"
#define EVERGREEN_MAX_DX9_CONSTS 256
#define EVERGREEN_MAX_SHADER_EXPORTS 32
#define EVERGREEN_MAX_VIEWPORTS 16
typedef struct _EVERGREEN_VIEWPORT_STATE
{
union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_TL; ////0,1 // = 0x28250, // DIFF
union UINT_FLOAT PA_SC_VPORT_SCISSOR_0_BR; ////0,1 // = 0x28254, // DIFF
union UINT_FLOAT PA_SC_VPORT_ZMIN_0; ////0 // = 0x282D0, // SAME
union UINT_FLOAT PA_SC_VPORT_ZMAX_0; ////0 // = 0x282D4, // SAME
union UINT_FLOAT PA_CL_VPORT_XSCALE; //// // = 0x2843C, // SAME
union UINT_FLOAT PA_CL_VPORT_XOFFSET; //// // = 0x28440, // SAME
union UINT_FLOAT PA_CL_VPORT_YSCALE; //// // = 0x28444, // SAME
union UINT_FLOAT PA_CL_VPORT_YOFFSET; //// // = 0x28448, // SAME
union UINT_FLOAT PA_CL_VPORT_ZSCALE; //// // = 0x2844C, // SAME
union UINT_FLOAT PA_CL_VPORT_ZOFFSET; //// // = 0x28450, // SAME
GLboolean enabled;
GLboolean dirty;
} EVERGREEN_VIEWPORT_STATE;
#define EVERGREEN_MAX_UCP 6
typedef struct _EVERGREEN_UCP_STATE
{
union UINT_FLOAT PA_CL_UCP_0_X; // = 0x285BC, // SAME 0x28E20
union UINT_FLOAT PA_CL_UCP_0_Y; // = 0x285C0, // SAME 0x28E24
union UINT_FLOAT PA_CL_UCP_0_Z; // = 0x285C4, // SAME 0x28E28
union UINT_FLOAT PA_CL_UCP_0_W; // = 0x285C8, // SAME 0x28E2C
GLboolean enabled;
GLboolean dirty;
} EVERGREEN_UCP_STATE;
#define EVERGREEN_MAX_RENDER_TARGETS 12
typedef struct _EVERGREEN_RENDER_TARGET_STATE
{
union UINT_FLOAT CB_COLOR0_BASE; ////0 // = 0x28C60, // SAME 0x28040
union UINT_FLOAT CB_COLOR0_PITCH; ////0 // = 0x28C64, //
union UINT_FLOAT CB_COLOR0_SLICE; ////0 // = 0x28C68, //
union UINT_FLOAT CB_COLOR0_VIEW; ////0 // = 0x28C6C, // SAME 0x28080
union UINT_FLOAT CB_COLOR0_INFO; ////0,1,2,3,4,5,6,78,9,10,11 // = 0x28C70, // DIFF 0x280A0
union UINT_FLOAT CB_COLOR0_ATTRIB; ////0 // = 0x28C74, //
union UINT_FLOAT CB_COLOR0_DIM; // = 0x28C78, //
union UINT_FLOAT CB_COLOR0_CMASK; ////0 // = 0x28C7C, //
union UINT_FLOAT CB_COLOR0_CMASK_SLICE; ////0 // = 0x28C80, //
union UINT_FLOAT CB_COLOR0_FMASK; ////0 // = 0x28C84, //
union UINT_FLOAT CB_COLOR0_FMASK_SLICE; ////0 // = 0x28C88, //
union UINT_FLOAT CB_COLOR0_CLEAR_WORD0; // = 0x28C8C, //
union UINT_FLOAT CB_COLOR0_CLEAR_WORD1; // = 0x28C90, //
union UINT_FLOAT CB_COLOR0_CLEAR_WORD2; // = 0x28C94, //
union UINT_FLOAT CB_COLOR0_CLEAR_WORD3; // = 0x28C98, //
GLboolean enabled;
GLboolean dirty;
} EVERGREEN_RENDER_TARGET_STATE;
typedef struct _EVERGREEN_CONFIG
{
union UINT_FLOAT SPI_CONFIG_CNTL; // = 0x9100, // DIFF
union UINT_FLOAT SPI_CONFIG_CNTL_1; // = 0x913C, // DIFF
union UINT_FLOAT CP_PERFMON_CNTL; // = 0x87FC, // SAME
union UINT_FLOAT SQ_MS_FIFO_SIZES; // = 0x8CF0, // SAME
union UINT_FLOAT SQ_CONFIG; // = 0x8C00, // DIFF
union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_1; // = 0x8C04, // SAME
union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_2; // = 0x8C08, // SAME
union UINT_FLOAT SQ_GPR_RESOURCE_MGMT_3; // = 0x8C0C, //
union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT; // = 0x8C18, // SAME 0x8C0C
union UINT_FLOAT SQ_THREAD_RESOURCE_MGMT_2; // = 0x8C1C, //
union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_1; // = 0x8C20, // SAME 0x8C10
union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_2; // = 0x8C24, // SAME 0x8C14
union UINT_FLOAT SQ_STACK_RESOURCE_MGMT_3; // = 0x8C28, //
union UINT_FLOAT SQ_DYN_GPR_CNTL_PS_FLUSH_REQ; // = 0x8D8C, // DIFF
union UINT_FLOAT SQ_LDS_RESOURCE_MGMT; // = 0x8E2C, //
union UINT_FLOAT VGT_CACHE_INVALIDATION; // = 0x88C4, // DIFF
union UINT_FLOAT VGT_GS_VERTEX_REUSE; // = 0x88D4, // SAME
union UINT_FLOAT PA_SC_FORCE_EOV_MAX_CNTS; // = 0x8B24, // SAME
union UINT_FLOAT PA_SC_LINE_STIPPLE_STATE; // = 0x8B10, // SAME
union UINT_FLOAT PA_CL_ENHANCE; // = 0x8A14, // SAME
} EVERGREEN_CONFIG;
typedef struct _EVERGREEN_PS_RES
{
union UINT_FLOAT SQ_PGM_START_PS; //// // = 0x28840, // SAME
GLboolean dirty;
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_0; // = 0x28940, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_1; // = 0x28944, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_2; // = 0x28948, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_3; // = 0x2894C, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_4; // = 0x28950, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_5; // = 0x28954, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_6; // = 0x28958, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_7; // = 0x2895C, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_8; // = 0x28960, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_9; // = 0x28964, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_10; // = 0x28968, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_11; // = 0x2896C, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_12; // = 0x28970, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_13; // = 0x28974, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_14; // = 0x28978, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_PS_15; // = 0x2897C, // SAME
int num_consts;
union UINT_FLOAT consts[EVERGREEN_MAX_DX9_CONSTS][4];
} EVERGREEN_PS_RES;
typedef struct _EVERGREEN_VS_RES
{
union UINT_FLOAT SQ_PGM_START_VS; //// // = 0x2885C, // SAME 0x28858
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_VS_0; //// // = 0x28180, //?
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_0; //// // = 0x28980, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_1; // = 0x28984, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_2; // = 0x28988, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_3; // = 0x2898C, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_4; // = 0x28990, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_5; // = 0x28994, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_6; // = 0x28998, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_7; // = 0x2899C, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_8; // = 0x289A0, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_9; // = 0x289A4, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_10; // = 0x289A8, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_11; // = 0x289AC, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_12; // = 0x289B0, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_13; // = 0x289B4, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_14; // = 0x289B8, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_VS_15; // = 0x289BC, // SAME
GLboolean dirty;
int num_consts;
union UINT_FLOAT consts[EVERGREEN_MAX_DX9_CONSTS][4];
} EVERGREEN_VS_RES;
typedef struct _EVERGREEN_CHIP_CONTEXT
{
/* Registers from PA block: */
union UINT_FLOAT PA_SC_SCREEN_SCISSOR_TL; //// // = 0x28030, // DIFF
union UINT_FLOAT PA_SC_SCREEN_SCISSOR_BR; //// // = 0x28034, // DIFF
union UINT_FLOAT PA_SC_WINDOW_OFFSET; //// // = 0x28200, // DIFF
union UINT_FLOAT PA_SC_WINDOW_SCISSOR_TL; //// // = 0x28204, // DIFF
union UINT_FLOAT PA_SC_WINDOW_SCISSOR_BR; //// // = 0x28208, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_RULE; //// // = 0x2820C, // SAME
union UINT_FLOAT PA_SC_CLIPRECT_0_TL; //// // = 0x28210, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_0_BR; //// // = 0x28214, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_1_TL; //// // = 0x28218, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_1_BR; //// // = 0x2821C, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_2_TL; //// // = 0x28220, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_2_BR; //// // = 0x28224, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_3_TL; //// // = 0x28228, // DIFF
union UINT_FLOAT PA_SC_CLIPRECT_3_BR; //// // = 0x2822C, // DIFF
union UINT_FLOAT PA_SC_EDGERULE; // = 0x28230, // SAME
union UINT_FLOAT PA_SU_HARDWARE_SCREEN_OFFSET; // = 0x28234, //
union UINT_FLOAT PA_SC_GENERIC_SCISSOR_TL; //// // = 0x28240, // DIFF
union UINT_FLOAT PA_SC_GENERIC_SCISSOR_BR; //// // = 0x28244, // DIFF
EVERGREEN_VIEWPORT_STATE viewport[EVERGREEN_MAX_VIEWPORTS];
EVERGREEN_UCP_STATE ucp[EVERGREEN_MAX_UCP];
union UINT_FLOAT PA_CL_POINT_X_RAD; // = 0x287D4, // SAME 0x28E10
union UINT_FLOAT PA_CL_POINT_Y_RAD; // = 0x287D8, // SAME 0x28E14
union UINT_FLOAT PA_CL_POINT_SIZE; // = 0x287DC, // SAME 0x28E18
union UINT_FLOAT PA_CL_POINT_CULL_RAD; // = 0x287E0, // SAME 0x28E1C
union UINT_FLOAT PA_CL_CLIP_CNTL; //// // = 0x28810, // SAME
union UINT_FLOAT PA_SU_SC_MODE_CNTL; //// // = 0x28814, // SAME
union UINT_FLOAT PA_CL_VTE_CNTL; //// // = 0x28818, // SAME
union UINT_FLOAT PA_CL_VS_OUT_CNTL; //// // = 0x2881C, // SAME
union UINT_FLOAT PA_CL_NANINF_CNTL; //// // = 0x28820, // SAME
union UINT_FLOAT PA_SU_LINE_STIPPLE_CNTL; // = 0x28824, //
union UINT_FLOAT PA_SU_LINE_STIPPLE_SCALE; // = 0x28828, //
union UINT_FLOAT PA_SU_PRIM_FILTER_CNTL; // = 0x2882C, //
union UINT_FLOAT PA_SU_POINT_SIZE; //// // = 0x28A00, // SAME
union UINT_FLOAT PA_SU_POINT_MINMAX; //// // = 0x28A04, // SAME
union UINT_FLOAT PA_SU_LINE_CNTL; //// // = 0x28A08, // SAME
union UINT_FLOAT PA_SC_LINE_STIPPLE; // = 0x28A0C, // SAME
union UINT_FLOAT PA_SC_MODE_CNTL_0; //// // = 0x28A48, //
union UINT_FLOAT PA_SC_MODE_CNTL_1; //// // = 0x28A4C, //
union UINT_FLOAT PA_SU_POLY_OFFSET_DB_FMT_CNTL; //// // = 0x28B78, // SAME 0x28DF8
union UINT_FLOAT PA_SU_POLY_OFFSET_CLAMP; //// // = 0x28B7C, // SAME 0x28DFC
union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_SCALE;//// // = 0x28B80, // SAME 0x28E00
union UINT_FLOAT PA_SU_POLY_OFFSET_FRONT_OFFSET; //// // = 0x28B84, // SAME 0x28E04
union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_SCALE; //// // = 0x28B88, // SAME 0x28E08
union UINT_FLOAT PA_SU_POLY_OFFSET_BACK_OFFSET; //// // = 0x28B8C, // SAME 0x28E0C
union UINT_FLOAT PA_SC_LINE_CNTL; //// // = 0x28C00, // DIFF
union UINT_FLOAT PA_SC_AA_CONFIG; //// // = 0x28C04, // SAME
union UINT_FLOAT PA_SU_VTX_CNTL; //// // = 0x28C08, // SAME
union UINT_FLOAT PA_CL_GB_VERT_CLIP_ADJ; //// // = 0x28C0C, // SAME
union UINT_FLOAT PA_CL_GB_VERT_DISC_ADJ; //// // = 0x28C10, // SAME
union UINT_FLOAT PA_CL_GB_HORZ_CLIP_ADJ; //// // = 0x28C14, // SAME
union UINT_FLOAT PA_CL_GB_HORZ_DISC_ADJ; //// // = 0x28C18, // SAME
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_0; //// // = 0x28C1C, //
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_1; //// // = 0x28C20, //
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_2; //// // = 0x28C24, //
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_3; //// // = 0x28C28, //
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_4; //// // = 0x28C2C, //
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_5; //// // = 0x28C30, //
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_6; //// // = 0x28C34, //
union UINT_FLOAT PA_SC_AA_SAMPLE_LOCS_7; //// // = 0x28C38, //
union UINT_FLOAT PA_SC_AA_MASK; //// // = 0x28C3C, // SAME 0x28C48
/* Registers from VGT block: */
union UINT_FLOAT VGT_INDEX_TYPE; // = 0x895C, // SAME
union UINT_FLOAT VGT_PRIMITIVE_TYPE; // = 0x8958, // SAME
union UINT_FLOAT VGT_MAX_VTX_INDX; //// // = 0x28400, // SAME
union UINT_FLOAT VGT_MIN_VTX_INDX; //// // = 0x28404, // SAME
union UINT_FLOAT VGT_INDX_OFFSET; //// // = 0x28408, // SAME
union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_INDX; // = 0x2840C, // SAME
union UINT_FLOAT VGT_DRAW_INITIATOR; // = 0x287F0, // SAME
union UINT_FLOAT VGT_IMMED_DATA; // = 0x287F4, // SAME
union UINT_FLOAT VGT_OUTPUT_PATH_CNTL; //// // = 0x28A10, // DIFF
union UINT_FLOAT VGT_HOS_CNTL; // = 0x28A14, // SAME
union UINT_FLOAT VGT_HOS_MAX_TESS_LEVEL; // = 0x28A18, // SAME
union UINT_FLOAT VGT_HOS_MIN_TESS_LEVEL; // = 0x28A1C, // SAME
union UINT_FLOAT VGT_HOS_REUSE_DEPTH; // = 0x28A20, // SAME
union UINT_FLOAT VGT_GROUP_PRIM_TYPE; // = 0x28A24, // SAME
union UINT_FLOAT VGT_GROUP_FIRST_DECR; // = 0x28A28, // SAME
union UINT_FLOAT VGT_GROUP_DECR; // = 0x28A2C, // SAME
union UINT_FLOAT VGT_GROUP_VECT_0_CNTL; // = 0x28A30, // SAME
union UINT_FLOAT VGT_GROUP_VECT_1_CNTL; // = 0x28A34, // SAME
union UINT_FLOAT VGT_GROUP_VECT_0_FMT_CNTL; // = 0x28A38, // SAME
union UINT_FLOAT VGT_GROUP_VECT_1_FMT_CNTL; // = 0x28A3C, // SAME
union UINT_FLOAT VGT_GS_MODE; //// // = 0x28A40, // DIFF
union UINT_FLOAT VGT_PRIMITIVEID_EN; //// // = 0x28A84, // SAME
union UINT_FLOAT VGT_DMA_NUM_INSTANCES; //// // = 0x28A88, // SAME
union UINT_FLOAT VGT_EVENT_INITIATOR; // = 0x28A90, // SAME
union UINT_FLOAT VGT_MULTI_PRIM_IB_RESET_EN; // = 0x28A94, // SAME
union UINT_FLOAT VGT_INSTANCE_STEP_RATE_0; //// // = 0x28AA0, // SAME
union UINT_FLOAT VGT_INSTANCE_STEP_RATE_1; //// // = 0x28AA4, // SAME
union UINT_FLOAT VGT_REUSE_OFF; //// // = 0x28AB4, // SAME
union UINT_FLOAT VGT_VTX_CNT_EN; //// // = 0x28AB8, // SAME
union UINT_FLOAT VGT_SHADER_STAGES_EN; //// // = 0x28B54, //
union UINT_FLOAT VGT_STRMOUT_CONFIG; //// // = 0x28B94, //
union UINT_FLOAT VGT_STRMOUT_BUFFER_CONFIG; //// // = 0x28B98, //
union UINT_FLOAT VGT_VERTEX_REUSE_BLOCK_CNTL;//// // = 0x28C58, // SAME
union UINT_FLOAT VGT_OUT_DEALLOC_CNTL; //// // = 0x28C5C, // SAME
/* Registers from SQ block: */
union UINT_FLOAT SQ_VTX_SEMANTIC_0; //// // = 0x28380, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_1; //// // = 0x28384, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_2; //// // = 0x28388, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_3; //// // = 0x2838C, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_4; //// // = 0x28390, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_5; //// // = 0x28394, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_6; //// // = 0x28398, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_7; //// // = 0x2839C, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_8; //// // = 0x283A0, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_9; //// // = 0x283A4, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_10; //// // = 0x283A8, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_11; //// // = 0x283AC, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_12; //// // = 0x283B0, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_13; //// // = 0x283B4, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_14; //// // = 0x283B8, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_15; //// // = 0x283BC, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_16; //// // = 0x283C0, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_17; //// // = 0x283C4, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_18; //// // = 0x283C8, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_19; //// // = 0x283CC, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_20; //// // = 0x283D0, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_21; //// // = 0x283D4, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_22; //// // = 0x283D8, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_23; //// // = 0x283DC, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_24; //// // = 0x283E0, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_25; //// // = 0x283E4, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_26; //// // = 0x283E8, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_27; //// // = 0x283EC, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_28; //// // = 0x283F0, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_29; //// // = 0x283F4, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_30; //// // = 0x283F8, // SAME
union UINT_FLOAT SQ_VTX_SEMANTIC_31; //// // = 0x283FC, // SAME
union UINT_FLOAT SQ_DYN_GPR_RESOURCE_LIMIT_1;//// // = 0x28838, //
union UINT_FLOAT SQ_PGM_RESOURCES_PS; //// // = 0x28844, // DIFF 0x28850
union UINT_FLOAT SQ_PGM_RESOURCES_2_PS; //// // = 0x28848, //
union UINT_FLOAT SQ_PGM_EXPORTS_PS; //// // = 0x2884C, // SAME 0x28854
union UINT_FLOAT SQ_PGM_RESOURCES_VS;//// // = 0x28860, // DIFF 0x28868
union UINT_FLOAT SQ_PGM_RESOURCES_2_VS; //// // = 0x28864, //
union UINT_FLOAT SQ_PGM_START_GS; //// // = 0x28874, // SAME 0x2886C
union UINT_FLOAT SQ_PGM_RESOURCES_GS; //// // = 0x28878, // DIFF 0x2887C
union UINT_FLOAT SQ_PGM_RESOURCES_2_GS; //// // = 0x2887C, //
union UINT_FLOAT SQ_PGM_START_ES; //// // = 0x2888C, // SAME 0x28880
union UINT_FLOAT SQ_PGM_RESOURCES_ES; //// // = 0x28890, // DIFF
union UINT_FLOAT SQ_PGM_RESOURCES_2_ES; //// // = 0x28894, //
union UINT_FLOAT SQ_PGM_START_FS; //// // = 0x288A4, // SAME 0x28894
union UINT_FLOAT SQ_PGM_RESOURCES_FS; //// // = 0x288A8, // DIFF 0x288A4
union UINT_FLOAT SQ_PGM_START_HS; // = 0x288B8, //
union UINT_FLOAT SQ_PGM_RESOURCES_HS; // = 0x288BC, //
union UINT_FLOAT SQ_PGM_RESOURCES_2_HS;//// // = 0x288C0, //
union UINT_FLOAT SQ_PGM_START_LS; // = 0x288D0, //
union UINT_FLOAT SQ_PGM_RESOURCES_LS; // = 0x288D4, //
union UINT_FLOAT SQ_PGM_RESOURCES_2_LS; //// // = 0x288D8, //
union UINT_FLOAT SQ_LDS_ALLOC_PS; //// // = 0x288EC, //
union UINT_FLOAT SQ_ESGS_RING_ITEMSIZE; //// // = 0x28900, // SAME 0x288A8
union UINT_FLOAT SQ_GSVS_RING_ITEMSIZE; //// // = 0x28904, // SAME 0x288AC
union UINT_FLOAT SQ_ESTMP_RING_ITEMSIZE; //// // = 0x28908, // SAME 0x288B0
union UINT_FLOAT SQ_GSTMP_RING_ITEMSIZE; //// // = 0x2890C, // SAME 0x288B4
union UINT_FLOAT SQ_VSTMP_RING_ITEMSIZE; //// // = 0x28910, // SAME 0x288B8
union UINT_FLOAT SQ_PSTMP_RING_ITEMSIZE; //// // = 0x28914, // SAME 0x288BC
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE; //// // = 0x2891C, // SAME 0x288C8
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_1; // = 0x28920, //
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_2; // = 0x28924, //
union UINT_FLOAT SQ_GS_VERT_ITEMSIZE_3; // = 0x28928, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_0; // = 0x289C0, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_1; // = 0x289C4, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_2; // = 0x289C8, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_3; // = 0x289CC, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_4; // = 0x289D0, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_5; // = 0x289D4, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_6; // = 0x289D8, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_7; // = 0x289DC, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_8; // = 0x289E0, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_9; // = 0x289E4, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_10; // = 0x289E8, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_11; // = 0x289EC, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_12; // = 0x289F0, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_13; // = 0x289F4, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_14; // = 0x289F8, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_GS_15; // = 0x289FC, // SAME
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_0; // = 0x28F00, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_1; // = 0x28F04, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_2; // = 0x28F08, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_3; // = 0x28F0C, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_4; // = 0x28F10, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_5; // = 0x28F14, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_6; // = 0x28F18, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_7; // = 0x28F1C, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_8; // = 0x28F20, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_9; // = 0x28F24, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_10; // = 0x28F28, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_11; // = 0x28F2C, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_12; // = 0x28F30, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_13; // = 0x28F34, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_14; // = 0x28F38, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_HS_15; // = 0x28F3C, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_0; // = 0x28F40, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_1; // = 0x28F44, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_2; // = 0x28F48, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_3; // = 0x28F4C, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_4; // = 0x28F50, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_5; // = 0x28F54, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_6; // = 0x28F58, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_7; // = 0x28F5C, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_8; // = 0x28F60, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_9; // = 0x28F64, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_10; // = 0x28F68, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_11; // = 0x28F6C, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_12; // = 0x28F70, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_13; // = 0x28F74, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_14; // = 0x28F78, //
union UINT_FLOAT SQ_ALU_CONST_CACHE_LS_15; // = 0x28F7C, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_0; // = 0x28F80, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_1; // = 0x28F84, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_2; // = 0x28F88, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_3; // = 0x28F8C, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_4; // = 0x28F90, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_5; // = 0x28F94, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_6; // = 0x28F98, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_7; // = 0x28F9C, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_8; // = 0x28FA0, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_9; // = 0x28FA4, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_10; // = 0x28FA8, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_11; // = 0x28FAC, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_12; // = 0x28FB0, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_13; // = 0x28FB4, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_14; // = 0x28FB8, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_HS_15; // = 0x28FBC, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_0; // = 0x28FC0, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_1; // = 0x28FC4, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_2; // = 0x28FC8, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_3; // = 0x28FCC, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_4; // = 0x28FD0, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_5; // = 0x28FD4, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_6; // = 0x28FD8, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_7; // = 0x28FDC, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_8; // = 0x28FE0, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_9; // = 0x28FE4, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_10; // = 0x28FE8, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_11; // = 0x28FEC, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_12; // = 0x28FF0, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_13; // = 0x28FF4, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_14; // = 0x28FF8, //
union UINT_FLOAT SQ_ALU_CONST_BUFFER_SIZE_LS_15; // = 0x28FFC, //
EVERGREEN_PS_RES ps;
EVERGREEN_VS_RES vs;
/* Registers from SPI block: */
union UINT_FLOAT SPI_VS_OUT_ID_0; //// // = 0x2861C, // SAME 0x28614
union UINT_FLOAT SPI_VS_OUT_ID_1; //// // = 0x28620, // SAME 0x28618
union UINT_FLOAT SPI_VS_OUT_ID_2; //// // = 0x28624, // SAME 0x2861C
union UINT_FLOAT SPI_VS_OUT_ID_3; //// // = 0x28628, // SAME 0x28620
union UINT_FLOAT SPI_VS_OUT_ID_4; //// // = 0x2862C, // SAME 0x28624
union UINT_FLOAT SPI_VS_OUT_ID_5; //// // = 0x28630, // SAME 0x28628
union UINT_FLOAT SPI_VS_OUT_ID_6; //// // = 0x28634, // SAME 0x2862C
union UINT_FLOAT SPI_VS_OUT_ID_7; //// // = 0x28638, // SAME 0x28630
union UINT_FLOAT SPI_VS_OUT_ID_8; //// // = 0x2863C, // SAME 0x28634
union UINT_FLOAT SPI_VS_OUT_ID_9; //// // = 0x28640, // SAME 0x28638
union UINT_FLOAT SPI_PS_INPUT_CNTL[32]; //// // = 0x28644, // SAME
union UINT_FLOAT SPI_VS_OUT_CONFIG; //// // = 0x286C4, // SAME
union UINT_FLOAT SPI_THREAD_GROUPING; //// // = 0x286C8, // DIFF
union UINT_FLOAT SPI_PS_IN_CONTROL_0; //// // = 0x286CC, // SAME
union UINT_FLOAT SPI_PS_IN_CONTROL_1; //// // = 0x286D0, // SAME
union UINT_FLOAT SPI_INTERP_CONTROL_0; //// // = 0x286D4, // SAME
union UINT_FLOAT SPI_INPUT_Z; //// // = 0x286D8, // SAME
union UINT_FLOAT SPI_FOG_CNTL; //// // = 0x286DC, // SAME
union UINT_FLOAT SPI_BARYC_CNTL; //// // = 0x286E0, //
union UINT_FLOAT SPI_PS_IN_CONTROL_2; //// // = 0x286E4, //
union UINT_FLOAT SPI_COMPUTE_INPUT_CNTL; // = 0x286E8, //
union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_X; // = 0x286EC, //
union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_Y; // = 0x286F0, //
union UINT_FLOAT SPI_COMPUTE_NUM_THREAD_Z; // = 0x286F4, //
/* Registers from SX block: */
union UINT_FLOAT SX_MISC; // = 0x28350, // SAME
union UINT_FLOAT SX_SURFACE_SYNC; // = 0x28354, // DIFF
union UINT_FLOAT SX_ALPHA_TEST_CONTROL; //// // = 0x28410, // SAME
union UINT_FLOAT SX_ALPHA_REF; // = 0x28438, // SAME
/* Registers from DB block: */
union UINT_FLOAT DB_RENDER_CONTROL; //// // = 0x28000, // DIFF 0x28D0C
union UINT_FLOAT DB_COUNT_CONTROL; //// // = 0x28004, //
union UINT_FLOAT DB_DEPTH_VIEW; //// // = 0x28008, // DIFF 0x28004
union UINT_FLOAT DB_RENDER_OVERRIDE; //// // = 0x2800C, // DIFF 0x28D10
union UINT_FLOAT DB_RENDER_OVERRIDE2; //// // = 0x28010, //
union UINT_FLOAT DB_HTILE_DATA_BASE; //// // = 0x28014, // SAME
union UINT_FLOAT DB_STENCIL_CLEAR; //// // = 0x28028, // SAME
union UINT_FLOAT DB_DEPTH_CLEAR; //// // = 0x2802C, // SAME
union UINT_FLOAT DB_Z_INFO; //// // = 0x28040, //
union UINT_FLOAT DB_STENCIL_INFO; //// // = 0x28044, //
union UINT_FLOAT DB_Z_READ_BASE; //// // = 0x28048, //
union UINT_FLOAT DB_STENCIL_READ_BASE;//// // = 0x2804C, //
union UINT_FLOAT DB_Z_WRITE_BASE; //// // = 0x28050, //
union UINT_FLOAT DB_STENCIL_WRITE_BASE; //// // = 0x28054, //
union UINT_FLOAT DB_DEPTH_SIZE; //// // = 0x28058, // DIFF 0x28000
union UINT_FLOAT DB_DEPTH_SLICE; //// // = 0x2805C, //
union UINT_FLOAT DB_STENCILREFMASK; // = 0x28430, // SAME
union UINT_FLOAT DB_STENCILREFMASK_BF; // = 0x28434, // SAME
union UINT_FLOAT DB_DEPTH_CONTROL; //// // = 0x28800, // SAME
union UINT_FLOAT DB_SHADER_CONTROL;//// // = 0x2880C, // DIFF
union UINT_FLOAT DB_HTILE_SURFACE; //// // = 0x28ABC, // SAME 0x28D24
union UINT_FLOAT DB_SRESULTS_COMPARE_STATE0; //// // = 0x28AC0, // SAME 0x28D28
union UINT_FLOAT DB_SRESULTS_COMPARE_STATE1; //// // = 0x28AC4, // SAME 0x28D2C
union UINT_FLOAT DB_PRELOAD_CONTROL; //// // = 0x28AC8, // SAME 0x28D30
union UINT_FLOAT DB_ALPHA_TO_MASK; //// // = 0x28B70, // SAME 0x28D44
/* Registers from CB block: */
union UINT_FLOAT CB_TARGET_MASK; //// // = 0x28238, // SAME
union UINT_FLOAT CB_SHADER_MASK; //// // = 0x2823C, // SAME
union UINT_FLOAT CB_BLEND_RED; //// // = 0x28414, // SAME
union UINT_FLOAT CB_BLEND_GREEN; //// // = 0x28418, // SAME
union UINT_FLOAT CB_BLEND_BLUE; //// // = 0x2841C, // SAME
union UINT_FLOAT CB_BLEND_ALPHA; //// // = 0x28420, // SAME
union UINT_FLOAT CB_BLEND0_CONTROL; //// // = 0x28780, // DIFF
union UINT_FLOAT CB_BLEND1_CONTROL; // = 0x28784, // DIFF
union UINT_FLOAT CB_BLEND2_CONTROL; // = 0x28788, // DIFF
union UINT_FLOAT CB_BLEND3_CONTROL; // = 0x2878C, // DIFF
union UINT_FLOAT CB_BLEND4_CONTROL; // = 0x28790, // DIFF
union UINT_FLOAT CB_BLEND5_CONTROL; // = 0x28794, // DIFF
union UINT_FLOAT CB_BLEND6_CONTROL; // = 0x28798, // DIFF
union UINT_FLOAT CB_BLEND7_CONTROL; // = 0x2879C, // DIFF
union UINT_FLOAT CB_COLOR_CONTROL; //// // = 0x28808, // DIFF
union UINT_FLOAT CB_CLRCMP_CONTROL; //// // = 0x28C40, // SAME 0x28C30
union UINT_FLOAT CB_CLRCMP_SRC; //// // = 0x28C44, // SAME 0x28C34
union UINT_FLOAT CB_CLRCMP_DST; //// // = 0x28C48, // SAME 0x28C38
union UINT_FLOAT CB_CLRCMP_MSK; //// // = 0x28C4C, // SAME 0x28C3C
EVERGREEN_RENDER_TARGET_STATE render_target[EVERGREEN_MAX_RENDER_TARGETS];
radeonTexObj* textures[R700_TEXTURE_NUMBERUNITS];
EVERGREEN_CONFIG evergreen_config;
GLboolean bEnablePerspective;
} EVERGREEN_CHIP_CONTEXT;
#endif /* _EVERGREEN_CHIP_H_ */

106
src/mesa/drivers/dri/r600/evergreen_context.c
View file

@ -1,106 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#include "main/glheader.h"
#include "main/api_arrayelt.h"
#include "main/context.h"
#include "main/simple_list.h"
#include "main/imports.h"
#include "main/bufferobj.h"
#include "main/texobj.h"
#include "radeon_common_context.h"
#include "evergreen_context.h"
#include "evergreen_state.h"
#include "evergreen_blit.h"
#include "r600_cmdbuf.h"
#include "radeon_queryobj.h"
static void evergreen_get_lock(radeonContextPtr rmesa)
{
drm_radeon_sarea_t *sarea = rmesa->sarea;
if (sarea->ctx_owner != rmesa->dri.hwContext) {
sarea->ctx_owner = rmesa->dri.hwContext;
if (!rmesa->radeonScreen->kernel_mm)
radeon_bo_legacy_texture_age(rmesa->radeonScreen->bom);
}
}
static void evergreen_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmesa)
{
/* please flush pipe do all pending work */
/* to be enabled */
}
static void evergreen_vtbl_pre_emit_atoms(radeonContextPtr radeon)
{
r700Start3D((context_t *)radeon);
}
static void evergreen_fallback(struct gl_context *ctx, GLuint bit, GLboolean mode)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
if (mode)
context->radeon.Fallback |= bit;
else
context->radeon.Fallback &= ~bit;
}
static void evergreen_emit_query_finish(radeonContextPtr radeon)
{
context_t *context = (context_t*) radeon;
BATCH_LOCALS(&context->radeon);
struct radeon_query_object *query = radeon->query.current;
BEGIN_BATCH_NO_AUTOSTATE(4 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_EVENT_WRITE, 2));
R600_OUT_BATCH(R600_EVENT_TYPE(ZPASS_DONE) | R600_EVENT_INDEX(1));
R600_OUT_BATCH(query->curr_offset + 8); /* hw writes qwords */
R600_OUT_BATCH(0x00000000);
R600_OUT_BATCH_RELOC(VGT_EVENT_INITIATOR, query->bo, 0, 0, RADEON_GEM_DOMAIN_GTT, 0);
END_BATCH();
assert(query->curr_offset < RADEON_QUERY_PAGE_SIZE);
query->emitted_begin = GL_FALSE;
}
void evergreen_init_vtbl(radeonContextPtr radeon)
{
radeon->vtbl.get_lock = evergreen_get_lock;
radeon->vtbl.update_viewport_offset = evergreenUpdateViewportOffset;
radeon->vtbl.emit_cs_header = evergreen_vtbl_emit_cs_header;
radeon->vtbl.swtcl_flush = NULL;
radeon->vtbl.pre_emit_atoms = evergreen_vtbl_pre_emit_atoms;
radeon->vtbl.fallback = evergreen_fallback;
radeon->vtbl.emit_query_finish = evergreen_emit_query_finish;
radeon->vtbl.check_blit = evergreen_check_blit;
radeon->vtbl.blit = evergreen_blit;
radeon->vtbl.is_format_renderable = r600IsFormatRenderable;
}

38
src/mesa/drivers/dri/r600/evergreen_context.h
View file

@ -1,38 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_CONTEXT_H_
#define _EVERGREEN_CONTEXT_H_
extern void evergreen_init_vtbl(radeonContextPtr radeon);
#endif //_EVERGREEN_CONTEXT_H_

335
src/mesa/drivers/dri/r600/evergreen_diff.h
View file

@ -1,335 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_DIFF_H_
#define _EVERGREEN_DIFF_H_
enum {
/* CB_BLEND_CONTROL */
EG_CB_BLENDX_CONTROL_ENABLE_bit = 1 << 30,
/* PA_SC_SCREEN_SCISSOR_TL */
EG_PA_SC_SCREEN_SCISSOR_TL__TL_X_mask = 0xffff << 0,
EG_PA_SC_SCREEN_SCISSOR_TL__TL_Y_mask = 0xffff << 16,
/* PA_SC_SCREEN_SCISSOR_BR */
EG_PA_SC_SCREEN_SCISSOR_BR__BR_X_mask = 0xffff << 0,
EG_PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask = 0xffff << 16,
/* PA_SC_WINDOW_SCISSOR_TL */
EG_PA_SC_WINDOW_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
EG_PA_SC_WINDOW_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
/* PA_SC_WINDOW_SCISSOR_BR */
EG_PA_SC_WINDOW_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
EG_PA_SC_WINDOW_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
/* PA_SC_CLIPRECT_0_TL */
EG_PA_SC_CLIPRECT_0_TL__TL_X_mask = 0x7fff << 0,
EG_PA_SC_CLIPRECT_0_TL__TL_Y_mask = 0x7fff << 16,
/* PA_SC_CLIPRECT_0_BR */
EG_PA_SC_CLIPRECT_0_BR__BR_X_mask = 0x7fff << 0,
EG_PA_SC_CLIPRECT_0_BR__BR_Y_mask = 0x7fff << 16,
/* PA_SC_GENERIC_SCISSOR_TL */
EG_PA_SC_GENERIC_SCISSOR_TL__TL_X_mask = 0x7fff << 0,
EG_PA_SC_GENERIC_SCISSOR_TL__TL_Y_mask = 0x7fff << 16,
/* PA_SC_GENERIC_SCISSOR_BR */
EG_PA_SC_GENERIC_SCISSOR_BR__BR_X_mask = 0x7fff << 0,
EG_PA_SC_GENERIC_SCISSOR_BR__BR_Y_mask = 0x7fff << 16,
/* PA_SC_VPORT_SCISSOR_0_TL */
EG_PA_SC_VPORT_SCISSOR_0_TL__TL_X_mask = 0x7fff << 0,
EG_PA_SC_VPORT_SCISSOR_0_TL__TL_Y_mask = 0x7fff << 16,
/* PA_SC_VPORT_SCISSOR_0_BR */
EG_PA_SC_VPORT_SCISSOR_0_BR__BR_X_mask = 0x7fff << 0,
EG_PA_SC_VPORT_SCISSOR_0_BR__BR_Y_mask = 0x7fff << 16,
/* PA_SC_WINDOW_OFFSET */
EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_shift = 0,
EG_PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_mask = 0xffff << 0,
EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_shift = 16,
EG_PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_mask = 0xffff << 16,
/* SPI_BARYC_CNTL */
EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_shift = 4,
EG_SPI_BARYC_CNTL__PERSP_CENTROID_ENA_mask = 0x3 << 4,
EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_shift = 20,
EG_SPI_BARYC_CNTL__LINEAR_CENTROID_ENA_mask = 0x3 << 20,
/* DB_SHADER_CONTROL */
EG_DB_SHADER_CONTROL__DUAL_EXPORT_ENABLE_bit = 1 << 9,
/* DB_Z_INFO */
EG_DB_Z_INFO__FORMAT_shift = 0, //2;
EG_DB_Z_INFO__FORMAT_mask = 0x3,
//2;
EG_DB_Z_INFO__ARRAY_MODE_shift = 4, //4;
EG_DB_Z_INFO__ARRAY_MODE_mask = 0xf << 4,
EG_DB_Z_INFO__TILE_SPLIT_shift = 8, //3;
EG_DB_Z_INFO__TILE_SPLIT_mask = 0x7 << 8,
//1;
EG_DB_Z_INFO__NUM_BANKS_shift = 12, //2;
EG_DB_Z_INFO__NUM_BANKS_mask = 0x3 << 12,
//2;
EG_DB_Z_INFO__BANK_WIDTH_shift = 16, //2;
EG_DB_Z_INFO__BANK_WIDTH_mask = 0x3 << 16,
//2;
EG_DB_Z_INFO__BANK_HEIGHT_shift = 20, //2;
EG_DB_Z_INFO__BANK_HEIGHT_mask = 0x3 << 20,
EG_Z_INVALID = 0x00000000,
EG_Z_16 = 0x00000001,
EG_Z_24 = 0x00000002,
EG_Z_32_FLOAT = 0x00000003,
EG_ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
EG_ADDR_SURF_8_BANK = 0x00000002,
EG_ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
EG_ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
/* DB_STENCIL_INFO */
EG_DB_STENCIL_INFO__FORMAT_bit = 1, //1;
//7;
EG_DB_STENCIL_INFO__TILE_SPLIT_shift = 8, //3;
EG_DB_STENCIL_INFO__TILE_SPLIT_mask = 0x7 << 8,
/* DB_DEPTH_SIZE */
EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_shift = 0, // 11;
EG_DB_DEPTH_SIZE__PITCH_TILE_MAX_mask = 0x7ff,
EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_shift = 11, // 11;
EG_DB_DEPTH_SIZE__HEIGHT_TILE_MAX_mask = 0x7ff << 11,
/* DB_COUNT_CONTROL */
EG_DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_shift = 0, //1
EG_DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_bit = 1,
EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_shift = 1, //1
EG_DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_bit = 1 << 1,
/* CB_COLOR_CONTROL */
//3;
EG_CB_COLOR_CONTROL__DEGAMMA_ENABLE_bit = 1 << 3,//1;
EG_CB_COLOR_CONTROL__MODE_shift = 4, //3;
EG_CB_COLOR_CONTROL__MODE_mask = 0x7 << 4,
//9;
EG_CB_COLOR_CONTROL__ROP3_shift = 16, //8;
EG_CB_COLOR_CONTROL__ROP3_mask = 0xff << 16,
EG_CB_NORMAL = 0x00000001,
/* CB_COLOR0_INFO */
EG_CB_COLOR0_INFO__ENDIAN_shift = 0, //2;
EG_CB_COLOR0_INFO__ENDIAN_mask = 0x3,
EG_CB_COLOR0_INFO__FORMAT_shift = 2, //6;
EG_CB_COLOR0_INFO__FORMAT_mask = 0x3f << 2,
EG_CB_COLOR0_INFO__ARRAY_MODE_shift = 8, //4;
EG_CB_COLOR0_INFO__ARRAY_MODE_mask = 0xf << 8,
EG_CB_COLOR0_INFO__NUMBER_TYPE_shift = 12, //3;
EG_CB_COLOR0_INFO__NUMBER_TYPE_mask = 0x7 << 12,
EG_CB_COLOR0_INFO__COMP_SWAP_shift = 15, //2;
EG_CB_COLOR0_INFO__COMP_SWAP_mask = 0x3 << 15,
EG_CB_COLOR0_INFO__FAST_CLEAR_bit = 1 << 17,//1;
EG_CB_COLOR0_INFO__COMPRESSION_bit = 1 << 18,//1;
EG_CB_COLOR0_INFO__BLEND_CLAMP_bit = 1 << 19,//1;
EG_CB_COLOR0_INFO__BLEND_BYPASS_bit = 1 << 20,//1;
EG_CB_COLOR0_INFO__SIMPLE_FLOAT_bit = 1 << 21,//1;
EG_CB_COLOR0_INFO__ROUND_MODE_bit = 1 << 22,//1;
EG_CB_COLOR0_INFO__TILE_COMPACT_bit = 1 << 23,//1;
EG_CB_COLOR0_INFO__SOURCE_FORMAT_shift = 24, //2;
EG_CB_COLOR0_INFO__SOURCE_FORMAT_mask = 0x3 << 24,
EG_CB_COLOR0_INFO__RAT_bit = 1 << 26,//1;
EG_CB_COLOR0_INFO__RESOURCE_TYPE_shift = 27, //3;
EG_CB_COLOR0_INFO__RESOURCE_TYPE_mask = 0x7 << 27,
/* CB_COLOR0_ATTRIB */
EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_shift = 4,
EG_CB_COLOR0_ATTRIB__NON_DISP_TILING_ORDER_bit = 1 << 4,
/* SPI_CONFIG_CNTL_1 */
EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_shift = 0,
EG_SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_mask = 0xf,
/* SQ_MS_FIFO_SIZES */
EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_shift = 0,
EG_SQ_MS_FIFO_SIZES__CACHE_FIFO_SIZE_mask = 0xff,
EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_shift = 8,
EG_SQ_MS_FIFO_SIZES__FETCH_FIFO_HIWATER_mask = 0x1f << 8,
EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_shift = 16,
EG_SQ_MS_FIFO_SIZES__DONE_FIFO_HIWATER_mask = 0xff << 16,
EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_shift = 24,
EG_SQ_MS_FIFO_SIZES__ALU_UPDATE_FIFO_HIWATER_mask = 0x1f << 24,
/* SQ_CONFIG */
EG_SQ_CONFIG__VC_ENABLE_bit = 1,
EG_SQ_CONFIG__EXPORT_SRC_C_bit = 1 << 1,
EG_SQ_CONFIG__PS_PRIO_shift = 24,
EG_SQ_CONFIG__PS_PRIO_mask = 0x3 << 24,
EG_SQ_CONFIG__VS_PRIO_shift = 26,
EG_SQ_CONFIG__VS_PRIO_mask = 0x3 << 26,
EG_SQ_CONFIG__GS_PRIO_shift = 28,
EG_SQ_CONFIG__GS_PRIO_mask = 0x3 << 28,
EG_SQ_CONFIG__ES_PRIO_shift = 30,
EG_SQ_CONFIG__ES_PRIO_mask = 0x3 << 30,
/* PA_SC_FORCE_EOV_MAX_CNTS */
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_shift = 0,
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_mask = 0x3fff,
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_shift = 16,
EG_PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_mask = 0x3fff << 16,
/* VGT_CACHE_INVALIDATION */
EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_shift = 0,
EG_VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_mask = 0x3,
/* CB_COLOR0_PITCH */
EG_CB_COLOR0_PITCH__TILE_MAX_shift = 0,
EG_CB_COLOR0_PITCH__TILE_MAX_mask = 0x7ff,
/* CB_COLOR0_SLICE */
EG_CB_COLOR0_SLICE__TILE_MAX_shift = 0,
EG_CB_COLOR0_SLICE__TILE_MAX_mask = 0x3fffff,
/* SQ_VTX_CONSTANT_WORD3_0 */
EG_SQ_VTX_CONSTANT_WORD3_0__UNCACHED_shift = 2,
EG_SQ_VTX_CONSTANT_WORD3_0__UNCACHED_bit = 1 << 2,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_shift = 3,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_X_mask = 0x7 << 3,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_shift = 6,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Y_mask = 0x7 << 6,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_shift = 9,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_Z_mask = 0x7 << 9,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_shift = 12,
EG_SQ_VTX_CONSTANT_WORD3_0__DST_SEL_W_mask = 0x7 << 12,
/* SQ_VTX_CONSTANT_WORD4_0 */
EG_SQ_VTX_CONSTANT_WORD4_0__NUM_ELEMENTS_shift = 0,
EG_SQ_VTX_CONSTANT_WORD4_0__NUM_ELEMENTS_mask = 0xFFFFFFFF,
/* SQ_VTX_CONSTANT_WORD7_0 */
EG_SQ_VTX_CONSTANT_WORD7_0__TYPE_shift = 30,
EG_SQ_VTX_CONSTANT_WORD7_0__TYPE_mask = 0x3 << 30,
/* SQ_TEX_SAMPLER_WORD0_0 */
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_shift = 0, // 3;
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_X_mask = 0x7,
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_shift = 3, // 3;
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Y_mask = 0x7 << 3,
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_shift = 6, // 3;
EG_SQ_TEX_SAMPLER_WORD0_0__CLAMP_Z_mask = 0x7 << 6,
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_shift = 9, // 2;
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MAG_FILTER_mask = 0x3 << 9,
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_shift = 11, // 2;
EG_SQ_TEX_SAMPLER_WORD0_0__XY_MIN_FILTER_mask = 0x3 << 11,
EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_shift = 13, // 2;
EG_SQ_TEX_SAMPLER_WORD0_0__Z_FILTER_mask = 0x3 << 13,
EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_shift = 15, // 2;
EG_SQ_TEX_SAMPLER_WORD0_0__MIP_FILTER_mask = 0x3 << 15,
EG_SQ_TEX_SAMPLER_WORD0_0__MAX_ANISO_RATIO_shift = 17, // 3;
EG_SQ_TEX_SAMPLER_WORD0_0__MAX_ANISO_RATIO_mask = 0x7 << 17,
EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_shift = 20,//2;
EG_SQ_TEX_SAMPLER_WORD0_0__BORDER_COLOR_TYPE_mask = 0x3 << 20,
EG_SQ_TEX_SAMPLER_WORD0_0__DCF_shift = 22, // 3;
EG_SQ_TEX_SAMPLER_WORD0_0__DCF_mask = 0x7 << 22,
EG_SQ_TEX_SAMPLER_WORD0_0__CHROMA_KEY_shift = 25, // 2;
EG_SQ_TEX_SAMPLER_WORD0_0__CHROMA_KEY_mask = 0x3 << 25,
EG_SQ_TEX_SAMPLER_WORD0_0__ANISO_THRESHOLD_shift = 27, // 3;
EG_SQ_TEX_SAMPLER_WORD0_0__ANISO_THRESHOLD_mask = 0x7 << 27,
EG_SQ_TEX_SAMPLER_WORD0_0__Reserved_shift = 30, // 2
EG_SQ_TEX_SAMPLER_WORD0_0__Reserved_mask = 0x3 << 30,
/* SQ_TEX_SAMPLER_WORD1_0 */
EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_shift = 0, // 12;
EG_SQ_TEX_SAMPLER_WORD1_0__MIN_LOD_mask = 0xfff,
EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_shift = 12,// 12;
EG_SQ_TEX_SAMPLER_WORD1_0__MAX_LOD_mask = 0xfff << 12,
/* SQ_TEX_SAMPLER_WORD2_0 */
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_shift = 0, //14;
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_mask = 0x3fff,
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC_shift = 14,//6;
EG_SQ_TEX_SAMPLER_WORD2_0__LOD_BIAS_SEC_mask = 0x3f << 14,
EG_SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE_shift = 20,//1;
EG_SQ_TEX_SAMPLER_WORD2_0__MC_COORD_TRUNCATE_bit = 1 << 20,
EG_SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_shift = 21,//1;
EG_SQ_TEX_SAMPLER_WORD2_0__FORCE_DEGAMMA_bit = 1 << 21,
EG_SQ_TEX_SAMPLER_WORD2_0__ANISO_BIAS_shift = 22,//6;
EG_SQ_TEX_SAMPLER_WORD2_0__ANISO_BIAS_mask = 0x3f << 22,
EG_SQ_TEX_SAMPLER_WORD2_0__TRUNCATE_COORD_shift = 28,//1;
EG_SQ_TEX_SAMPLER_WORD2_0__TRUNCATE_COORD_bit = 1 << 28,
EG_SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_shift = 29,//1;
EG_SQ_TEX_SAMPLER_WORD2_0__DISABLE_CUBE_WRAP_bit = 1 << 29,
EG_SQ_TEX_SAMPLER_WORD2_0__Reserved_shift = 30,//1;
EG_SQ_TEX_SAMPLER_WORD2_0__Reserved_bit = 1 << 30,
EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_shift = 31,//1;
EG_SQ_TEX_SAMPLER_WORD2_0__TYPE_bit = 1 << 31,
/* SQ_TEX_RESOURCE_WORD0_0 */
EG_SQ_TEX_RESOURCE_WORD0_0__DIM_shift = 0, // 3;
EG_SQ_TEX_RESOURCE_WORD0_0__DIM_mask = 0x7,
EG_SQ_TEX_RESOURCE_WORD0_0__ISET_shift = 3, // 1;
EG_SQ_TEX_RESOURCE_WORD0_0__ISET_bit = 1 << 3,
EG_SQ_TEX_RESOURCE_WORD0_0__Reserve_shift = 4, // 1;
EG_SQ_TEX_RESOURCE_WORD0_0__Reserve_bit = 1 << 4,
EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_shift = 5, // 1;
EG_SQ_TEX_RESOURCE_WORD0_0__NDTO_bit = 1 << 5,
EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_shift = 6, // 12;
EG_SQ_TEX_RESOURCE_WORD0_0__PITCH_mask = 0xfff << 6,
EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_shift = 18,// 14;
EG_SQ_TEX_RESOURCE_WORD0_0__TEX_WIDTH_mask = 0x3fff << 18,
/* SQ_TEX_RESOURCE_WORD1_0 */
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_shift = 0, // 14;
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_HEIGHT_mask = 0x3fff,
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_shift = 14,// 13;
EG_SQ_TEX_RESOURCE_WORD1_0__TEX_DEPTH_mask = 0x1fff << 14,
EG_SQ_TEX_RESOURCE_WORD1_0__Reserved_shift = 27,// 1;
EG_SQ_TEX_RESOURCE_WORD1_0__Reserved_bit = 1 << 27,
EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_shift = 28,// 4;
EG_SQ_TEX_RESOURCE_WORD1_0__ARRAY_MODE_mask = 0xf << 28,
/* SQ_TEX_RESOURCE_WORD6_0 */
EG_SQ_TEX_RESOURCE_WORD6_0__MAX_ANISO_RATIO_shift = 0, //: 3;
EG_SQ_TEX_RESOURCE_WORD6_0__MAX_ANISO_RATIO_mask = 0x7,
EG_SQ_TEX_RESOURCE_WORD6_0__INTERLACED_shift = 6, //1;
EG_SQ_TEX_RESOURCE_WORD6_0__INTERLACED_bit = 1 << 6,
EG_SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_shift = 8, //12;
EG_SQ_TEX_RESOURCE_WORD6_0__MIN_LOD_mask = 0xfff << 8,
EG_SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_shift = 29,// 3;
EG_SQ_TEX_RESOURCE_WORD6_0__TILE_SPLIT_mask = 0x7 << 29,
/* SQ_TEX_RESOURCE_WORD7_0 */
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_shift = 0, // 6;
EG_SQ_TEX_RESOURCE_WORD7_0__DATA_FORMAT_mask = 0x3f,
EG_SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_shift = 6, // 2;
EG_SQ_TEX_RESOURCE_WORD7_0__MACRO_TILE_ASPECT_mask = 0x3 << 6,
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_shift = 8, // 2;
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_WIDTH_mask = 0x3 << 8,
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_shift = 10,// 2;
EG_SQ_TEX_RESOURCE_WORD7_0__BANK_HEIGHT_mask = 0x3 << 10,
EG_SQ_TEX_RESOURCE_WORD7_0__DEPTH_SAMPLE_ORDER_shift = 15,// 1;
EG_SQ_TEX_RESOURCE_WORD7_0__DEPTH_SAMPLE_ORDER_bit = 1 << 15,
EG_SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_shift = 16,// 2;
EG_SQ_TEX_RESOURCE_WORD7_0__NUM_BANKS_mask = 0x3 << 16,
EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_shift = 30,// 2;
EG_SQ_TEX_RESOURCE_WORD7_0__TYPE_mask = 0x3 << 30,
};
/* */
#define EG_SQ_FETCH_RESOURCE_COUNT 0x00000400
#define EG_SQ_TEX_SAMPLER_COUNT 0x0000006c
#define EG_SQ_LOOP_CONST_COUNT 0x000000c0
#define EG_SET_RESOURCE_OFFSET 0x30000
#define EG_SET_RESOURCE_END 0x30400 //r600 := offset + 0x4000
#define EG_SET_LOOP_CONST_OFFSET 0x3A200
#define EG_SET_LOOP_CONST_END 0x3A26C //r600 := offset + 0x180
#define EG_SQ_FETCH_RESOURCE_VS_OFFSET 0x000000b0
#define EG_FETCH_RESOURCE_STRIDE 8
#define EG_SET_BOOL_CONST_OFFSET 0x3A500
#define EG_SET_BOOL_CONST_END 0x3A506
#endif //_EVERGREEN_DIFF_H_

802
src/mesa/drivers/dri/r600/evergreen_fragprog.c
View file

@ -1,802 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
* CooperYuan <cooper.yuan@amd.com>, <cooperyuan@gmail.com>
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include "main/imports.h"
#include "program/prog_parameter.h"
#include "program/prog_statevars.h"
#include "program/program.h"
#include "r600_context.h"
#include "r600_cmdbuf.h"
#include "r600_emit.h"
#include "evergreen_vertprog.h"
#include "evergreen_fragprog.h"
void evergreen_insert_wpos_code(struct gl_context *ctx, struct gl_fragment_program *fprog)
{
static const gl_state_index winstate[STATE_LENGTH]
= { STATE_INTERNAL, STATE_FB_SIZE, 0, 0, 0};
struct prog_instruction *newInst, *inst;
GLint win_size; /* state reference */
GLuint wpos_temp; /* temp register */
int i, j;
/* PARAM win_size = STATE_FB_SIZE */
win_size = _mesa_add_state_reference(fprog->Base.Parameters, winstate);
wpos_temp = fprog->Base.NumTemporaries++;
/* scan program where WPOS is used and replace with wpos_temp */
inst = fprog->Base.Instructions;
for (i = 0; i < fprog->Base.NumInstructions; i++) {
for (j=0; j < 3; j++) {
if(inst->SrcReg[j].File == PROGRAM_INPUT &&
inst->SrcReg[j].Index == FRAG_ATTRIB_WPOS) {
inst->SrcReg[j].File = PROGRAM_TEMPORARY;
inst->SrcReg[j].Index = wpos_temp;
}
}
inst++;
}
_mesa_insert_instructions(&(fprog->Base), 0, 1);
newInst = fprog->Base.Instructions;
/* invert wpos.y
* wpos_temp.xyzw = wpos.x-yzw + winsize.0y00 */
newInst[0].Opcode = OPCODE_ADD;
newInst[0].DstReg.File = PROGRAM_TEMPORARY;
newInst[0].DstReg.Index = wpos_temp;
newInst[0].DstReg.WriteMask = WRITEMASK_XYZW;
newInst[0].SrcReg[0].File = PROGRAM_INPUT;
newInst[0].SrcReg[0].Index = FRAG_ATTRIB_WPOS;
newInst[0].SrcReg[0].Swizzle = SWIZZLE_XYZW;
newInst[0].SrcReg[0].Negate = NEGATE_Y;
newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR;
newInst[0].SrcReg[1].Index = win_size;
newInst[0].SrcReg[1].Swizzle = MAKE_SWIZZLE4(SWIZZLE_ZERO, SWIZZLE_Y, SWIZZLE_ZERO, SWIZZLE_ZERO);
}
//TODO : Validate FP input with VP output.
void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm,
struct gl_fragment_program *mesa_fp,
struct gl_context *ctx)
{
unsigned int unBit;
unsigned int i;
/* match fp inputs with vp exports. */
struct evergreen_vertex_program_cont *vpc =
(struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
pAsm->number_used_registers = 0;
//Input mapping : mesa_fp->Base.InputsRead set the flag, set in
//The flags parsed in parse_attrib_binding. FRAG_ATTRIB_COLx, FRAG_ATTRIB_TEXx, ...
//MUST match order in Map_Vertex_Output
unBit = 1 << FRAG_ATTRIB_WPOS;
if(mesa_fp->Base.InputsRead & unBit)
{
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS] = pAsm->number_used_registers++;
}
unBit = 1 << VERT_RESULT_COL0;
if(OutputsWritten & unBit)
{
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0] = pAsm->number_used_registers++;
}
unBit = 1 << VERT_RESULT_COL1;
if(OutputsWritten & unBit)
{
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1] = pAsm->number_used_registers++;
}
unBit = 1 << VERT_RESULT_FOGC;
if(OutputsWritten & unBit)
{
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC] = pAsm->number_used_registers++;
}
for(i=0; i<8; i++)
{
unBit = 1 << (VERT_RESULT_TEX0 + i);
if(OutputsWritten & unBit)
{
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i] = pAsm->number_used_registers++;
}
}
/* order has been taken care of */
#if 1
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
{
unBit = 1 << i;
if(OutputsWritten & unBit)
{
pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0] = pAsm->number_used_registers++;
}
}
#else
if( (mesa_fp->Base.InputsRead >> FRAG_ATTRIB_VAR0) > 0 )
{
struct evergreen_vertex_program_cont *vpc =
(struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
struct gl_program_parameter_list * VsVarying = vpc->mesa_program.Base.Varying;
struct gl_program_parameter_list * PsVarying = mesa_fp->Base.Varying;
struct gl_program_parameter * pVsParam;
struct gl_program_parameter * pPsParam;
GLuint j, k;
GLuint unMaxVarying = 0;
for(i=0; i<VsVarying->NumParameters; i++)
{
pAsm->uiFP_AttributeMap[i + FRAG_ATTRIB_VAR0] = 0;
}
for(i=FRAG_ATTRIB_VAR0; i<FRAG_ATTRIB_MAX; i++)
{
unBit = 1 << i;
if(mesa_fp->Base.InputsRead & unBit)
{
j = i - FRAG_ATTRIB_VAR0;
pPsParam = PsVarying->Parameters + j;
for(k=0; k<VsVarying->NumParameters; k++)
{
pVsParam = VsVarying->Parameters + k;
if( strcmp(pPsParam->Name, pVsParam->Name) == 0)
{
pAsm->uiFP_AttributeMap[i] = pAsm->number_used_registers + k;
if(k > unMaxVarying)
{
unMaxVarying = k;
}
break;
}
}
}
}
pAsm->number_used_registers += unMaxVarying + 1;
}
#endif
unBit = 1 << FRAG_ATTRIB_FACE;
if(mesa_fp->Base.InputsRead & unBit)
{
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE] = pAsm->number_used_registers++;
}
unBit = 1 << FRAG_ATTRIB_PNTC;
if(mesa_fp->Base.InputsRead & unBit)
{
pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC] = pAsm->number_used_registers++;
}
pAsm->uIIns = pAsm->number_used_registers;
/* Map temporary registers (GPRs) */
pAsm->starting_temp_register_number = pAsm->number_used_registers;
if(mesa_fp->Base.NumNativeTemporaries >= mesa_fp->Base.NumTemporaries)
{
pAsm->number_used_registers += mesa_fp->Base.NumNativeTemporaries;
}
else
{
pAsm->number_used_registers += mesa_fp->Base.NumTemporaries;
}
/* Output mapping */
pAsm->number_of_exports = 0;
pAsm->number_of_colorandz_exports = 0; /* don't include stencil and mask out. */
pAsm->starting_export_register_number = pAsm->number_used_registers;
unBit = 1 << FRAG_RESULT_COLOR;
if(mesa_fp->Base.OutputsWritten & unBit)
{
pAsm->uiFP_OutputMap[FRAG_RESULT_COLOR] = pAsm->number_used_registers++;
pAsm->number_of_exports++;
pAsm->number_of_colorandz_exports++;
}
unBit = 1 << FRAG_RESULT_DEPTH;
if(mesa_fp->Base.OutputsWritten & unBit)
{
pAsm->depth_export_register_number = pAsm->number_used_registers;
pAsm->uiFP_OutputMap[FRAG_RESULT_DEPTH] = pAsm->number_used_registers++;
pAsm->number_of_exports++;
pAsm->number_of_colorandz_exports++;
pAsm->pR700Shader->depthIsExported = 1;
}
pAsm->flag_reg_index = pAsm->number_used_registers++;
pAsm->uFirstHelpReg = pAsm->number_used_registers;
}
GLboolean evergreen_Find_Instruction_Dependencies_fp(struct evergreen_fragment_program *fp,
struct gl_fragment_program *mesa_fp)
{
GLuint i, j;
GLint * puiTEMPwrites;
GLint * puiTEMPreads;
struct prog_instruction * pILInst;
InstDeps *pInstDeps;
struct prog_instruction * texcoord_DepInst;
GLint nDepInstID;
puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
puiTEMPreads = (GLint*) MALLOC(sizeof(GLuint)*mesa_fp->Base.NumTemporaries);
for(i=0; i<mesa_fp->Base.NumTemporaries; i++)
{
puiTEMPwrites[i] = -1;
puiTEMPreads[i] = -1;
}
pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_fp->Base.NumInstructions);
for(i=0; i<mesa_fp->Base.NumInstructions; i++)
{
pInstDeps[i].nDstDep = -1;
pILInst = &(mesa_fp->Base.Instructions[i]);
//Dst
if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
{
//Set lastwrite for the temp
puiTEMPwrites[pILInst->DstReg.Index] = i;
}
//Src
for(j=0; j<3; j++)
{
if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
{
//Set dep.
pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
//Set first read
if(puiTEMPreads[pILInst->SrcReg[j].Index] < 0 )
{
puiTEMPreads[pILInst->SrcReg[j].Index] = i;
}
}
else
{
pInstDeps[i].nSrcDeps[j] = -1;
}
}
}
fp->r700AsmCode.pInstDeps = pInstDeps;
//Find dep for tex inst
for(i=0; i<mesa_fp->Base.NumInstructions; i++)
{
pILInst = &(mesa_fp->Base.Instructions[i]);
if(GL_TRUE == IsTex(pILInst->Opcode))
{ //src0 is the tex coord register, src1 is texunit, src2 is textype
nDepInstID = pInstDeps[i].nSrcDeps[0];
if(nDepInstID >= 0)
{
texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
{
pInstDeps[nDepInstID].nDstDep = i;
pInstDeps[i].nDstDep = i;
}
else if(GL_TRUE == IsTex(texcoord_DepInst->Opcode) )
{
pInstDeps[i].nDstDep = i;
}
else
{ //... other deps?
}
}
// make sure that we dont overwrite src used earlier
nDepInstID = puiTEMPreads[pILInst->DstReg.Index];
if(nDepInstID < i)
{
pInstDeps[i].nDstDep = puiTEMPreads[pILInst->DstReg.Index];
texcoord_DepInst = &(mesa_fp->Base.Instructions[nDepInstID]);
if(GL_TRUE == IsAlu(texcoord_DepInst->Opcode) )
{
pInstDeps[nDepInstID].nDstDep = i;
}
}
}
}
FREE(puiTEMPwrites);
FREE(puiTEMPreads);
return GL_TRUE;
}
GLboolean evergreenTranslateFragmentShader(struct evergreen_fragment_program *fp,
struct gl_fragment_program *mesa_fp,
struct gl_context *ctx)
{
GLuint number_of_colors_exported;
GLboolean z_enabled = GL_FALSE;
GLuint unBit, shadow_unit;
int i;
struct prog_instruction *inst;
gl_state_index shadow_ambient[STATE_LENGTH]
= { STATE_INTERNAL, STATE_SHADOW_AMBIENT, 0, 0, 0};
//Init_Program
Init_r700_AssemblerBase( SPT_FP, &(fp->r700AsmCode), &(fp->r700Shader) );
fp->constbo0 = NULL;
fp->r700AsmCode.bUseMemConstant = GL_TRUE;
fp->r700AsmCode.unAsic = 8;
if(mesa_fp->Base.InputsRead & FRAG_BIT_WPOS)
{
evergreen_insert_wpos_code(ctx, mesa_fp);
}
/* add/map consts for ARB_shadow_ambient */
if(mesa_fp->Base.ShadowSamplers)
{
inst = mesa_fp->Base.Instructions;
for (i = 0; i < mesa_fp->Base.NumInstructions; i++)
{
if(inst->TexShadow == 1)
{
shadow_unit = inst->TexSrcUnit;
shadow_ambient[2] = shadow_unit;
fp->r700AsmCode.shadow_regs[shadow_unit] =
_mesa_add_state_reference(mesa_fp->Base.Parameters, shadow_ambient);
}
inst++;
}
}
evergreen_Map_Fragment_Program(&(fp->r700AsmCode), mesa_fp, ctx);
if( GL_FALSE == evergreen_Find_Instruction_Dependencies_fp(fp, mesa_fp) )
{
return GL_FALSE;
}
InitShaderProgram(&(fp->r700AsmCode));
for(i=0; i < MAX_SAMPLERS; i++)
{
fp->r700AsmCode.SamplerUnits[i] = fp->mesa_program.Base.SamplerUnits[i];
}
fp->r700AsmCode.unCurNumILInsts = mesa_fp->Base.NumInstructions;
if( GL_FALSE == AssembleInstr(0,
0,
mesa_fp->Base.NumInstructions,
&(mesa_fp->Base.Instructions[0]),
&(fp->r700AsmCode)) )
{
return GL_FALSE;
}
if(GL_FALSE == Process_Fragment_Exports(&(fp->r700AsmCode), mesa_fp->Base.OutputsWritten) )
{
return GL_FALSE;
}
if( GL_FALSE == RelocProgram(&(fp->r700AsmCode), &(mesa_fp->Base)) )
{
return GL_FALSE;
}
fp->r700Shader.nRegs = (fp->r700AsmCode.number_used_registers == 0) ? 0
: (fp->r700AsmCode.number_used_registers - 1);
fp->r700Shader.nParamExports = fp->r700AsmCode.number_of_exports;
number_of_colors_exported = fp->r700AsmCode.number_of_colorandz_exports;
unBit = 1 << FRAG_RESULT_DEPTH;
if(mesa_fp->Base.OutputsWritten & unBit)
{
z_enabled = GL_TRUE;
number_of_colors_exported--;
}
/* illegal to set this to 0 */
if(number_of_colors_exported || z_enabled)
{
fp->r700Shader.exportMode = number_of_colors_exported << 1 | z_enabled;
}
else
{
fp->r700Shader.exportMode = (1 << 1);
}
fp->translated = GL_TRUE;
return GL_TRUE;
}
void evergreenSelectFragmentShader(struct gl_context *ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
(ctx->FragmentProgram._Current);
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
{
fp->r700AsmCode.bR6xx = 1;
}
if (GL_FALSE == fp->translated)
evergreenTranslateFragmentShader(fp, &(fp->mesa_program), ctx);
}
void * evergreenGetActiveFpShaderBo(struct gl_context * ctx)
{
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
(ctx->FragmentProgram._Current);
return fp->shaderbo;
}
void * evergreenGetActiveFpShaderConstBo(struct gl_context * ctx)
{
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
(ctx->FragmentProgram._Current);
return fp->constbo0;
}
GLboolean evergreenSetupFragmentProgram(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
(ctx->FragmentProgram._Current);
r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
struct gl_fragment_program *mesa_fp = &(fp->mesa_program);
unsigned int ui, i;
unsigned int unNumOfReg;
unsigned int unBit;
GLuint exportCount;
GLboolean point_sprite = GL_FALSE;
if(GL_FALSE == fp->loaded)
{
if(fp->r700Shader.bNeedsAssembly == GL_TRUE)
{
Assemble( &(fp->r700Shader) );
}
r600EmitShader(ctx,
&(fp->shaderbo),
(GLvoid *)(fp->r700Shader.pProgram),
fp->r700Shader.uShaderBinaryDWORDSize,
"FS");
fp->loaded = GL_TRUE;
}
/* TODO : enable this after MemUse fixed *=
(context->chipobj.MemUse)(context, fp->shadercode.buf->id);
*/
EVERGREEN_STATECHANGE(context, sq);
evergreen->SQ_PGM_RESOURCES_PS.u32All = 0;
SETbit(evergreen->SQ_PGM_RESOURCES_PS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
evergreen->ps.SQ_ALU_CONST_CACHE_PS_0.u32All = 0;
evergreen->ps.SQ_PGM_START_PS.u32All = 0;
EVERGREEN_STATECHANGE(context, spi);
unNumOfReg = fp->r700Shader.nRegs + 1;
ui = (evergreen->SPI_PS_IN_CONTROL_0.u32All & NUM_INTERP_mask) / (1 << NUM_INTERP_shift);
/* PS uses fragment.position */
if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS))
{
ui += 1;
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, CENTERS_ONLY, BARYC_SAMPLE_CNTL_shift, BARYC_SAMPLE_CNTL_mask);
SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
SETbit(evergreen->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
}
else
{
CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, POSITION_ENA_bit);
CLEARbit(evergreen->SPI_INPUT_Z.u32All, PROVIDE_Z_TO_SPI_bit);
}
if (mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_FACE))
{
ui += 1;
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
SETbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
SETbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ALL_BITS_bit);
SETfield(evergreen->SPI_PS_IN_CONTROL_1.u32All, pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE], FRONT_FACE_ADDR_shift, FRONT_FACE_ADDR_mask);
}
else
{
CLEARbit(evergreen->SPI_PS_IN_CONTROL_1.u32All, FRONT_FACE_ENA_bit);
}
/* see if we need any point_sprite replacements */
for (i = VERT_RESULT_TEX0; i<= VERT_RESULT_TEX7; i++)
{
if(ctx->Point.CoordReplace[i - VERT_RESULT_TEX0] == GL_TRUE)
point_sprite = GL_TRUE;
}
if ((mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC)) || point_sprite)
{
/* for FRAG_ATTRIB_PNTC we need to increase num_interp */
if(mesa_fp->Base.InputsRead & (1 << FRAG_ATTRIB_PNTC))
{
ui++;
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, ui, NUM_INTERP_shift, NUM_INTERP_mask);
}
SETbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_S, PNT_SPRITE_OVRD_X_shift, PNT_SPRITE_OVRD_X_mask);
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_T, PNT_SPRITE_OVRD_Y_shift, PNT_SPRITE_OVRD_Y_mask);
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_0, PNT_SPRITE_OVRD_Z_shift, PNT_SPRITE_OVRD_Z_mask);
SETfield(evergreen->SPI_INTERP_CONTROL_0.u32All, SPI_PNT_SPRITE_SEL_1, PNT_SPRITE_OVRD_W_shift, PNT_SPRITE_OVRD_W_mask);
if(ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
SETbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
else
CLEARbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_TOP_1_bit);
}
else
{
CLEARbit(evergreen->SPI_INTERP_CONTROL_0.u32All, PNT_SPRITE_ENA_bit);
}
ui = (unNumOfReg < ui) ? ui : unNumOfReg;
SETfield(evergreen->SQ_PGM_RESOURCES_PS.u32All, ui, NUM_GPRS_shift, NUM_GPRS_mask);
CLEARbit(evergreen->SQ_PGM_RESOURCES_PS.u32All, UNCACHED_FIRST_INST_bit);
if(fp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
{
SETfield(evergreen->SQ_PGM_RESOURCES_PS.u32All, fp->r700Shader.uStackSize,
STACK_SIZE_shift, STACK_SIZE_mask);
}
SETfield(evergreen->SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
EXPORT_MODE_shift, EXPORT_MODE_mask);
// emit ps input map
struct evergreen_vertex_program_cont *vpc =
(struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
GLbitfield OutputsWritten = vpc->mesa_program.Base.OutputsWritten;
for(ui = 0; ui < EVERGREEN_MAX_SHADER_EXPORTS; ui++)
evergreen->SPI_PS_INPUT_CNTL[ui].u32All = 0;
unBit = 1 << FRAG_ATTRIB_WPOS;
if(mesa_fp->Base.InputsRead & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_WPOS];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
unBit = 1 << VERT_RESULT_COL0;
if(OutputsWritten & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL0];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
else
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
unBit = 1 << VERT_RESULT_COL1;
if(OutputsWritten & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_COL1];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
if (evergreen->SPI_INTERP_CONTROL_0.u32All & FLAT_SHADE_ENA_bit)
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
else
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
unBit = 1 << VERT_RESULT_FOGC;
if(OutputsWritten & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FOGC];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
for(i=0; i<8; i++)
{
unBit = 1 << (VERT_RESULT_TEX0 + i);
if(OutputsWritten & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_TEX0 + i];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
/* ARB_point_sprite */
if(ctx->Point.CoordReplace[i] == GL_TRUE)
{
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
}
}
}
unBit = 1 << FRAG_ATTRIB_FACE;
if(mesa_fp->Base.InputsRead & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_FACE];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
unBit = 1 << FRAG_ATTRIB_PNTC;
if(mesa_fp->Base.InputsRead & unBit)
{
ui = pAsm->uiFP_AttributeMap[FRAG_ATTRIB_PNTC];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, PT_SPRITE_TEX_bit);
}
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
{
unBit = 1 << i;
if(OutputsWritten & unBit)
{
ui = pAsm->uiFP_AttributeMap[i-VERT_RESULT_VAR0+FRAG_ATTRIB_VAR0];
SETbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, SEL_CENTROID_bit);
SETfield(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, ui,
SEMANTIC_shift, SEMANTIC_mask);
CLEARbit(evergreen->SPI_PS_INPUT_CNTL[ui].u32All, FLAT_SHADE_bit);
}
}
exportCount = (evergreen->SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
return GL_TRUE;
}
GLboolean evergreenSetupFPconstants(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
struct evergreen_fragment_program *fp = (struct evergreen_fragment_program *)
(ctx->FragmentProgram._Current);
r700_AssemblerBase *pAsm = &(fp->r700AsmCode);
struct gl_program_parameter_list *paramList;
unsigned int unNumParamData;
unsigned int ui;
int alloc_size;
/* sent out shader constants. */
paramList = fp->mesa_program.Base.Parameters;
if(NULL != paramList)
{
_mesa_load_state_parameters(ctx, paramList);
if (paramList->NumParameters > EVERGREEN_MAX_DX9_CONSTS)
return GL_FALSE;
EVERGREEN_STATECHANGE(context, sq);
evergreen->ps.num_consts = paramList->NumParameters;
unNumParamData = paramList->NumParameters;
for(ui=0; ui<unNumParamData; ui++) {
evergreen->ps.consts[ui][0].f32All = paramList->ParameterValues[ui][0].f;
evergreen->ps.consts[ui][1].f32All = paramList->ParameterValues[ui][1].f;
evergreen->ps.consts[ui][2].f32All = paramList->ParameterValues[ui][2].f;
evergreen->ps.consts[ui][3].f32All = paramList->ParameterValues[ui][3].f;
}
/* alloc multiple of 16 constants */
alloc_size = ((unNumParamData * 4 * 4) + 255) & ~255;
/* Load fp constants to gpu */
if(unNumParamData > 0)
{
radeonAllocDmaRegion(&context->radeon,
&context->fp_Constbo,
&context->fp_bo_offset,
alloc_size,
256);
r600EmitShaderConsts(ctx,
context->fp_Constbo,
context->fp_bo_offset,
(GLvoid *)&(evergreen->ps.consts[0][0]),
unNumParamData * 4 * 4);
}
} else
evergreen->ps.num_consts = 0;
COMPILED_SUB * pCompiledSub;
GLuint uj;
GLuint unConstOffset = evergreen->ps.num_consts;
for(ui=0; ui<pAsm->unNumPresub; ui++)
{
pCompiledSub = pAsm->presubs[ui].pCompiledSub;
evergreen->ps.num_consts += pCompiledSub->NumParameters;
for(uj=0; uj<pCompiledSub->NumParameters; uj++)
{
evergreen->ps.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
evergreen->ps.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
evergreen->ps.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
evergreen->ps.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
}
unConstOffset += pCompiledSub->NumParameters;
}
return GL_TRUE;
}

77
src/mesa/drivers/dri/r600/evergreen_fragprog.h
View file

@ -1,77 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_FRAGPROG_H_
#define _EVERGREEN_FRAGPROG_H_
#include "r600_context.h"
#include "r700_assembler.h"
struct evergreen_fragment_program
{
struct gl_fragment_program mesa_program;
r700_AssemblerBase r700AsmCode;
R700_Shader r700Shader;
GLboolean translated;
GLboolean loaded;
GLboolean error;
void * shaderbo;
GLuint k0used;
void * constbo0;
GLboolean WritesDepth;
GLuint optimization;
};
/* Internal */
void evergreen_insert_wpos_code(struct gl_context *ctx, struct gl_fragment_program *fprog);
void evergreen_Map_Fragment_Program(r700_AssemblerBase *pAsm,
struct gl_fragment_program *mesa_fp,
struct gl_context *ctx);
GLboolean evergreen_Find_Instruction_Dependencies_fp(struct evergreen_fragment_program *fp,
struct gl_fragment_program *mesa_fp);
GLboolean evergreenTranslateFragmentShader(struct evergreen_fragment_program *fp,
struct gl_fragment_program *mesa_vp,
struct gl_context *ctx);
/* Interface */
extern void evergreenSelectFragmentShader(struct gl_context *ctx);
extern GLboolean evergreenSetupFragmentProgram(struct gl_context * ctx);
extern GLboolean evergreenSetupFPconstants(struct gl_context * ctx);
extern void * evergreenGetActiveFpShaderBo(struct gl_context * ctx);
extern void * evergreenGetActiveFpShaderConstBo(struct gl_context * ctx);
#endif /*_EVERGREEN_FRAGPROG_H_*/

53
src/mesa/drivers/dri/r600/evergreen_ioctl.c
View file

@ -1,53 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#include <sched.h>
#include <errno.h>
#include "main/glheader.h"
#include "main/imports.h"
#include "main/macros.h"
#include "main/context.h"
#include "main/simple_list.h"
#include "radeon_common.h"
#include "r600_context.h"
#include "evergreen_ioctl.h"
#include "r700_clear.h"
void evergreenClear(struct gl_context * ctx, GLbitfield mask)
{
r700Clear(ctx, mask);
}
void evergreenInitIoctlFuncs(struct dd_function_table *functions)
{
functions->Clear = evergreenClear;
functions->Finish = radeonFinish;
functions->Flush = radeonFlush;
}

36
src/mesa/drivers/dri/r600/evergreen_ioctl.h
View file

@ -1,36 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_IOCTL_H_
#define _EVERGREEN_IOCTL_H_
#include "r600_context.h"
#include "radeon_drm.h"
extern void evergreenClear(struct gl_context * ctx, GLbitfield mask);
extern void evergreenInitIoctlFuncs(struct dd_function_table *functions);
#endif /* _EVERGREEN_IOCTL_H_ */

881
src/mesa/drivers/dri/r600/evergreen_off.h
View file

@ -1,881 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_OFF_H_
#define _EVERGREEN_OFF_H_
enum
{
/* Registers from PA block: */
EG_PA_SC_SCREEN_SCISSOR_TL = 0x28030, // DIFF
EG_PA_SC_SCREEN_SCISSOR_BR = 0x28034, // DIFF
EG_PA_SC_WINDOW_OFFSET = 0x28200, // DIFF
EG_PA_SC_WINDOW_SCISSOR_TL = 0x28204, // DIFF
EG_PA_SC_WINDOW_SCISSOR_BR = 0x28208, // DIFF
EG_PA_SC_CLIPRECT_RULE = 0x2820C, // SAME
EG_PA_SC_CLIPRECT_0_TL = 0x28210, // DIFF
EG_PA_SC_CLIPRECT_0_BR = 0x28214, // DIFF
EG_PA_SC_CLIPRECT_1_TL = 0x28218, // DIFF
EG_PA_SC_CLIPRECT_1_BR = 0x2821C, // DIFF
EG_PA_SC_CLIPRECT_2_TL = 0x28220, // DIFF
EG_PA_SC_CLIPRECT_2_BR = 0x28224, // DIFF
EG_PA_SC_CLIPRECT_3_TL = 0x28228, // DIFF
EG_PA_SC_CLIPRECT_3_BR = 0x2822C, // DIFF
EG_PA_SC_EDGERULE = 0x28230, // SAME
EG_PA_SU_HARDWARE_SCREEN_OFFSET = 0x28234, //
EG_PA_SC_GENERIC_SCISSOR_TL = 0x28240, // DIFF
EG_PA_SC_GENERIC_SCISSOR_BR = 0x28244, // DIFF
EG_PA_SC_VPORT_SCISSOR_0_TL = 0x28250, // DIFF
EG_PA_SC_VPORT_SCISSOR_0_BR = 0x28254, // DIFF
EG_PA_SC_VPORT_SCISSOR_1_TL = 0x28258, // DIFF
EG_PA_SC_VPORT_SCISSOR_1_BR = 0x2825C, // DIFF
EG_PA_SC_VPORT_SCISSOR_2_TL = 0x28260, // DIFF
EG_PA_SC_VPORT_SCISSOR_2_BR = 0x28264, // DIFF
EG_PA_SC_VPORT_SCISSOR_3_TL = 0x28268, // DIFF
EG_PA_SC_VPORT_SCISSOR_3_BR = 0x2826C, // DIFF
EG_PA_SC_VPORT_SCISSOR_4_TL = 0x28270, // DIFF
EG_PA_SC_VPORT_SCISSOR_4_BR = 0x28274, // DIFF
EG_PA_SC_VPORT_SCISSOR_5_TL = 0x28278, // DIFF
EG_PA_SC_VPORT_SCISSOR_5_BR = 0x2827C, // DIFF
EG_PA_SC_VPORT_SCISSOR_6_TL = 0x28280, // DIFF
EG_PA_SC_VPORT_SCISSOR_6_BR = 0x28284, // DIFF
EG_PA_SC_VPORT_SCISSOR_7_TL = 0x28288, // DIFF
EG_PA_SC_VPORT_SCISSOR_7_BR = 0x2828C, // DIFF
EG_PA_SC_VPORT_SCISSOR_8_TL = 0x28290, // DIFF
EG_PA_SC_VPORT_SCISSOR_8_BR = 0x28294, // DIFF
EG_PA_SC_VPORT_SCISSOR_9_TL = 0x28298, // DIFF
EG_PA_SC_VPORT_SCISSOR_9_BR = 0x2829C, // DIFF
EG_PA_SC_VPORT_SCISSOR_10_TL = 0x282A0, // DIFF
EG_PA_SC_VPORT_SCISSOR_10_BR = 0x282A4, // DIFF
EG_PA_SC_VPORT_SCISSOR_11_TL = 0x282A8, // DIFF
EG_PA_SC_VPORT_SCISSOR_11_BR = 0x282AC, // DIFF
EG_PA_SC_VPORT_SCISSOR_12_TL = 0x282B0, // DIFF
EG_PA_SC_VPORT_SCISSOR_12_BR = 0x282B4, // DIFF
EG_PA_SC_VPORT_SCISSOR_13_TL = 0x282B8, // DIFF
EG_PA_SC_VPORT_SCISSOR_13_BR = 0x282BC, // DIFF
EG_PA_SC_VPORT_SCISSOR_14_TL = 0x282C0, // DIFF
EG_PA_SC_VPORT_SCISSOR_14_BR = 0x282C4, // DIFF
EG_PA_SC_VPORT_SCISSOR_15_TL = 0x282C8, // DIFF
EG_PA_SC_VPORT_SCISSOR_15_BR = 0x282CC, // DIFF
EG_PA_SC_VPORT_ZMIN_0 = 0x282D0, // SAME
EG_PA_SC_VPORT_ZMAX_0 = 0x282D4, // SAME
EG_PA_SC_VPORT_ZMIN_1 = 0x282D8, // SAME
EG_PA_SC_VPORT_ZMAX_1 = 0x282DC, // SAME
EG_PA_SC_VPORT_ZMIN_2 = 0x282E0, // SAME
EG_PA_SC_VPORT_ZMAX_2 = 0x282E4, // SAME
EG_PA_SC_VPORT_ZMIN_3 = 0x282E8, // SAME
EG_PA_SC_VPORT_ZMAX_3 = 0x282EC, // SAME
EG_PA_SC_VPORT_ZMIN_4 = 0x282F0, // SAME
EG_PA_SC_VPORT_ZMAX_4 = 0x282F4, // SAME
EG_PA_SC_VPORT_ZMIN_5 = 0x282F8, // SAME
EG_PA_SC_VPORT_ZMAX_5 = 0x282FC, // SAME
EG_PA_SC_VPORT_ZMIN_6 = 0x28300, // SAME
EG_PA_SC_VPORT_ZMAX_6 = 0x28304, // SAME
EG_PA_SC_VPORT_ZMIN_7 = 0x28308, // SAME
EG_PA_SC_VPORT_ZMAX_7 = 0x2830C, // SAME
EG_PA_SC_VPORT_ZMIN_8 = 0x28310, // SAME
EG_PA_SC_VPORT_ZMAX_8 = 0x28314, // SAME
EG_PA_SC_VPORT_ZMIN_9 = 0x28318, // SAME
EG_PA_SC_VPORT_ZMAX_9 = 0x2831C, // SAME
EG_PA_SC_VPORT_ZMIN_10 = 0x28320, // SAME
EG_PA_SC_VPORT_ZMAX_10 = 0x28324, // SAME
EG_PA_SC_VPORT_ZMIN_11 = 0x28328, // SAME
EG_PA_SC_VPORT_ZMAX_11 = 0x2832C, // SAME
EG_PA_SC_VPORT_ZMIN_12 = 0x28330, // SAME
EG_PA_SC_VPORT_ZMAX_12 = 0x28334, // SAME
EG_PA_SC_VPORT_ZMIN_13 = 0x28338, // SAME
EG_PA_SC_VPORT_ZMAX_13 = 0x2833C, // SAME
EG_PA_SC_VPORT_ZMIN_14 = 0x28340, // SAME
EG_PA_SC_VPORT_ZMAX_14 = 0x28344, // SAME
EG_PA_SC_VPORT_ZMIN_15 = 0x28348, // SAME
EG_PA_SC_VPORT_ZMAX_15 = 0x2834C, // SAME
EG_PA_CL_VPORT_XSCALE = 0x2843C, // SAME
EG_PA_CL_VPORT_XOFFSET = 0x28440, // SAME
EG_PA_CL_VPORT_YSCALE = 0x28444, // SAME
EG_PA_CL_VPORT_YOFFSET = 0x28448, // SAME
EG_PA_CL_VPORT_ZSCALE = 0x2844C, // SAME
EG_PA_CL_VPORT_ZOFFSET = 0x28450, // SAME
EG_PA_CL_VPORT_XSCALE_1 = 0x28454, // SAME
EG_PA_CL_VPORT_XOFFSET_1 = 0x28458, // SAME
EG_PA_CL_VPORT_YSCALE_1 = 0x2845C, // SAME
EG_PA_CL_VPORT_YOFFSET_1 = 0x28460, // SAME
EG_PA_CL_VPORT_ZSCALE_1 = 0x28464, // SAME
EG_PA_CL_VPORT_ZOFFSET_1 = 0x28468, // SAME
EG_PA_CL_VPORT_XSCALE_2 = 0x2846C, // SAME
EG_PA_CL_VPORT_XOFFSET_2 = 0x28470, // SAME
EG_PA_CL_VPORT_YSCALE_2 = 0x28474, // SAME
EG_PA_CL_VPORT_YOFFSET_2 = 0x28478, // SAME
EG_PA_CL_VPORT_ZSCALE_2 = 0x2847C, // SAME
EG_PA_CL_VPORT_ZOFFSET_2 = 0x28480, // SAME
EG_PA_CL_VPORT_XSCALE_3 = 0x28484, // SAME
EG_PA_CL_VPORT_XOFFSET_3 = 0x28488, // SAME
EG_PA_CL_VPORT_YSCALE_3 = 0x2848C, // SAME
EG_PA_CL_VPORT_YOFFSET_3 = 0x28490, // SAME
EG_PA_CL_VPORT_ZSCALE_3 = 0x28494, // SAME
EG_PA_CL_VPORT_ZOFFSET_3 = 0x28498, // SAME
EG_PA_CL_VPORT_XSCALE_4 = 0x2849C, // SAME
EG_PA_CL_VPORT_XOFFSET_4 = 0x284A0, // SAME
EG_PA_CL_VPORT_YSCALE_4 = 0x284A4, // SAME
EG_PA_CL_VPORT_YOFFSET_4 = 0x284A8, // SAME
EG_PA_CL_VPORT_ZSCALE_4 = 0x284AC, // SAME
EG_PA_CL_VPORT_ZOFFSET_4 = 0x284B0, // SAME
EG_PA_CL_VPORT_XSCALE_5 = 0x284B4, // SAME
EG_PA_CL_VPORT_XOFFSET_5 = 0x284B8, // SAME
EG_PA_CL_VPORT_YSCALE_5 = 0x284BC, // SAME
EG_PA_CL_VPORT_YOFFSET_5 = 0x284C0, // SAME
EG_PA_CL_VPORT_ZSCALE_5 = 0x284C4, // SAME
EG_PA_CL_VPORT_ZOFFSET_5 = 0x284C8, // SAME
EG_PA_CL_VPORT_XSCALE_6 = 0x284CC, // SAME
EG_PA_CL_VPORT_XOFFSET_6 = 0x284D0, // SAME
EG_PA_CL_VPORT_YSCALE_6 = 0x284D4, // SAME
EG_PA_CL_VPORT_YOFFSET_6 = 0x284D8, // SAME
EG_PA_CL_VPORT_ZSCALE_6 = 0x284DC, // SAME
EG_PA_CL_VPORT_ZOFFSET_6 = 0x284E0, // SAME
EG_PA_CL_VPORT_XSCALE_7 = 0x284E4, // SAME
EG_PA_CL_VPORT_XOFFSET_7 = 0x284E8, // SAME
EG_PA_CL_VPORT_YSCALE_7 = 0x284EC, // SAME
EG_PA_CL_VPORT_YOFFSET_7 = 0x284F0, // SAME
EG_PA_CL_VPORT_ZSCALE_7 = 0x284F4, // SAME
EG_PA_CL_VPORT_ZOFFSET_7 = 0x284F8, // SAME
EG_PA_CL_VPORT_XSCALE_8 = 0x284FC, // SAME
EG_PA_CL_VPORT_XOFFSET_8 = 0x28500, // SAME
EG_PA_CL_VPORT_YSCALE_8 = 0x28504, // SAME
EG_PA_CL_VPORT_YOFFSET_8 = 0x28508, // SAME
EG_PA_CL_VPORT_ZSCALE_8 = 0x2850C, // SAME
EG_PA_CL_VPORT_ZOFFSET_8 = 0x28510, // SAME
EG_PA_CL_VPORT_XSCALE_9 = 0x28514, // SAME
EG_PA_CL_VPORT_XOFFSET_9 = 0x28518, // SAME
EG_PA_CL_VPORT_YSCALE_9 = 0x2851C, // SAME
EG_PA_CL_VPORT_YOFFSET_9 = 0x28520, // SAME
EG_PA_CL_VPORT_ZSCALE_9 = 0x28524, // SAME
EG_PA_CL_VPORT_ZOFFSET_9 = 0x28528, // SAME
EG_PA_CL_VPORT_XSCALE_10 = 0x2852C, // SAME
EG_PA_CL_VPORT_XOFFSET_10 = 0x28530, // SAME
EG_PA_CL_VPORT_YSCALE_10 = 0x28534, // SAME
EG_PA_CL_VPORT_YOFFSET_10 = 0x28538, // SAME
EG_PA_CL_VPORT_ZSCALE_10 = 0x2853C, // SAME
EG_PA_CL_VPORT_ZOFFSET_10 = 0x28540, // SAME
EG_PA_CL_VPORT_XSCALE_11 = 0x28544, // SAME
EG_PA_CL_VPORT_XOFFSET_11 = 0x28548, // SAME
EG_PA_CL_VPORT_YSCALE_11 = 0x2854C, // SAME
EG_PA_CL_VPORT_YOFFSET_11 = 0x28550, // SAME
EG_PA_CL_VPORT_ZSCALE_11 = 0x28554, // SAME
EG_PA_CL_VPORT_ZOFFSET_11 = 0x28558, // SAME
EG_PA_CL_VPORT_XSCALE_12 = 0x2855C, // SAME
EG_PA_CL_VPORT_XOFFSET_12 = 0x28560, // SAME
EG_PA_CL_VPORT_YSCALE_12 = 0x28564, // SAME
EG_PA_CL_VPORT_YOFFSET_12 = 0x28568, // SAME
EG_PA_CL_VPORT_ZSCALE_12 = 0x2856C, // SAME
EG_PA_CL_VPORT_ZOFFSET_12 = 0x28570, // SAME
EG_PA_CL_VPORT_XSCALE_13 = 0x28574, // SAME
EG_PA_CL_VPORT_XOFFSET_13 = 0x28578, // SAME
EG_PA_CL_VPORT_YSCALE_13 = 0x2857C, // SAME
EG_PA_CL_VPORT_YOFFSET_13 = 0x28580, // SAME
EG_PA_CL_VPORT_ZSCALE_13 = 0x28584, // SAME
EG_PA_CL_VPORT_ZOFFSET_13 = 0x28588, // SAME
EG_PA_CL_VPORT_XSCALE_14 = 0x2858C, // SAME
EG_PA_CL_VPORT_XOFFSET_14 = 0x28590, // SAME
EG_PA_CL_VPORT_YSCALE_14 = 0x28594, // SAME
EG_PA_CL_VPORT_YOFFSET_14 = 0x28598, // SAME
EG_PA_CL_VPORT_ZSCALE_14 = 0x2859C, // SAME
EG_PA_CL_VPORT_ZOFFSET_14 = 0x285A0, // SAME
EG_PA_CL_VPORT_XSCALE_15 = 0x285A4, // SAME
EG_PA_CL_VPORT_XOFFSET_15 = 0x285A8, // SAME
EG_PA_CL_VPORT_YSCALE_15 = 0x285AC, // SAME
EG_PA_CL_VPORT_YOFFSET_15 = 0x285B0, // SAME
EG_PA_CL_VPORT_ZSCALE_15 = 0x285B4, // SAME
EG_PA_CL_VPORT_ZOFFSET_15 = 0x285B8, // SAME
EG_PA_CL_UCP_0_X = 0x285BC, // SAME 0x28E20
EG_PA_CL_UCP_0_Y = 0x285C0, // SAME 0x28E24
EG_PA_CL_UCP_0_Z = 0x285C4, // SAME 0x28E28
EG_PA_CL_UCP_0_W = 0x285C8, // SAME 0x28E2C
EG_PA_CL_UCP_1_X = 0x285CC, // SAME 0x28E30
EG_PA_CL_UCP_1_Y = 0x285D0, // SAME 0x28E34
EG_PA_CL_UCP_1_Z = 0x285D4, // SAME 0x28E38
EG_PA_CL_UCP_1_W = 0x285D8, // SAME 0x28E3C
EG_PA_CL_UCP_2_X = 0x285DC, // SAME 0x28E40
EG_PA_CL_UCP_2_Y = 0x285E0, // SAME 0x28E44
EG_PA_CL_UCP_2_Z = 0x285E4, // SAME 0x28E48
EG_PA_CL_UCP_2_W = 0x285E8, // SAME 0x28E4C
EG_PA_CL_UCP_3_X = 0x285EC, // SAME 0x28E50
EG_PA_CL_UCP_3_Y = 0x285F0, // SAME 0x28E54
EG_PA_CL_UCP_3_Z = 0x285F4, // SAME 0x28E58
EG_PA_CL_UCP_3_W = 0x285F8, // SAME 0x28E5C
EG_PA_CL_UCP_4_X = 0x285FC, // SAME 0x28E60
EG_PA_CL_UCP_4_Y = 0x28600, // SAME 0x28E64
EG_PA_CL_UCP_4_Z = 0x28604, // SAME 0x28E68
EG_PA_CL_UCP_4_W = 0x28608, // SAME 0x28E6C
EG_PA_CL_UCP_5_X = 0x2860C, // SAME 0x28E70
EG_PA_CL_UCP_5_Y = 0x28610, // SAME 0x28E74
EG_PA_CL_UCP_5_Z = 0x28614, // SAME 0x28E78
EG_PA_CL_UCP_5_W = 0x28618, // SAME 0x28E7C
EG_PA_CL_POINT_X_RAD = 0x287D4, // SAME 0x28E10
EG_PA_CL_POINT_Y_RAD = 0x287D8, // SAME 0x28E14
EG_PA_CL_POINT_SIZE = 0x287DC, // SAME 0x28E18
EG_PA_CL_POINT_CULL_RAD = 0x287E0, // SAME 0x28E1C
EG_PA_CL_CLIP_CNTL = 0x28810, // SAME
EG_PA_SU_SC_MODE_CNTL = 0x28814, // SAME
EG_PA_CL_VTE_CNTL = 0x28818, // SAME
EG_PA_CL_VS_OUT_CNTL = 0x2881C, // SAME
EG_PA_CL_NANINF_CNTL = 0x28820, // SAME
EG_PA_SU_LINE_STIPPLE_CNTL = 0x28824, //
EG_PA_SU_LINE_STIPPLE_SCALE = 0x28828, //
EG_PA_SU_PRIM_FILTER_CNTL = 0x2882C, //
EG_PA_SU_POINT_SIZE = 0x28A00, // SAME
EG_PA_SU_POINT_MINMAX = 0x28A04, // SAME
EG_PA_SU_LINE_CNTL = 0x28A08, // SAME
EG_PA_SC_LINE_STIPPLE = 0x28A0C, // SAME
EG_PA_SC_MODE_CNTL_0 = 0x28A48, //
EG_PA_SC_MODE_CNTL_1 = 0x28A4C, //
EG_PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x28B78, // SAME 0x28DF8
EG_PA_SU_POLY_OFFSET_CLAMP = 0x28B7C, // SAME 0x28DFC
EG_PA_SU_POLY_OFFSET_FRONT_SCALE = 0x28B80, // SAME 0x28E00
EG_PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x28B84, // SAME 0x28E04
EG_PA_SU_POLY_OFFSET_BACK_SCALE = 0x28B88, // SAME 0x28E08
EG_PA_SU_POLY_OFFSET_BACK_OFFSET = 0x28B8C, // SAME 0x28E0C
EG_PA_SC_LINE_CNTL = 0x28C00, // DIFF
EG_PA_SC_AA_CONFIG = 0x28C04, // SAME
EG_PA_SU_VTX_CNTL = 0x28C08, // SAME
EG_PA_CL_GB_VERT_CLIP_ADJ = 0x28C0C, // SAME
EG_PA_CL_GB_VERT_DISC_ADJ = 0x28C10, // SAME
EG_PA_CL_GB_HORZ_CLIP_ADJ = 0x28C14, // SAME
EG_PA_CL_GB_HORZ_DISC_ADJ = 0x28C18, // SAME
EG_PA_SC_AA_SAMPLE_LOCS_0 = 0x28C1C, //
EG_PA_SC_AA_SAMPLE_LOCS_1 = 0x28C20, //
EG_PA_SC_AA_SAMPLE_LOCS_2 = 0x28C24, //
EG_PA_SC_AA_SAMPLE_LOCS_3 = 0x28C28, //
EG_PA_SC_AA_SAMPLE_LOCS_4 = 0x28C2C, //
EG_PA_SC_AA_SAMPLE_LOCS_5 = 0x28C30, //
EG_PA_SC_AA_SAMPLE_LOCS_6 = 0x28C34, //
EG_PA_SC_AA_SAMPLE_LOCS_7 = 0x28C38, //
EG_PA_SC_AA_MASK = 0x28C3C, // SAME 0x28C48
/* Registers from VGT block: */
EG_VGT_INDEX_TYPE = 0x895C, //? config space
EG_VGT_PRIMITIVE_TYPE = 0x8958, //? config space
EG_VGT_MAX_VTX_INDX = 0x28400, // SAME
EG_VGT_MIN_VTX_INDX = 0x28404, // SAME
EG_VGT_INDX_OFFSET = 0x28408, // SAME
EG_VGT_MULTI_PRIM_IB_RESET_INDX = 0x2840C, // SAME
EG_CS_COPY_STATE = 0x287CC, //
EG_GFX_COPY_STATE = 0x287D0, // SAME
EG_VGT_DMA_BASE_HI = 0x287E4, // SAME
EG_VGT_DMA_BASE = 0x287E8, // SAME
EG_VGT_DRAW_INITIATOR = 0x287F0, // SAME
EG_VGT_IMMED_DATA = 0x287F4, // SAME
EG_VGT_EVENT_ADDRESS_REG = 0x287F8, // SAME
EG_VGT_OUTPUT_PATH_CNTL = 0x28A10, // DIFF
EG_VGT_HOS_CNTL = 0x28A14, // SAME
EG_VGT_HOS_MAX_TESS_LEVEL = 0x28A18, // SAME
EG_VGT_HOS_MIN_TESS_LEVEL = 0x28A1C, // SAME
EG_VGT_HOS_REUSE_DEPTH = 0x28A20, // SAME
EG_VGT_GROUP_PRIM_TYPE = 0x28A24, // SAME
EG_VGT_GROUP_FIRST_DECR = 0x28A28, // SAME
EG_VGT_GROUP_DECR = 0x28A2C, // SAME
EG_VGT_GROUP_VECT_0_CNTL = 0x28A30, // SAME
EG_VGT_GROUP_VECT_1_CNTL = 0x28A34, // SAME
EG_VGT_GROUP_VECT_0_FMT_CNTL = 0x28A38, // SAME
EG_VGT_GROUP_VECT_1_FMT_CNTL = 0x28A3C, // SAME
EG_VGT_GS_MODE = 0x28A40, // DIFF
EG_VGT_ENHANCE = 0x28A50, // DIFF
EG_VGT_GS_PER_ES = 0x28A54, // DIFF 0x88C8
EG_VGT_ES_PER_GS = 0x28A58, // DIFF 0x88CC
EG_VGT_GS_PER_VS = 0x28A5C, // SAME 0x88E8
EG_VGT_GS_OUT_PRIM_TYPE = 0x28A6C, // SAME
EG_VGT_DMA_SIZE = 0x28A74, // SAME
EG_VGT_DMA_MAX_SIZE = 0x28A78, // SAME
EG_VGT_DMA_INDEX_TYPE = 0x28A7C, // SAME
EG_VGT_PRIMITIVEID_EN = 0x28A84, // SAME
EG_VGT_DMA_NUM_INSTANCES = 0x28A88, // SAME
EG_VGT_EVENT_INITIATOR = 0x28A90, // SAME
EG_VGT_MULTI_PRIM_IB_RESET_EN = 0x28A94, // SAME
EG_VGT_INSTANCE_STEP_RATE_0 = 0x28AA0, // SAME
EG_VGT_INSTANCE_STEP_RATE_1 = 0x28AA4, // SAME
EG_VGT_REUSE_OFF = 0x28AB4, // SAME
EG_VGT_VTX_CNT_EN = 0x28AB8, // SAME
EG_VGT_STRMOUT_BUFFER_SIZE_0 = 0x28AD0, // SAME
EG_VGT_STRMOUT_VTX_STRIDE_0 = 0x28AD4, // SAME
EG_VGT_STRMOUT_BUFFER_BASE_0 = 0x28AD8, // SAME
EG_VGT_STRMOUT_BUFFER_OFFSET_0 = 0x28ADC, // SAME
EG_VGT_STRMOUT_BUFFER_SIZE_1 = 0x28AE0, // SAME
EG_VGT_STRMOUT_VTX_STRIDE_1 = 0x28AE4, // SAME
EG_VGT_STRMOUT_BUFFER_BASE_1 = 0x28AE8, // SAME
EG_VGT_STRMOUT_BUFFER_OFFSET_1 = 0x28AEC, // SAME
EG_VGT_STRMOUT_BUFFER_SIZE_2 = 0x28AF0, // SAME
EG_VGT_STRMOUT_VTX_STRIDE_2 = 0x28AF4, // SAME
EG_VGT_STRMOUT_BUFFER_BASE_2 = 0x28AF8, // SAME
EG_VGT_STRMOUT_BUFFER_OFFSET_2 = 0x28AFC, // SAME
EG_VGT_STRMOUT_BUFFER_SIZE_3 = 0x28B00, // SAME
EG_VGT_STRMOUT_VTX_STRIDE_3 = 0x28B04, // SAME
EG_VGT_STRMOUT_BUFFER_BASE_3 = 0x28B08, // SAME
EG_VGT_STRMOUT_BUFFER_OFFSET_3 = 0x28B0C, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_0 = 0x28B10, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_1 = 0x28B14, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_2 = 0x28B18, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_3 = 0x28B1C, // SAME
EG_VGT_STRMOUT_DRAW_OPAQUE_OFFSET = 0x28B28, // SAME
EG_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE = 0x28B2C, // SAME
EG_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE = 0x28B30, // DIFF
EG_VGT_GS_MAX_VERT_OUT = 0x28B38, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_HI_0 = 0x28B44, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_HI_1 = 0x28B48, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_HI_2 = 0x28B4C, // SAME
EG_VGT_STRMOUT_BASE_OFFSET_HI_3 = 0x28B50, // SAME
EG_VGT_SHADER_STAGES_EN = 0x28B54, //
EG_VGT_LS_HS_CONFIG = 0x28B58, //
EG_VGT_LS_SIZE = 0x28B5C, //
EG_VGT_HS_SIZE = 0x28B60, //
EG_VGT_LS_HS_ALLOC = 0x28B64, //
EG_VGT_HS_PATCH_CONST = 0x28B68, //
EG_VGT_TF_PARAM = 0x28B6C, //
EG_VGT_DISPATCH_INITIATOR = 0x28B74, //
EG_VGT_GS_INSTANCE_CNT = 0x28B90, //
EG_VGT_STRMOUT_CONFIG = 0x28B94, //
EG_VGT_STRMOUT_BUFFER_CONFIG = 0x28B98, //
EG_VGT_VERTEX_REUSE_BLOCK_CNTL = 0x28C58, // SAME
EG_VGT_OUT_DEALLOC_CNTL = 0x28C5C, // SAME
/* Registers from TP block: */
EG_GDS_ADDR_BASE = 0x28720, //
EG_GDS_ADDR_SIZE = 0x28724, //
EG_GDS_ORDERED_WAVE_PER_SE = 0x28728, //
EG_GDS_APPEND_CONSUME_UAV0 = 0x2872C, //
EG_GDS_APPEND_CONSUME_UAV1 = 0x28730, //
EG_GDS_APPEND_CONSUME_UAV2 = 0x28734, //
EG_GDS_APPEND_CONSUME_UAV3 = 0x28738, //
EG_GDS_APPEND_CONSUME_UAV4 = 0x2873C, //
EG_GDS_APPEND_CONSUME_UAV5 = 0x28740, //
EG_GDS_APPEND_CONSUME_UAV6 = 0x28744, //
EG_GDS_APPEND_CONSUME_UAV7 = 0x28748, //
EG_GDS_APPEND_CONSUME_UAV8 = 0x2874C, //
EG_GDS_APPEND_CONSUME_UAV9 = 0x28750, //
EG_GDS_APPEND_CONSUME_UAV10 = 0x28754, //
EG_GDS_APPEND_CONSUME_UAV11 = 0x28758, //
/* Registers from SQ block: */
EG_SQ_LOOP_CONST_0 = 0x3A200, // 0x3E200
EG_SQ_ALU_CONST_BUFFER_SIZE_VS_0 = 0x28180, // ?
EG_SQ_VTX_SEMANTIC_0 = 0x28380, // SAME
EG_SQ_VTX_SEMANTIC_1 = 0x28384, // SAME
EG_SQ_VTX_SEMANTIC_2 = 0x28388, // SAME
EG_SQ_VTX_SEMANTIC_3 = 0x2838C, // SAME
EG_SQ_VTX_SEMANTIC_4 = 0x28390, // SAME
EG_SQ_VTX_SEMANTIC_5 = 0x28394, // SAME
EG_SQ_VTX_SEMANTIC_6 = 0x28398, // SAME
EG_SQ_VTX_SEMANTIC_7 = 0x2839C, // SAME
EG_SQ_VTX_SEMANTIC_8 = 0x283A0, // SAME
EG_SQ_VTX_SEMANTIC_9 = 0x283A4, // SAME
EG_SQ_VTX_SEMANTIC_10 = 0x283A8, // SAME
EG_SQ_VTX_SEMANTIC_11 = 0x283AC, // SAME
EG_SQ_VTX_SEMANTIC_12 = 0x283B0, // SAME
EG_SQ_VTX_SEMANTIC_13 = 0x283B4, // SAME
EG_SQ_VTX_SEMANTIC_14 = 0x283B8, // SAME
EG_SQ_VTX_SEMANTIC_15 = 0x283BC, // SAME
EG_SQ_VTX_SEMANTIC_16 = 0x283C0, // SAME
EG_SQ_VTX_SEMANTIC_17 = 0x283C4, // SAME
EG_SQ_VTX_SEMANTIC_18 = 0x283C8, // SAME
EG_SQ_VTX_SEMANTIC_19 = 0x283CC, // SAME
EG_SQ_VTX_SEMANTIC_20 = 0x283D0, // SAME
EG_SQ_VTX_SEMANTIC_21 = 0x283D4, // SAME
EG_SQ_VTX_SEMANTIC_22 = 0x283D8, // SAME
EG_SQ_VTX_SEMANTIC_23 = 0x283DC, // SAME
EG_SQ_VTX_SEMANTIC_24 = 0x283E0, // SAME
EG_SQ_VTX_SEMANTIC_25 = 0x283E4, // SAME
EG_SQ_VTX_SEMANTIC_26 = 0x283E8, // SAME
EG_SQ_VTX_SEMANTIC_27 = 0x283EC, // SAME
EG_SQ_VTX_SEMANTIC_28 = 0x283F0, // SAME
EG_SQ_VTX_SEMANTIC_29 = 0x283F4, // SAME
EG_SQ_VTX_SEMANTIC_30 = 0x283F8, // SAME
EG_SQ_VTX_SEMANTIC_31 = 0x283FC, // SAME
EG_SQ_LSTMP_RING_ITEMSIZE = 0x28830, //
EG_SQ_HSTMP_RING_ITEMSIZE = 0x28834, //
EG_SQ_DYN_GPR_RESOURCE_LIMIT_1 = 0x28838, //
EG_SQ_PGM_START_PS = 0x28840, // SAME
EG_SQ_PGM_RESOURCES_PS = 0x28844, // DIFF 0x28850
EG_SQ_PGM_RESOURCES_2_PS = 0x28848, //
EG_SQ_PGM_EXPORTS_PS = 0x2884C, // SAME 0x28854
EG_SQ_PGM_START_VS = 0x2885C, // SAME 0x28858
EG_SQ_PGM_RESOURCES_VS = 0x28860, // DIFF 0x28868
EG_SQ_PGM_RESOURCES_2_VS = 0x28864, //
EG_SQ_PGM_START_GS = 0x28874, // SAME 0x2886C
EG_SQ_PGM_RESOURCES_GS = 0x28878, // DIFF 0x2887C
EG_SQ_PGM_RESOURCES_2_GS = 0x2887C, //
EG_SQ_PGM_START_ES = 0x2888C, // SAME 0x28880
EG_SQ_PGM_RESOURCES_ES = 0x28890, // DIFF
EG_SQ_PGM_RESOURCES_2_ES = 0x28894, //
EG_SQ_PGM_START_FS = 0x288A4, // SAME 0x28894
EG_SQ_PGM_RESOURCES_FS = 0x288A8, // DIFF 0x288A4
EG_SQ_PGM_START_HS = 0x288B8, //
EG_SQ_PGM_RESOURCES_HS = 0x288BC, //
EG_SQ_PGM_RESOURCES_2_HS = 0x288C0, //
EG_SQ_PGM_START_LS = 0x288D0, //
EG_SQ_PGM_RESOURCES_LS = 0x288D4, //
EG_SQ_PGM_RESOURCES_2_LS = 0x288D8, //
EG_SQ_THREAD_TRACE_USERDATA = 0x288DC, //
EG_SQ_LDS_ALLOC = 0x288E8, //
EG_SQ_LDS_ALLOC_PS = 0x288EC, //
EG_SQ_VTX_SEMANTIC_CLEAR = 0x288F0, // SAME 0x288E0
EG_SQ_THREAD_TRACE_CTRL = 0x288F8, //
EG_SQ_ESGS_RING_ITEMSIZE = 0x28900, // SAME 0x288A8
EG_SQ_GSVS_RING_ITEMSIZE = 0x28904, // SAME 0x288AC
EG_SQ_ESTMP_RING_ITEMSIZE = 0x28908, // SAME 0x288B0
EG_SQ_GSTMP_RING_ITEMSIZE = 0x2890C, // SAME 0x288B4
EG_SQ_VSTMP_RING_ITEMSIZE = 0x28910, // SAME 0x288B8
EG_SQ_PSTMP_RING_ITEMSIZE = 0x28914, // SAME 0x288BC
EG_SQ_GS_VERT_ITEMSIZE = 0x2891C, // SAME 0x288C8
EG_SQ_GS_VERT_ITEMSIZE_1 = 0x28920, //
EG_SQ_GS_VERT_ITEMSIZE_2 = 0x28924, //
EG_SQ_GS_VERT_ITEMSIZE_3 = 0x28928, //
EG_SQ_GSVS_RING_OFFSET_1 = 0x2892C, //
EG_SQ_GSVS_RING_OFFSET_2 = 0x28930, //
EG_SQ_GSVS_RING_OFFSET_3 = 0x28934, //
EG_SQ_ALU_CONST_CACHE_PS_0 = 0x28940, // SAME
EG_SQ_ALU_CONST_CACHE_PS_1 = 0x28944, // SAME
EG_SQ_ALU_CONST_CACHE_PS_2 = 0x28948, // SAME
EG_SQ_ALU_CONST_CACHE_PS_3 = 0x2894C, // SAME
EG_SQ_ALU_CONST_CACHE_PS_4 = 0x28950, // SAME
EG_SQ_ALU_CONST_CACHE_PS_5 = 0x28954, // SAME
EG_SQ_ALU_CONST_CACHE_PS_6 = 0x28958, // SAME
EG_SQ_ALU_CONST_CACHE_PS_7 = 0x2895C, // SAME
EG_SQ_ALU_CONST_CACHE_PS_8 = 0x28960, // SAME
EG_SQ_ALU_CONST_CACHE_PS_9 = 0x28964, // SAME
EG_SQ_ALU_CONST_CACHE_PS_10 = 0x28968, // SAME
EG_SQ_ALU_CONST_CACHE_PS_11 = 0x2896C, // SAME
EG_SQ_ALU_CONST_CACHE_PS_12 = 0x28970, // SAME
EG_SQ_ALU_CONST_CACHE_PS_13 = 0x28974, // SAME
EG_SQ_ALU_CONST_CACHE_PS_14 = 0x28978, // SAME
EG_SQ_ALU_CONST_CACHE_PS_15 = 0x2897C, // SAME
EG_SQ_ALU_CONST_CACHE_VS_0 = 0x28980, // SAME
EG_SQ_ALU_CONST_CACHE_VS_1 = 0x28984, // SAME
EG_SQ_ALU_CONST_CACHE_VS_2 = 0x28988, // SAME
EG_SQ_ALU_CONST_CACHE_VS_3 = 0x2898C, // SAME
EG_SQ_ALU_CONST_CACHE_VS_4 = 0x28990, // SAME
EG_SQ_ALU_CONST_CACHE_VS_5 = 0x28994, // SAME
EG_SQ_ALU_CONST_CACHE_VS_6 = 0x28998, // SAME
EG_SQ_ALU_CONST_CACHE_VS_7 = 0x2899C, // SAME
EG_SQ_ALU_CONST_CACHE_VS_8 = 0x289A0, // SAME
EG_SQ_ALU_CONST_CACHE_VS_9 = 0x289A4, // SAME
EG_SQ_ALU_CONST_CACHE_VS_10 = 0x289A8, // SAME
EG_SQ_ALU_CONST_CACHE_VS_11 = 0x289AC, // SAME
EG_SQ_ALU_CONST_CACHE_VS_12 = 0x289B0, // SAME
EG_SQ_ALU_CONST_CACHE_VS_13 = 0x289B4, // SAME
EG_SQ_ALU_CONST_CACHE_VS_14 = 0x289B8, // SAME
EG_SQ_ALU_CONST_CACHE_VS_15 = 0x289BC, // SAME
EG_SQ_ALU_CONST_CACHE_GS_0 = 0x289C0, // SAME
EG_SQ_ALU_CONST_CACHE_GS_1 = 0x289C4, // SAME
EG_SQ_ALU_CONST_CACHE_GS_2 = 0x289C8, // SAME
EG_SQ_ALU_CONST_CACHE_GS_3 = 0x289CC, // SAME
EG_SQ_ALU_CONST_CACHE_GS_4 = 0x289D0, // SAME
EG_SQ_ALU_CONST_CACHE_GS_5 = 0x289D4, // SAME
EG_SQ_ALU_CONST_CACHE_GS_6 = 0x289D8, // SAME
EG_SQ_ALU_CONST_CACHE_GS_7 = 0x289DC, // SAME
EG_SQ_ALU_CONST_CACHE_GS_8 = 0x289E0, // SAME
EG_SQ_ALU_CONST_CACHE_GS_9 = 0x289E4, // SAME
EG_SQ_ALU_CONST_CACHE_GS_10 = 0x289E8, // SAME
EG_SQ_ALU_CONST_CACHE_GS_11 = 0x289EC, // SAME
EG_SQ_ALU_CONST_CACHE_GS_12 = 0x289F0, // SAME
EG_SQ_ALU_CONST_CACHE_GS_13 = 0x289F4, // SAME
EG_SQ_ALU_CONST_CACHE_GS_14 = 0x289F8, // SAME
EG_SQ_ALU_CONST_CACHE_GS_15 = 0x289FC, // SAME
EG_SQ_ALU_CONST_CACHE_HS_0 = 0x28F00, //
EG_SQ_ALU_CONST_CACHE_HS_1 = 0x28F04, //
EG_SQ_ALU_CONST_CACHE_HS_2 = 0x28F08, //
EG_SQ_ALU_CONST_CACHE_HS_3 = 0x28F0C, //
EG_SQ_ALU_CONST_CACHE_HS_4 = 0x28F10, //
EG_SQ_ALU_CONST_CACHE_HS_5 = 0x28F14, //
EG_SQ_ALU_CONST_CACHE_HS_6 = 0x28F18, //
EG_SQ_ALU_CONST_CACHE_HS_7 = 0x28F1C, //
EG_SQ_ALU_CONST_CACHE_HS_8 = 0x28F20, //
EG_SQ_ALU_CONST_CACHE_HS_9 = 0x28F24, //
EG_SQ_ALU_CONST_CACHE_HS_10 = 0x28F28, //
EG_SQ_ALU_CONST_CACHE_HS_11 = 0x28F2C, //
EG_SQ_ALU_CONST_CACHE_HS_12 = 0x28F30, //
EG_SQ_ALU_CONST_CACHE_HS_13 = 0x28F34, //
EG_SQ_ALU_CONST_CACHE_HS_14 = 0x28F38, //
EG_SQ_ALU_CONST_CACHE_HS_15 = 0x28F3C, //
EG_SQ_ALU_CONST_CACHE_LS_0 = 0x28F40, //
EG_SQ_ALU_CONST_CACHE_LS_1 = 0x28F44, //
EG_SQ_ALU_CONST_CACHE_LS_2 = 0x28F48, //
EG_SQ_ALU_CONST_CACHE_LS_3 = 0x28F4C, //
EG_SQ_ALU_CONST_CACHE_LS_4 = 0x28F50, //
EG_SQ_ALU_CONST_CACHE_LS_5 = 0x28F54, //
EG_SQ_ALU_CONST_CACHE_LS_6 = 0x28F58, //
EG_SQ_ALU_CONST_CACHE_LS_7 = 0x28F5C, //
EG_SQ_ALU_CONST_CACHE_LS_8 = 0x28F60, //
EG_SQ_ALU_CONST_CACHE_LS_9 = 0x28F64, //
EG_SQ_ALU_CONST_CACHE_LS_10 = 0x28F68, //
EG_SQ_ALU_CONST_CACHE_LS_11 = 0x28F6C, //
EG_SQ_ALU_CONST_CACHE_LS_12 = 0x28F70, //
EG_SQ_ALU_CONST_CACHE_LS_13 = 0x28F74, //
EG_SQ_ALU_CONST_CACHE_LS_14 = 0x28F78, //
EG_SQ_ALU_CONST_CACHE_LS_15 = 0x28F7C, //
EG_SQ_ALU_CONST_BUFFER_SIZE_PS_0 = 0x28140,
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_0 = 0x28F80, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_1 = 0x28F84, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_2 = 0x28F88, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_3 = 0x28F8C, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_4 = 0x28F90, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_5 = 0x28F94, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_6 = 0x28F98, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_7 = 0x28F9C, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_8 = 0x28FA0, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_9 = 0x28FA4, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_10 = 0x28FA8, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_11 = 0x28FAC, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_12 = 0x28FB0, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_13 = 0x28FB4, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_14 = 0x28FB8, //
EG_SQ_ALU_CONST_BUFFER_SIZE_HS_15 = 0x28FBC, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_0 = 0x28FC0, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_1 = 0x28FC4, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_2 = 0x28FC8, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_3 = 0x28FCC, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_4 = 0x28FD0, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_5 = 0x28FD4, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_6 = 0x28FD8, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_7 = 0x28FDC, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_8 = 0x28FE0, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_9 = 0x28FE4, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_10 = 0x28FE8, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_11 = 0x28FEC, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_12 = 0x28FF0, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_13 = 0x28FF4, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_14 = 0x28FF8, //
EG_SQ_ALU_CONST_BUFFER_SIZE_LS_15 = 0x28FFC, //
/* Registers from SPI block: */
EG_SPI_VS_OUT_ID_0 = 0x2861C, // SAME 0x28614
EG_SPI_VS_OUT_ID_1 = 0x28620, // SAME 0x28618
EG_SPI_VS_OUT_ID_2 = 0x28624, // SAME 0x2861C
EG_SPI_VS_OUT_ID_3 = 0x28628, // SAME 0x28620
EG_SPI_VS_OUT_ID_4 = 0x2862C, // SAME 0x28624
EG_SPI_VS_OUT_ID_5 = 0x28630, // SAME 0x28628
EG_SPI_VS_OUT_ID_6 = 0x28634, // SAME 0x2862C
EG_SPI_VS_OUT_ID_7 = 0x28638, // SAME 0x28630
EG_SPI_VS_OUT_ID_8 = 0x2863C, // SAME 0x28634
EG_SPI_VS_OUT_ID_9 = 0x28640, // SAME 0x28638
EG_SPI_PS_INPUT_CNTL_0 = 0x28644, // SAME
EG_SPI_PS_INPUT_CNTL_1 = 0x28648, // SAME
EG_SPI_PS_INPUT_CNTL_2 = 0x2864C, // SAME
EG_SPI_PS_INPUT_CNTL_3 = 0x28650, // SAME
EG_SPI_PS_INPUT_CNTL_4 = 0x28654, // SAME
EG_SPI_PS_INPUT_CNTL_5 = 0x28658, // SAME
EG_SPI_PS_INPUT_CNTL_6 = 0x2865C, // SAME
EG_SPI_PS_INPUT_CNTL_7 = 0x28660, // SAME
EG_SPI_PS_INPUT_CNTL_8 = 0x28664, // SAME
EG_SPI_PS_INPUT_CNTL_9 = 0x28668, // SAME
EG_SPI_PS_INPUT_CNTL_10 = 0x2866C, // SAME
EG_SPI_PS_INPUT_CNTL_11 = 0x28670, // SAME
EG_SPI_PS_INPUT_CNTL_12 = 0x28674, // SAME
EG_SPI_PS_INPUT_CNTL_13 = 0x28678, // SAME
EG_SPI_PS_INPUT_CNTL_14 = 0x2867C, // SAME
EG_SPI_PS_INPUT_CNTL_15 = 0x28680, // SAME
EG_SPI_PS_INPUT_CNTL_16 = 0x28684, // SAME
EG_SPI_PS_INPUT_CNTL_17 = 0x28688, // SAME
EG_SPI_PS_INPUT_CNTL_18 = 0x2868C, // SAME
EG_SPI_PS_INPUT_CNTL_19 = 0x28690, // SAME
EG_SPI_PS_INPUT_CNTL_20 = 0x28694, // SAME
EG_SPI_PS_INPUT_CNTL_21 = 0x28698, // SAME
EG_SPI_PS_INPUT_CNTL_22 = 0x2869C, // SAME
EG_SPI_PS_INPUT_CNTL_23 = 0x286A0, // SAME
EG_SPI_PS_INPUT_CNTL_24 = 0x286A4, // SAME
EG_SPI_PS_INPUT_CNTL_25 = 0x286A8, // SAME
EG_SPI_PS_INPUT_CNTL_26 = 0x286AC, // SAME
EG_SPI_PS_INPUT_CNTL_27 = 0x286B0, // SAME
EG_SPI_PS_INPUT_CNTL_28 = 0x286B4, // SAME
EG_SPI_PS_INPUT_CNTL_29 = 0x286B8, // SAME
EG_SPI_PS_INPUT_CNTL_30 = 0x286BC, // SAME
EG_SPI_PS_INPUT_CNTL_31 = 0x286C0, // SAME
EG_SPI_VS_OUT_CONFIG = 0x286C4, // SAME
EG_SPI_THREAD_GROUPING = 0x286C8, // DIFF
EG_SPI_PS_IN_CONTROL_0 = 0x286CC, // SAME
EG_SPI_PS_IN_CONTROL_1 = 0x286D0, // SAME
EG_SPI_INTERP_CONTROL_0 = 0x286D4, // SAME
EG_SPI_INPUT_Z = 0x286D8, // SAME
EG_SPI_FOG_CNTL = 0x286DC, // SAME
EG_SPI_BARYC_CNTL = 0x286E0, //
EG_SPI_PS_IN_CONTROL_2 = 0x286E4, //
EG_SPI_COMPUTE_INPUT_CNTL = 0x286E8, //
EG_SPI_COMPUTE_NUM_THREAD_X = 0x286EC, //
EG_SPI_COMPUTE_NUM_THREAD_Y = 0x286F0, //
EG_SPI_COMPUTE_NUM_THREAD_Z = 0x286F4, //
/* Registers from SX block: */
EG_SX_MISC = 0x28350, // SAME
EG_SX_SURFACE_SYNC = 0x28354, // DIFF
EG_SX_ALPHA_TEST_CONTROL = 0x28410, // SAME
EG_SX_ALPHA_REF = 0x28438, // SAME
/* Registers from DB block: */
EG_DB_RENDER_CONTROL = 0x28000, // DIFF 0x28D0C
EG_DB_COUNT_CONTROL = 0x28004, //
EG_DB_DEPTH_VIEW = 0x28008, // DIFF 0x28004
EG_DB_RENDER_OVERRIDE = 0x2800C, // DIFF 0x28D10
EG_DB_RENDER_OVERRIDE2 = 0x28010, //
EG_DB_HTILE_DATA_BASE = 0x28014, // SAME
EG_DB_STENCIL_CLEAR = 0x28028, // SAME
EG_DB_DEPTH_CLEAR = 0x2802C, // SAME
EG_DB_Z_INFO = 0x28040, //
EG_DB_STENCIL_INFO = 0x28044, //
EG_DB_Z_READ_BASE = 0x28048, //
EG_DB_STENCIL_READ_BASE = 0x2804C, //
EG_DB_Z_WRITE_BASE = 0x28050, //
EG_DB_STENCIL_WRITE_BASE = 0x28054, //
EG_DB_DEPTH_SIZE = 0x28058, // DIFF 0x28000
EG_DB_DEPTH_SLICE = 0x2805C, //
EG_DB_STENCILREFMASK = 0x28430, // SAME
EG_DB_STENCILREFMASK_BF = 0x28434, // SAME
EG_DB_DEPTH_CONTROL = 0x28800, // SAME
EG_DB_SHADER_CONTROL = 0x2880C, // DIFF
EG_DB_HTILE_SURFACE = 0x28ABC, // SAME 0x28D24
EG_DB_SRESULTS_COMPARE_STATE0 = 0x28AC0, // SAME 0x28D28
EG_DB_SRESULTS_COMPARE_STATE1 = 0x28AC4, // SAME 0x28D2C
EG_DB_PRELOAD_CONTROL = 0x28AC8, // SAME 0x28D30
EG_DB_ALPHA_TO_MASK = 0x28B70, // SAME 0x28D44
/* Registers from CB block: */
EG_CB_TARGET_MASK = 0x28238, // SAME
EG_CB_SHADER_MASK = 0x2823C, // SAME
EG_CB_BLEND_RED = 0x28414, // SAME
EG_CB_BLEND_GREEN = 0x28418, // SAME
EG_CB_BLEND_BLUE = 0x2841C, // SAME
EG_CB_BLEND_ALPHA = 0x28420, // SAME
EG_CB_BLEND0_CONTROL = 0x28780, // DIFF
EG_CB_BLEND1_CONTROL = 0x28784, // DIFF
EG_CB_BLEND2_CONTROL = 0x28788, // DIFF
EG_CB_BLEND3_CONTROL = 0x2878C, // DIFF
EG_CB_BLEND4_CONTROL = 0x28790, // DIFF
EG_CB_BLEND5_CONTROL = 0x28794, // DIFF
EG_CB_BLEND6_CONTROL = 0x28798, // DIFF
EG_CB_BLEND7_CONTROL = 0x2879C, // DIFF
EG_CB_COLOR_CONTROL = 0x28808, // DIFF
EG_CB_IMMED0_BASE = 0x28B9C, //
EG_CB_IMMED1_BASE = 0x28BA0, //
EG_CB_IMMED2_BASE = 0x28BA4, //
EG_CB_IMMED3_BASE = 0x28BA8, //
EG_CB_IMMED4_BASE = 0x28BAC, //
EG_CB_IMMED5_BASE = 0x28BB0, //
EG_CB_IMMED6_BASE = 0x28BB4, //
EG_CB_IMMED7_BASE = 0x28BB8, //
EG_CB_IMMED8_BASE = 0x28BBC, //
EG_CB_IMMED9_BASE = 0x28BC0, //
EG_CB_IMMED10_BASE = 0x28BC4, //
EG_CB_IMMED11_BASE = 0x28BC8, //
EG_CB_CLRCMP_CONTROL = 0x28C40, // SAME 0x28C30
EG_CB_CLRCMP_SRC = 0x28C44, // SAME 0x28C34
EG_CB_CLRCMP_DST = 0x28C48, // SAME 0x28C38
EG_CB_CLRCMP_MSK = 0x28C4C, // SAME 0x28C3C
EG_CB_COLOR0_BASE = 0x28C60, // SAME 0x28040
EG_CB_COLOR0_PITCH = 0x28C64, //
EG_CB_COLOR0_SLICE = 0x28C68, //
EG_CB_COLOR0_VIEW = 0x28C6C, // SAME 0x28080
EG_CB_COLOR0_INFO = 0x28C70, // DIFF 0x280A0
EG_CB_COLOR0_ATTRIB = 0x28C74, //
EG_CB_COLOR0_DIM = 0x28C78, //
EG_CB_COLOR0_CMASK = 0x28C7C, //
EG_CB_COLOR0_CMASK_SLICE = 0x28C80, //
EG_CB_COLOR0_FMASK = 0x28C84, //
EG_CB_COLOR0_FMASK_SLICE = 0x28C88, //
EG_CB_COLOR0_CLEAR_WORD0 = 0x28C8C, //
EG_CB_COLOR0_CLEAR_WORD1 = 0x28C90, //
EG_CB_COLOR0_CLEAR_WORD2 = 0x28C94, //
EG_CB_COLOR0_CLEAR_WORD3 = 0x28C98, //
EG_CB_COLOR1_BASE = 0x28C9C, // SAME 0x28044
EG_CB_COLOR1_PITCH = 0x28CA0, //
EG_CB_COLOR1_SLICE = 0x28CA4, //
EG_CB_COLOR1_VIEW = 0x28CA8, // SAME 0x28084
EG_CB_COLOR1_INFO = 0x28CAC, // DIFF 0x280A4
EG_CB_COLOR1_ATTRIB = 0x28CB0, //
EG_CB_COLOR1_DIM = 0x28CB4, //
EG_CB_COLOR1_CMASK = 0x28CB8, //
EG_CB_COLOR1_CMASK_SLICE = 0x28CBC, //
EG_CB_COLOR1_FMASK = 0x28CC0, //
EG_CB_COLOR1_FMASK_SLICE = 0x28CC4, //
EG_CB_COLOR1_CLEAR_WORD0 = 0x28CC8, //
EG_CB_COLOR1_CLEAR_WORD1 = 0x28CCC, //
EG_CB_COLOR1_CLEAR_WORD2 = 0x28CD0, //
EG_CB_COLOR1_CLEAR_WORD3 = 0x28CD4, //
EG_CB_COLOR2_BASE = 0x28CD8, // SAME 0x28048
EG_CB_COLOR2_PITCH = 0x28CDC, //
EG_CB_COLOR2_SLICE = 0x28CE0, //
EG_CB_COLOR2_VIEW = 0x28CE4, // SAME 0x28088
EG_CB_COLOR2_INFO = 0x28CE8, // DIFF 0x280A8
EG_CB_COLOR2_ATTRIB = 0x28CEC, //
EG_CB_COLOR2_DIM = 0x28CF0, //
EG_CB_COLOR2_CMASK = 0x28CF4, //
EG_CB_COLOR2_CMASK_SLICE = 0x28CF8, //
EG_CB_COLOR2_FMASK = 0x28CFC, //
EG_CB_COLOR2_FMASK_SLICE = 0x28D00, //
EG_CB_COLOR2_CLEAR_WORD0 = 0x28D04, //
EG_CB_COLOR2_CLEAR_WORD1 = 0x28D08, //
EG_CB_COLOR2_CLEAR_WORD2 = 0x28D0C, //
EG_CB_COLOR2_CLEAR_WORD3 = 0x28D10, //
EG_CB_COLOR3_BASE = 0x28D14, // SAME 0x2804C
EG_CB_COLOR3_PITCH = 0x28D18, //
EG_CB_COLOR3_SLICE = 0x28D1C, //
EG_CB_COLOR3_VIEW = 0x28D20, // SAME 0x2808C
EG_CB_COLOR3_INFO = 0x28D24, // DIFF 0x280AC
EG_CB_COLOR3_ATTRIB = 0x28D28, //
EG_CB_COLOR3_DIM = 0x28D2C, //
EG_CB_COLOR3_CMASK = 0x28D30, //
EG_CB_COLOR3_CMASK_SLICE = 0x28D34, //
EG_CB_COLOR3_FMASK = 0x28D38, //
EG_CB_COLOR3_FMASK_SLICE = 0x28D3C, //
EG_CB_COLOR3_CLEAR_WORD0 = 0x28D40, //
EG_CB_COLOR3_CLEAR_WORD1 = 0x28D44, //
EG_CB_COLOR3_CLEAR_WORD2 = 0x28D48, //
EG_CB_COLOR3_CLEAR_WORD3 = 0x28D4C, //
EG_CB_COLOR4_BASE = 0x28D50, // SAME 0x28050
EG_CB_COLOR4_PITCH = 0x28D54, //
EG_CB_COLOR4_SLICE = 0x28D58, //
EG_CB_COLOR4_VIEW = 0x28D5C, // SAME 0x28090
EG_CB_COLOR4_INFO = 0x28D60, // DIFF 0x280B0
EG_CB_COLOR4_ATTRIB = 0x28D64, //
EG_CB_COLOR4_DIM = 0x28D68, //
EG_CB_COLOR4_CMASK = 0x28D6C, //
EG_CB_COLOR4_CMASK_SLICE = 0x28D70, //
EG_CB_COLOR4_FMASK = 0x28D74, //
EG_CB_COLOR4_FMASK_SLICE = 0x28D78, //
EG_CB_COLOR4_CLEAR_WORD0 = 0x28D7C, //
EG_CB_COLOR4_CLEAR_WORD1 = 0x28D80, //
EG_CB_COLOR4_CLEAR_WORD2 = 0x28D84, //
EG_CB_COLOR4_CLEAR_WORD3 = 0x28D88, //
EG_CB_COLOR5_BASE = 0x28D8C, // SAME 0x28054
EG_CB_COLOR5_PITCH = 0x28D90, //
EG_CB_COLOR5_SLICE = 0x28D94, //
EG_CB_COLOR5_VIEW = 0x28D98, // SAME 0x28094
EG_CB_COLOR5_INFO = 0x28D9C, // DIFF 0x280B4
EG_CB_COLOR5_ATTRIB = 0x28DA0, //
EG_CB_COLOR5_DIM = 0x28DA4, //
EG_CB_COLOR5_CMASK = 0x28DA8, //
EG_CB_COLOR5_CMASK_SLICE = 0x28DAC, //
EG_CB_COLOR5_FMASK = 0x28DB0, //
EG_CB_COLOR5_FMASK_SLICE = 0x28DB4, //
EG_CB_COLOR5_CLEAR_WORD0 = 0x28DB8, //
EG_CB_COLOR5_CLEAR_WORD1 = 0x28DBC, //
EG_CB_COLOR5_CLEAR_WORD2 = 0x28DC0, //
EG_CB_COLOR5_CLEAR_WORD3 = 0x28DC4, //
EG_CB_COLOR6_BASE = 0x28DC8, // SAME 0x28058
EG_CB_COLOR6_PITCH = 0x28DCC, //
EG_CB_COLOR6_SLICE = 0x28DD0, //
EG_CB_COLOR6_VIEW = 0x28DD4, // SAME 0x28098
EG_CB_COLOR6_INFO = 0x28DD8, // DIFF 0x280B8
EG_CB_COLOR6_ATTRIB = 0x28DDC, //
EG_CB_COLOR6_DIM = 0x28DE0, //
EG_CB_COLOR6_CMASK = 0x28DE4, //
EG_CB_COLOR6_CMASK_SLICE = 0x28DE8, //
EG_CB_COLOR6_FMASK = 0x28DEC, //
EG_CB_COLOR6_FMASK_SLICE = 0x28DF0, //
EG_CB_COLOR6_CLEAR_WORD0 = 0x28DF4, //
EG_CB_COLOR6_CLEAR_WORD1 = 0x28DF8, //
EG_CB_COLOR6_CLEAR_WORD2 = 0x28DFC, //
EG_CB_COLOR6_CLEAR_WORD3 = 0x28E00, //
EG_CB_COLOR7_BASE = 0x28E04, // SAME 0x2805C
EG_CB_COLOR7_PITCH = 0x28E08, //
EG_CB_COLOR7_SLICE = 0x28E0C, //
EG_CB_COLOR7_VIEW = 0x28E10, // SAME 0x2809C
EG_CB_COLOR7_INFO = 0x28E14, // DIFF 0x280BC
EG_CB_COLOR7_ATTRIB = 0x28E18, //
EG_CB_COLOR7_DIM = 0x28E1C, //
EG_CB_COLOR7_CMASK = 0x28E20, //
EG_CB_COLOR7_CMASK_SLICE = 0x28E24, //
EG_CB_COLOR7_FMASK = 0x28E28, //
EG_CB_COLOR7_FMASK_SLICE = 0x28E2C, //
EG_CB_COLOR7_CLEAR_WORD0 = 0x28E30, //
EG_CB_COLOR7_CLEAR_WORD1 = 0x28E34, //
EG_CB_COLOR7_CLEAR_WORD2 = 0x28E38, //
EG_CB_COLOR7_CLEAR_WORD3 = 0x28E3C, //
EG_CB_COLOR8_BASE = 0x28E40, //
EG_CB_COLOR8_PITCH = 0x28E44, //
EG_CB_COLOR8_SLICE = 0x28E48, //
EG_CB_COLOR8_VIEW = 0x28E4C, //
EG_CB_COLOR8_INFO = 0x28E50, //
EG_CB_COLOR8_ATTRIB = 0x28E54, //
EG_CB_COLOR8_DIM = 0x28E58, //
EG_CB_COLOR9_BASE = 0x28E5C, //
EG_CB_COLOR9_PITCH = 0x28E60, //
EG_CB_COLOR9_SLICE = 0x28E64, //
EG_CB_COLOR9_VIEW = 0x28E68, //
EG_CB_COLOR9_INFO = 0x28E6C, //
EG_CB_COLOR9_ATTRIB = 0x28E70, //
EG_CB_COLOR9_DIM = 0x28E74, //
EG_CB_COLOR10_BASE = 0x28E78, //
EG_CB_COLOR10_PITCH = 0x28E7C, //
EG_CB_COLOR10_SLICE = 0x28E80, //
EG_CB_COLOR10_VIEW = 0x28E84, //
EG_CB_COLOR10_INFO = 0x28E88, //
EG_CB_COLOR10_ATTRIB = 0x28E8C, //
EG_CB_COLOR10_DIM = 0x28E90, //
EG_CB_COLOR11_BASE = 0x28E94, //
EG_CB_COLOR11_PITCH = 0x28E98, //
EG_CB_COLOR11_SLICE = 0x28E9C, //
EG_CB_COLOR11_VIEW = 0x28EA0, //
EG_CB_COLOR11_INFO = 0x28EA4, //
EG_CB_COLOR11_ATTRIB = 0x28EA8, //
EG_CB_COLOR11_DIM = 0x28EAC, //
/* Registers from CP block: */
EG_COHER_DEST_BASE_0 = 0x28248, // SAME
EG_COHER_DEST_BASE_1 = 0x2824C, // SAME
EG_CP_PERFMON_CNTX_CNTL = 0x28358, //
/* Config: */
EG_SPI_CONFIG_CNTL = 0x9100, // DIFF
EG_SPI_CONFIG_CNTL_1 = 0x913C, // DIFF
EG_CP_PERFMON_CNTL = 0x87FC, // SAME
EG_SQ_MS_FIFO_SIZES = 0x8CF0, // SAME
EG_SQ_CONFIG = 0x8C00, // DIFF
EG_SQ_GPR_RESOURCE_MGMT_1 = 0x8C04, // SAME
EG_SQ_GPR_RESOURCE_MGMT_2 = 0x8C08, // SAME
EG_SQ_THREAD_RESOURCE_MGMT = 0x8C18, // SAME 0x8C0C,
EG_SQ_STACK_RESOURCE_MGMT_1 = 0x8C20, // SAME 0x8C10,
EG_SQ_STACK_RESOURCE_MGMT_2 = 0x8C24, // SAME 0x8C14,
EG_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ = 0x8D8C, // DIFF
EG_SQ_LDS_RESOURCE_MGMT = 0x8E2C, //
EG_SQ_GPR_RESOURCE_MGMT_3 = 0x8C0C, //
EG_SQ_STACK_RESOURCE_MGMT_3 = 0x8C28, //
EG_SQ_THREAD_RESOURCE_MGMT_2 = 0x8C1C, //
EG_VGT_CACHE_INVALIDATION = 0x88C4, // DIFF
EG_VGT_GS_VERTEX_REUSE = 0x88D4, // SAME
EG_PA_SC_FORCE_EOV_MAX_CNTS = 0x8B24, // SAME
EG_PA_SC_LINE_STIPPLE_STATE = 0x8B10, // SAME
EG_PA_CL_ENHANCE = 0x8A14, // SAME
/* Tex border color */
EG_TD_PS_BORDER_COLOR_RED = 0xA404,
EG_TD_PS_BORDER_COLOR_GREEN = 0xA408,
EG_TD_PS_BORDER_COLOR_BLUE = 0xA40C,
EG_TD_PS_BORDER_COLOR_ALPHA = 0xA410,
/* const */
EG_SQ_VTX_CONSTANT_WORD0_0 = 0x30000, // 0x38000
};
#endif /* _EVERGREEN_OFF_H_ */

193
src/mesa/drivers/dri/r600/evergreen_oglprog.c
View file

@ -1,193 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#include <string.h>
#include "main/glheader.h"
#include "main/imports.h"
#include "program/program.h"
#include "tnl/tnl.h"
#include "r600_context.h"
#include "r600_emit.h"
#include "evergreen_oglprog.h"
#include "evergreen_fragprog.h"
#include "evergreen_vertprog.h"
static void evergreen_freeVertProgCache(struct gl_context *ctx, struct r700_vertex_program_cont *cache)
{
struct evergreen_vertex_program *tmp, *vp = (struct evergreen_vertex_program *) cache->progs;
while (vp) {
tmp = vp->next;
/* Release DMA region */
r600DeleteShader(ctx, vp->shaderbo);
if(NULL != vp->constbo0)
{
r600DeleteShader(ctx, vp->constbo0);
}
/* Clean up */
Clean_Up_Assembler(&(vp->r700AsmCode));
Clean_Up_Shader(&(vp->r700Shader));
_mesa_reference_vertprog(ctx, &vp->mesa_program, NULL);
free(vp);
vp = tmp;
}
}
static struct gl_program *evergreenNewProgram(struct gl_context * ctx,
GLenum target,
GLuint id)
{
struct gl_program *pProgram = NULL;
struct evergreen_vertex_program_cont *vpc;
struct evergreen_fragment_program *fp;
radeon_print(RADEON_SHADER, RADEON_VERBOSE,
"%s %u, %u\n", __func__, target, id);
switch (target)
{
case GL_VERTEX_STATE_PROGRAM_NV:
case GL_VERTEX_PROGRAM_ARB:
vpc = CALLOC_STRUCT(evergreen_vertex_program_cont);
pProgram = _mesa_init_vertex_program(ctx,
&vpc->mesa_program,
target,
id);
break;
case GL_FRAGMENT_PROGRAM_NV:
case GL_FRAGMENT_PROGRAM_ARB:
fp = CALLOC_STRUCT(evergreen_fragment_program);
pProgram = _mesa_init_fragment_program(ctx,
&fp->mesa_program,
target,
id);
fp->translated = GL_FALSE;
fp->loaded = GL_FALSE;
fp->shaderbo = NULL;
fp->constbo0 = NULL;
break;
default:
_mesa_problem(ctx, "Bad target in evergreenNewProgram");
}
return pProgram;
}
static void evergreenDeleteProgram(struct gl_context * ctx, struct gl_program *prog)
{
struct evergreen_vertex_program_cont *vpc = (struct evergreen_vertex_program_cont *)prog;
struct evergreen_fragment_program * fp;
radeon_print(RADEON_SHADER, RADEON_VERBOSE,
"%s %p\n", __func__, prog);
switch (prog->Target)
{
case GL_VERTEX_STATE_PROGRAM_NV:
case GL_VERTEX_PROGRAM_ARB:
evergreen_freeVertProgCache(ctx, (struct r700_vertex_program_cont *) vpc);
break;
case GL_FRAGMENT_PROGRAM_NV:
case GL_FRAGMENT_PROGRAM_ARB:
fp = (struct evergreen_fragment_program*)prog;
/* Release DMA region */
r600DeleteShader(ctx, fp->shaderbo);
if(NULL != fp->constbo0)
{
r600DeleteShader(ctx, fp->constbo0);
}
/* Clean up */
Clean_Up_Assembler(&(fp->r700AsmCode));
Clean_Up_Shader(&(fp->r700Shader));
break;
default:
_mesa_problem(ctx, "Bad target in evergreenNewProgram");
}
_mesa_delete_program(ctx, prog);
}
static GLboolean
evergreenProgramStringNotify(struct gl_context * ctx, GLenum target, struct gl_program *prog)
{
struct evergreen_vertex_program_cont *vpc = (struct evergreen_vertex_program_cont *)prog;
struct evergreen_fragment_program * fp = (struct evergreen_fragment_program*)prog;
switch (target) {
case GL_VERTEX_PROGRAM_ARB:
evergreen_freeVertProgCache(ctx, (struct r700_vertex_program_cont *) vpc);
vpc->progs = NULL;
break;
case GL_FRAGMENT_PROGRAM_ARB:
r600DeleteShader(ctx, fp->shaderbo);
if(NULL != fp->constbo0)
{
r600DeleteShader(ctx, fp->constbo0);
fp->constbo0 = NULL;
}
Clean_Up_Assembler(&(fp->r700AsmCode));
Clean_Up_Shader(&(fp->r700Shader));
fp->translated = GL_FALSE;
fp->loaded = GL_FALSE;
fp->shaderbo = NULL;
break;
}
/* XXX check if program is legal, within limits */
return GL_TRUE;
}
static GLboolean evergreenIsProgramNative(struct gl_context * ctx, GLenum target, struct gl_program *prog)
{
return GL_TRUE;
}
void evergreenInitShaderFuncs(struct dd_function_table *functions)
{
functions->NewProgram = evergreenNewProgram;
functions->DeleteProgram = evergreenDeleteProgram;
functions->ProgramStringNotify = evergreenProgramStringNotify;
functions->IsProgramNative = evergreenIsProgramNative;
}

33
src/mesa/drivers/dri/r600/evergreen_oglprog.h
View file

@ -1,33 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_OGLPROG_H_
#define _EVERGREEN_OGLPROG_H_
#include "r600_context.h"
extern void evergreenInitShaderFuncs(struct dd_function_table *functions);
#endif /*_EVERGREEN_OGLPROG_H_*/

971
src/mesa/drivers/dri/r600/evergreen_render.c
View file

@ -1,971 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#include "main/glheader.h"
#include "main/state.h"
#include "main/imports.h"
#include "main/enums.h"
#include "main/macros.h"
#include "main/context.h"
#include "main/dd.h"
#include "main/simple_list.h"
#include "main/api_arrayelt.h"
#include "swrast/swrast.h"
#include "swrast_setup/swrast_setup.h"
#include "vbo/vbo.h"
#include "tnl/tnl.h"
#include "tnl/t_vp_build.h"
#include "tnl/t_context.h"
#include "tnl/t_vertex.h"
#include "vbo/vbo_context.h"
#include "r600_context.h"
#include "r600_cmdbuf.h"
#include "evergreen_fragprog.h"
#include "evergreen_vertprog.h"
#include "evergreen_state.h"
#include "evergreen_tex.h"
#include "radeon_buffer_objects.h"
#include "radeon_common_context.h"
static unsigned int evergreenPrimitiveType(int prim) //same
{
switch (prim & PRIM_MODE_MASK)
{
case GL_POINTS:
return DI_PT_POINTLIST;
break;
case GL_LINES:
return DI_PT_LINELIST;
break;
case GL_LINE_STRIP:
return DI_PT_LINESTRIP;
break;
case GL_LINE_LOOP:
return DI_PT_LINELOOP;
break;
case GL_TRIANGLES:
return DI_PT_TRILIST;
break;
case GL_TRIANGLE_STRIP:
return DI_PT_TRISTRIP;
break;
case GL_TRIANGLE_FAN:
return DI_PT_TRIFAN;
break;
case GL_QUADS:
return DI_PT_QUADLIST;
break;
case GL_QUAD_STRIP:
return DI_PT_QUADSTRIP;
break;
case GL_POLYGON:
return DI_PT_POLYGON;
break;
default:
assert(0);
return -1;
break;
}
}
static int evergreenNumVerts(int num_verts, int prim) //same
{
int verts_off = 0;
switch (prim & PRIM_MODE_MASK) {
case GL_POINTS:
verts_off = 0;
break;
case GL_LINES:
verts_off = num_verts % 2;
break;
case GL_LINE_STRIP:
if (num_verts < 2)
verts_off = num_verts;
break;
case GL_LINE_LOOP:
if (num_verts < 2)
verts_off = num_verts;
break;
case GL_TRIANGLES:
verts_off = num_verts % 3;
break;
case GL_TRIANGLE_STRIP:
if (num_verts < 3)
verts_off = num_verts;
break;
case GL_TRIANGLE_FAN:
if (num_verts < 3)
verts_off = num_verts;
break;
case GL_QUADS:
verts_off = num_verts % 4;
break;
case GL_QUAD_STRIP:
if (num_verts < 4)
verts_off = num_verts;
else
verts_off = num_verts % 2;
break;
case GL_POLYGON:
if (num_verts < 3)
verts_off = num_verts;
break;
default:
assert(0);
return -1;
break;
}
return num_verts - verts_off;
}
static void evergreenRunRenderPrimitive(struct gl_context * ctx, int start, int end, int prim,
GLint basevertex) //same
{
context_t *context = EVERGREEN_CONTEXT(ctx);
BATCH_LOCALS(&context->radeon);
int type, total_emit;
int num_indices;
uint32_t vgt_draw_initiator = 0;
uint32_t vgt_index_type = 0;
uint32_t vgt_primitive_type = 0;
uint32_t vgt_num_indices = 0;
type = evergreenPrimitiveType(prim);
num_indices = evergreenNumVerts(end - start, prim);
radeon_print(RADEON_RENDER, RADEON_TRACE,
"%s type %x num_indices %d\n",
__func__, type, num_indices);
if (type < 0 || num_indices <= 0)
return;
SETfield(vgt_primitive_type, type,
VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
if(GL_TRUE != context->ind_buf.is_32bit)
{
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
/* 16-bit indexes are packed in a 32-bit value */
SETfield(vgt_index_type,
#if MESA_BIG_ENDIAN
VGT_DMA_SWAP_32_BIT,
#else
VGT_DMA_SWAP_NONE,
#endif
SWAP_MODE_shift, SWAP_MODE_mask);
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
total_emit = 3 /* VGT_PRIMITIVE_TYPE */
+ 2 /* VGT_INDEX_TYPE */
+ 2 /* NUM_INSTANCES */
+ 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
+ 5 + 2; /* DRAW_INDEX */
BEGIN_BATCH_NO_AUTOSTATE(total_emit);
// prim
R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
R600_OUT_BATCH(vgt_primitive_type);
// index type
R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
R600_OUT_BATCH(vgt_index_type);
// num instances
R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
R600_OUT_BATCH(1);
/* offset */
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
R600_OUT_BATCH(basevertex); //VTX_BASE_VTX_LOC
R600_OUT_BATCH(0); //VTX_START_INST_LOC
// draw packet
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX, 3));
R600_OUT_BATCH(context->ind_buf.bo_offset);
R600_OUT_BATCH(0);
R600_OUT_BATCH(vgt_num_indices);
R600_OUT_BATCH(vgt_draw_initiator);
R600_OUT_BATCH_RELOC(context->ind_buf.bo_offset,
context->ind_buf.bo,
context->ind_buf.bo_offset,
RADEON_GEM_DOMAIN_GTT, 0, 0);
END_BATCH();
COMMIT_BATCH();
}
static void evergreenRunRenderPrimitiveImmediate(struct gl_context * ctx, int start, int end, int prim) //same
{
context_t *context = EVERGREEN_CONTEXT(ctx);
BATCH_LOCALS(&context->radeon);
int type, i;
uint32_t num_indices, total_emit = 0;
uint32_t vgt_draw_initiator = 0;
uint32_t vgt_index_type = 0;
uint32_t vgt_primitive_type = 0;
uint32_t vgt_num_indices = 0;
type = evergreenPrimitiveType(prim);
num_indices = evergreenNumVerts(end - start, prim);
radeon_print(RADEON_RENDER, RADEON_TRACE,
"%s type %x num_indices %d\n",
__func__, type, num_indices);
if (type < 0 || num_indices <= 0)
return;
SETfield(vgt_primitive_type, type,
VGT_PRIMITIVE_TYPE__PRIM_TYPE_shift, VGT_PRIMITIVE_TYPE__PRIM_TYPE_mask);
if (num_indices > 0xffff)
{
SETfield(vgt_index_type, DI_INDEX_SIZE_32_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
else
{
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
/* 16-bit indexes are packed in a 32-bit value */
SETfield(vgt_index_type,
#if MESA_BIG_ENDIAN
VGT_DMA_SWAP_32_BIT,
#else
VGT_DMA_SWAP_NONE,
#endif
SWAP_MODE_shift, SWAP_MODE_mask);
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
if (start == 0)
{
SETfield(vgt_draw_initiator, DI_SRC_SEL_AUTO_INDEX, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
}
else
{
if (num_indices > 0xffff)
{
total_emit += num_indices;
}
else
{
total_emit += (num_indices + 1) / 2;
}
SETfield(vgt_draw_initiator, DI_SRC_SEL_IMMEDIATE, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
}
total_emit += 3 /* VGT_PRIMITIVE_TYPE */
+ 2 /* VGT_INDEX_TYPE */
+ 2 /* NUM_INSTANCES */
+ 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
+ 3; /* DRAW */
BEGIN_BATCH_NO_AUTOSTATE(total_emit);
// prim
R600_OUT_BATCH_REGSEQ(VGT_PRIMITIVE_TYPE, 1);
R600_OUT_BATCH(vgt_primitive_type);
// index type
R600_OUT_BATCH(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
R600_OUT_BATCH(vgt_index_type);
// num instances
R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
R600_OUT_BATCH(1);
/* offset */
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
R600_OUT_BATCH(0); //VTX_BASE_VTX_LOC
R600_OUT_BATCH(0); //VTX_START_INST_LOC
// draw packet
if(start == 0)
{
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
R600_OUT_BATCH(vgt_num_indices);
R600_OUT_BATCH(vgt_draw_initiator);
}
else
{
if (num_indices > 0xffff)
{
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (num_indices + 1)));
R600_OUT_BATCH(vgt_num_indices);
R600_OUT_BATCH(vgt_draw_initiator);
for (i = start; i < (start + num_indices); i++)
{
R600_OUT_BATCH(i);
}
}
else
{
R600_OUT_BATCH(CP_PACKET3(R600_IT_DRAW_INDEX_IMMD, (((num_indices + 1) / 2) + 1)));
R600_OUT_BATCH(vgt_num_indices);
R600_OUT_BATCH(vgt_draw_initiator);
for (i = start; i < (start + num_indices); i += 2)
{
if ((i + 1) == (start + num_indices))
{
R600_OUT_BATCH(i);
}
else
{
R600_OUT_BATCH(((i + 1) << 16) | (i));
}
}
}
}
END_BATCH();
COMMIT_BATCH();
}
#define CONVERT( TYPE, MACRO ) do { \
GLuint i, j, sz; \
sz = input->Size; \
if (input->Normalized) { \
for (i = 0; i < count; i++) { \
const TYPE *in = (TYPE *)src_ptr; \
for (j = 0; j < sz; j++) { \
*dst_ptr++ = MACRO(*in); \
in++; \
} \
src_ptr += stride; \
} \
} else { \
for (i = 0; i < count; i++) { \
const TYPE *in = (TYPE *)src_ptr; \
for (j = 0; j < sz; j++) { \
*dst_ptr++ = (GLfloat)(*in); \
in++; \
} \
src_ptr += stride; \
} \
} \
} while (0)
/**
* Convert attribute data type to float
* If the attribute uses named buffer object replace the bo with newly allocated bo
*/
static void evergreenConvertAttrib(struct gl_context *ctx, int count,
const struct gl_client_array *input,
struct StreamDesc *attr)
{
context_t *context = R700_CONTEXT(ctx);
const GLvoid *src_ptr;
GLboolean mapped_named_bo = GL_FALSE;
GLfloat *dst_ptr;
GLuint stride;
stride = (input->StrideB == 0) ? evergreen_getTypeSize(input->Type) * input->Size : input->StrideB;
/* Convert value for first element only */
if (input->StrideB == 0)
{
count = 1;
}
if (input->BufferObj->Name)
{
if (!input->BufferObj->Pointer)
{
ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
GL_MAP_READ_BIT, input->BufferObj);
mapped_named_bo = GL_TRUE;
}
src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
}
else
{
src_ptr = input->Ptr;
}
radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset,
sizeof(GLfloat) * input->Size * count, 32);
radeon_bo_map(attr->bo, 1);
dst_ptr = (GLfloat *)ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
assert(src_ptr != NULL);
switch (input->Type)
{
case GL_DOUBLE:
CONVERT(GLdouble, (GLfloat));
break;
case GL_UNSIGNED_INT:
CONVERT(GLuint, UINT_TO_FLOAT);
break;
case GL_INT:
CONVERT(GLint, INT_TO_FLOAT);
break;
case GL_UNSIGNED_SHORT:
CONVERT(GLushort, USHORT_TO_FLOAT);
break;
case GL_SHORT:
CONVERT(GLshort, SHORT_TO_FLOAT);
break;
case GL_UNSIGNED_BYTE:
assert(input->Format != GL_BGRA);
CONVERT(GLubyte, UBYTE_TO_FLOAT);
break;
case GL_BYTE:
CONVERT(GLbyte, BYTE_TO_FLOAT);
break;
default:
assert(0);
break;
}
radeon_bo_unmap(attr->bo);
if (mapped_named_bo)
{
ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
}
}
static void evergreenFixupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
GLvoid *src_ptr;
GLuint *out;
int i;
GLboolean mapped_named_bo = GL_FALSE;
if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
{
ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
GL_MAP_READ_BIT, mesa_ind_buf->obj);
mapped_named_bo = GL_TRUE;
assert(mesa_ind_buf->obj->Pointer != NULL);
}
src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
if (mesa_ind_buf->type == GL_UNSIGNED_BYTE)
{
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
GLubyte *in = (GLubyte *)src_ptr;
radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
&context->ind_buf.bo_offset, size, 4);
radeon_bo_map(context->ind_buf.bo, 1);
assert(context->ind_buf.bo->ptr != NULL);
out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
{
*out++ = in[i] | in[i + 1] << 16;
}
if (i < mesa_ind_buf->count)
{
*out++ = in[i];
}
radeon_bo_unmap(context->ind_buf.bo);
#if MESA_BIG_ENDIAN
}
else
{ /* if (mesa_ind_buf->type == GL_UNSIGNED_SHORT) */
GLushort *in = (GLushort *)src_ptr;
GLuint size = sizeof(GLushort) * ((mesa_ind_buf->count + 1) & ~1);
radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
&context->ind_buf.bo_offset, size, 4);
radeon_bo_map(context->ind_buf.bo, 1);
assert(context->ind_buf.bo->ptr != NULL);
out = (GLuint *)ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
for (i = 0; i + 1 < mesa_ind_buf->count; i += 2)
{
*out++ = in[i] | in[i + 1] << 16;
}
if (i < mesa_ind_buf->count)
{
*out++ = in[i];
}
radeon_bo_unmap(context->ind_buf.bo);
#endif
}
context->ind_buf.is_32bit = GL_FALSE;
context->ind_buf.count = mesa_ind_buf->count;
if (mapped_named_bo)
{
ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
}
}
static GLboolean evergreen_check_fallbacks(struct gl_context *ctx) //same
{
if (ctx->RenderMode != GL_RENDER)
return GL_TRUE;
return GL_FALSE;
}
/* start 3d, idle, cb/db flush */
#define PRE_EMIT_STATE_BUFSZ 5 + 5 + 14
static GLuint evergreenPredictRenderSize(struct gl_context* ctx,
const struct _mesa_prim *prim,
const struct _mesa_index_buffer *ib,
GLuint nr_prims)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
GLboolean flushed;
GLuint dwords, i;
GLuint state_size;
dwords = PRE_EMIT_STATE_BUFSZ;
if (ib)
dwords += nr_prims * 18;
else {
for (i = 0; i < nr_prims; ++i)
{
if (prim[i].start == 0)
dwords += 14;
else if (prim[i].count > 0xffff)
dwords += prim[i].count + 14;
else
dwords += ((prim[i].count + 1) / 2) + 14;
}
}
state_size = radeonCountStateEmitSize(&context->radeon);
flushed = rcommonEnsureCmdBufSpace(&context->radeon,
dwords + state_size,
__FUNCTION__);
if (flushed)
dwords += radeonCountStateEmitSize(&context->radeon);
else
dwords += state_size;
radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s: total prediction size is %d.\n", __FUNCTION__, dwords);
return dwords;
}
static void evergreenSetupIndexBuffer(struct gl_context *ctx, const struct _mesa_index_buffer *mesa_ind_buf)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
if (!mesa_ind_buf) {
context->ind_buf.bo = NULL;
return;
}
#if MESA_BIG_ENDIAN
if (mesa_ind_buf->type == GL_UNSIGNED_INT)
#else
if (mesa_ind_buf->type != GL_UNSIGNED_BYTE)
#endif
{
const GLvoid *src_ptr;
GLvoid *dst_ptr;
GLboolean mapped_named_bo = GL_FALSE;
if (mesa_ind_buf->obj->Name && !mesa_ind_buf->obj->Pointer)
{
ctx->Driver.MapBufferRange(ctx, 0, mesa_ind_buf->obj->Size,
GL_MAP_READ_BIT, mesa_ind_buf->obj);
assert(mesa_ind_buf->obj->Pointer != NULL);
mapped_named_bo = GL_TRUE;
}
src_ptr = ADD_POINTERS(mesa_ind_buf->obj->Pointer, mesa_ind_buf->ptr);
const GLuint size = mesa_ind_buf->count * getTypeSize(mesa_ind_buf->type);
radeonAllocDmaRegion(&context->radeon, &context->ind_buf.bo,
&context->ind_buf.bo_offset, size, 4);
radeon_bo_map(context->ind_buf.bo, 1);
assert(context->ind_buf.bo->ptr != NULL);
dst_ptr = ADD_POINTERS(context->ind_buf.bo->ptr, context->ind_buf.bo_offset);
memcpy(dst_ptr, src_ptr, size);
radeon_bo_unmap(context->ind_buf.bo);
context->ind_buf.is_32bit = (mesa_ind_buf->type == GL_UNSIGNED_INT);
context->ind_buf.count = mesa_ind_buf->count;
if (mapped_named_bo)
{
ctx->Driver.UnmapBuffer(ctx, mesa_ind_buf->obj);
}
}
else
{
evergreenFixupIndexBuffer(ctx, mesa_ind_buf);
}
}
#if 0 /* unused */
static void evergreenAlignDataToDword(struct gl_context *ctx,
const struct gl_client_array *input,
int count,
struct StreamDesc *attr)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
const int dst_stride = (input->StrideB + 3) & ~3;
const int size = getTypeSize(input->Type) * input->Size * count;
GLboolean mapped_named_bo = GL_FALSE;
radeonAllocDmaRegion(&context->radeon, &attr->bo, &attr->bo_offset, size, 32);
radeon_bo_map(attr->bo, 1);
if (!input->BufferObj->Pointer)
{
ctx->Driver.MapBufferRange(ctx, 0, input->BufferObj->Size,
GL_MAP_READ_BIT, input->BufferObj->obj);
mapped_named_bo = GL_TRUE;
}
{
GLvoid *src_ptr = ADD_POINTERS(input->BufferObj->Pointer, input->Ptr);
GLvoid *dst_ptr = ADD_POINTERS(attr->bo->ptr, attr->bo_offset);
int i;
for (i = 0; i < count; ++i)
{
memcpy(dst_ptr, src_ptr, input->StrideB);
src_ptr += input->StrideB;
dst_ptr += dst_stride;
}
}
radeon_bo_unmap(attr->bo);
if (mapped_named_bo)
{
ctx->Driver.UnmapBuffer(ctx, input->BufferObj);
}
attr->stride = dst_stride;
}
#endif
static void evergreenSetupStreams(struct gl_context *ctx, const struct gl_client_array *input[], int count)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
GLuint stride;
int ret;
int i, index;
EVERGREEN_STATECHANGE(context, vtx);
for(index = 0; index < context->nNumActiveAos; index++)
{
struct radeon_aos *aos = &context->radeon.tcl.aos[index];
i = context->stream_desc[index].element;
stride = (input[i]->StrideB == 0) ? getTypeSize(input[i]->Type) * input[i]->Size : input[i]->StrideB;
if (input[i]->Type == GL_DOUBLE || input[i]->Type == GL_UNSIGNED_INT || input[i]->Type == GL_INT
#if MESA_BIG_ENDIAN
|| getTypeSize(input[i]->Type) != 4
#endif
)
{
evergreenConvertAttrib(ctx, count, input[i], &context->stream_desc[index]);
}
else
{
if (input[i]->BufferObj->Name)
{
context->stream_desc[index].stride = input[i]->StrideB;
context->stream_desc[index].bo_offset = (intptr_t) input[i]->Ptr;
context->stream_desc[index].bo = get_radeon_buffer_object(input[i]->BufferObj)->bo;
context->stream_desc[index].is_named_bo = GL_TRUE;
}
else
{
int size;
int local_count = count;
uint32_t *dst;
if (input[i]->StrideB == 0)
{
size = getTypeSize(input[i]->Type) * input[i]->Size;
local_count = 1;
}
else
{
size = getTypeSize(input[i]->Type) * input[i]->Size * local_count;
}
radeonAllocDmaRegion(&context->radeon, &context->stream_desc[index].bo,
&context->stream_desc[index].bo_offset, size, 32);
radeon_bo_map(context->stream_desc[index].bo, 1);
assert(context->stream_desc[index].bo->ptr != NULL);
dst = (uint32_t *)ADD_POINTERS(context->stream_desc[index].bo->ptr,
context->stream_desc[index].bo_offset);
switch (context->stream_desc[index].dwords)
{
case 1:
radeonEmitVec4(dst, input[i]->Ptr, input[i]->StrideB, local_count);
break;
case 2:
radeonEmitVec8(dst, input[i]->Ptr, input[i]->StrideB, local_count);
break;
case 3:
radeonEmitVec12(dst, input[i]->Ptr, input[i]->StrideB, local_count);
break;
case 4:
radeonEmitVec16(dst, input[i]->Ptr, input[i]->StrideB, local_count);
break;
default:
assert(0);
break;
}
radeon_bo_unmap(context->stream_desc[index].bo);
}
}
aos->count = context->stream_desc[index].stride == 0 ? 1 : count;
aos->stride = context->stream_desc[index].stride / sizeof(float);
aos->components = context->stream_desc[index].dwords;
aos->bo = context->stream_desc[index].bo;
aos->offset = context->stream_desc[index].bo_offset;
if(context->stream_desc[index].is_named_bo)
{
radeon_cs_space_add_persistent_bo(context->radeon.cmdbuf.cs,
context->stream_desc[index].bo,
RADEON_GEM_DOMAIN_GTT, 0);
}
}
ret = radeon_cs_space_check_with_bo(context->radeon.cmdbuf.cs,
first_elem(&context->radeon.dma.reserved)->bo,
RADEON_GEM_DOMAIN_GTT, 0);
}
static void evergreenFreeData(struct gl_context *ctx)
{
/* Need to zero tcl.aos[n].bo and tcl.elt_dma_bo
* to prevent double unref in radeonReleaseArrays
* called during context destroy
*/
context_t *context = EVERGREEN_CONTEXT(ctx);
int i;
for (i = 0; i < context->nNumActiveAos; i++)
{
if (!context->stream_desc[i].is_named_bo)
{
radeon_bo_unref(context->stream_desc[i].bo);
}
context->radeon.tcl.aos[i].bo = NULL;
}
if(context->vp_Constbo != NULL)
{
radeon_bo_unref(context->vp_Constbo);
context->vp_Constbo = NULL;
}
if(context->fp_Constbo != NULL)
{
radeon_bo_unref(context->fp_Constbo);
context->fp_Constbo = NULL;
}
if (context->ind_buf.bo != NULL)
{
radeon_bo_unref(context->ind_buf.bo);
}
}
static GLboolean evergreenTryDrawPrims(struct gl_context *ctx,
const struct gl_client_array *arrays[],
const struct _mesa_prim *prim,
GLuint nr_prims,
const struct _mesa_index_buffer *ib,
GLuint min_index,
GLuint max_index )
{
context_t *context = EVERGREEN_CONTEXT(ctx);
radeonContextPtr radeon = &context->radeon;
GLuint i, id = 0;
struct radeon_renderbuffer *rrb;
if (ctx->NewState)
_mesa_update_state( ctx );
if (evergreen_check_fallbacks(ctx))
return GL_FALSE;
_tnl_UpdateFixedFunctionProgram(ctx);
evergreenSetVertexFormat(ctx, arrays, max_index + 1);
/* shaders need to be updated before buffers are validated */
evergreenUpdateShaders(ctx);
if (!evergreenValidateBuffers(ctx))
return GL_FALSE;
/* always emit CB base to prevent
* lock ups on some chips.
*/
EVERGREEN_STATECHANGE(context, cb);
/* mark vtx as dirty since it changes per-draw */
EVERGREEN_STATECHANGE(context, vtx);
evergreenSetScissor(context);
evergreenSetupVertexProgram(ctx);
evergreenSetupFragmentProgram(ctx);
evergreenUpdateShaderStates(ctx);
GLuint emit_end = evergreenPredictRenderSize(ctx, prim, ib, nr_prims)
+ context->radeon.cmdbuf.cs->cdw;
/* evergreenPredictRenderSize will call radeonReleaseDmaRegions, so update VP/FP const buf after it. */
evergreenSetupVPconstants(ctx);
evergreenSetupFPconstants(ctx);
evergreenSetupIndexBuffer(ctx, ib);
evergreenSetupStreams(ctx, arrays, max_index + 1);
radeonEmitState(radeon);
radeon_debug_add_indent();
for (i = 0; i < nr_prims; ++i)
{
if (context->ind_buf.bo)
evergreenRunRenderPrimitive(ctx,
prim[i].start,
prim[i].start + prim[i].count,
prim[i].mode,
prim[i].basevertex);
else
evergreenRunRenderPrimitiveImmediate(ctx,
prim[i].start,
prim[i].start + prim[i].count,
prim[i].mode);
}
radeon_debug_remove_indent();
/* Flush render op cached for last several quads. */
/* XXX drm should handle this in fence submit */
//evergreeWaitForIdleClean(context);
rrb = radeon_get_colorbuffer(&context->radeon);
if (rrb && rrb->bo)
r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
CB_ACTION_ENA_bit | (1 << (id + 6)));
rrb = radeon_get_depthbuffer(&context->radeon);
if (rrb && rrb->bo)
r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,
DB_ACTION_ENA_bit | DB_DEST_BASE_ENA_bit);
evergreenFreeData(ctx);
if (emit_end < context->radeon.cmdbuf.cs->cdw)
{
WARN_ONCE("Rendering was %d commands larger than predicted size."
" We might overflow command buffer.\n", context->radeon.cmdbuf.cs->cdw - emit_end);
}
return GL_TRUE;
}
static void evergreenDrawPrims(struct gl_context *ctx,
const struct gl_client_array *arrays[],
const struct _mesa_prim *prim,
GLuint nr_prims,
const struct _mesa_index_buffer *ib,
GLboolean index_bounds_valid,
GLuint min_index,
GLuint max_index)
{
GLboolean retval = GL_FALSE;
context_t *context = EVERGREEN_CONTEXT(ctx);
radeonContextPtr radeon = &context->radeon;
radeon_prepare_render(radeon);
/* This check should get folded into just the places that
* min/max index are really needed.
*/
if (!vbo_all_varyings_in_vbos(arrays)) {
if (!index_bounds_valid)
vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
/* do we want to rebase, minimizes the
* amount of data to upload? */
if (min_index) {
vbo_rebase_prims( ctx, arrays, prim, nr_prims, ib, min_index, max_index, evergreenDrawPrims );
return;
}
}
/* Make an attempt at drawing */
retval = evergreenTryDrawPrims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
/* If failed run tnl pipeline - it should take care of fallbacks */
if (!retval) {
_swsetup_Wakeup(ctx);
_tnl_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
}
}
void evergreenInitDraw(struct gl_context *ctx)
{
struct vbo_context *vbo = vbo_context(ctx);
/* to be enabled */
vbo->draw_prims = evergreenDrawPrims;
}

735
src/mesa/drivers/dri/r600/evergreen_sq.h
View file

@ -1,735 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_SQ_H_
#define _EVERGREEN_SQ_H_
enum{
//CF
EG_CF_WORD0__ADDR_shift = 0,
EG_CF_WORD0__ADDR_mask = 0xFFFFFF,
EG_CF_WORD0__JUMPTABLE_SEL_shift = 24,
EG_CF_WORD0__JUMPTABLE_SEL_mask = 0x7 << 24,
EG_CF_WORD1__POP_COUNT_shift = 0, //3 bits
EG_CF_WORD1__POP_COUNT_mask = 0x7,
EG_CF_WORD1__CF_CONST_shift = 3, //5 bits
EG_CF_WORD1__CF_CONST_mask = 0x1F << 3,
EG_CF_WORD1__COND_shift = 8, //2 bits
EG_CF_WORD1__COND_mask = 0x3 << 8,
EG_CF_WORD1__COUNT_shift = 10,//6 bits
EG_CF_WORD1__COUNT_mask = 0x3F << 10,
EG_CF_WORD1__reserved_shift = 16,//4 bits
EG_CF_WORD1__VPM_shift = 20,//1 bit
EG_CF_WORD1__VPM_bit = 1 << 20,
EG_CF_WORD1__EOP_shift = 21,//1 bit
EG_CF_WORD1__EOP_bit = 1 << 21,
EG_CF_WORD1__CF_INST_shift = 22,//8 bits
EG_CF_WORD1__CF_INST_mask = 0xFF << 22,
EG_CF_WORD1__WQM_shift = 30,//1 bit
EG_CF_WORD1__WQM_bit = 1 << 30,
EG_CF_WORD1__BARRIER_shift = 31,//1 bit
EG_CF_WORD1__BARRIER_bit = 1 << 31,
EG_CF_INST_NOP = 0,
EG_CF_INST_TC = 1,
EG_CF_INST_VC = 2,
EG_CF_INST_GDS = 3,
EG_CF_INST_LOOP_START = 4,
EG_CF_INST_LOOP_END = 5,
EG_CF_INST_LOOP_START_DX10 = 6,
EG_CF_INST_LOOP_START_NO_AL = 7,
EG_CF_INST_LOOP_CONTINUE = 8,
EG_CF_INST_LOOP_BREAK = 9,
EG_CF_INST_JUMP = 10,
EG_CF_INST_PUSH = 11,
EG_CF_INST_Reserved_12 = 12,
EG_CF_INST_ELSE = 13,
EG_CF_INST_POP = 14,
EG_CF_INST_Reserved_15 = 15,
EG_CF_INST_Reserved_16 = 16,
EG_CF_INST_Reserved_17 = 17,
EG_CF_INST_CALL = 18,
EG_CF_INST_CALL_FS = 19,
EG_CF_INST_RETURN = 20,
EG_CF_INST_EMIT_VERTEX = 21,
EG_CF_INST_EMIT_CUT_VERTEX = 22,
EG_CF_INST_CUT_VERTEX = 23,
EG_CF_INST_KILL = 24,
EG_CF_INST_Reserved_25 = 25,
EG_CF_INST_WAIT_ACK = 26,
EG_CF_INST_TC_ACK = 27,
EG_CF_INST_VC_ACK = 28,
EG_CF_INST_JUMPTABLE = 29,
EG_CF_INST_GLOBAL_WAVE_SYNC = 30,
EG_CF_INST_HALT = 31,
//TEX
EG_TEX_WORD0__TEX_INST_shift = 0, //5 bits
EG_TEX_WORD0__TEX_INST_mask = 0x1F,
EG_TEX_WORD0__INST_MOD_shift = 5, //2 bits
EG_TEX_WORD0__INST_MOD_mask = 0x3 << 5,
EG_TEX_WORD0__FWQ_shift = 7, //1 bit
EG_TEX_WORD0__FWQ_bit = 1 << 7,
EG_TEX_WORD0__RESOURCE_ID_shift = 8, //8 bits
EG_TEX_WORD0__RESOURCE_ID_mask = 0xFF << 8,
EG_TEX_WORD0__SRC_GPR_shift = 16,//7 bits
EG_TEX_WORD0__SRC_GPR_mask = 0x7F << 16,
EG_TEX_WORD0__SRC_REL_shift = 23,//1 bit
EG_TEX_WORD0__SRC_REL_bit = 1 << 23,
EG_TEX_WORD0__ALT_CONST_shift = 24,//1 bit
EG_TEX_WORD0__ALT_CONST_bit = 1 << 24,
EG_TEX_WORD0__RIM_shift = 25,//2 bits
EG_TEX_WORD0__RIM_mask = 0x3 << 25,
EG_TEX_WORD0__SIM_shift = 27,//2 bits
EG_TEX_WORD0__SIM_mask = 0x3 << 27,
EG_TEX_WORD0__Reserved_shift = 29,//3 bits
EG_TEX_WORD0__Reserved_mask = 0x7 << 29,
EG_TEX_INST_Reserved_0 = 0,
EG_TEX_INST_Reserved_1 = 1,
EG_TEX_INST_Reserved_2 = 2,
EG_TEX_INST_LD = 3,
EG_TEX_INST_GET_TEXTURE_RESINFO = 4,
EG_TEX_INST_GET_NUMBER_OF_SAMPLES= 5,
EG_TEX_INST_GET_COMP_TEX_LOD = 6,
EG_TEX_INST_GET_GRADIENTS_H = 7,
EG_TEX_INST_GET_GRADIENTS_V = 8,
EG_TEX_INST_SET_TEXTURE_OFFSETS = 9,
EG_TEX_INST_KEEP_GRADIENTS = 10,
EG_TEX_INST_SET_GRADIENTS_H = 11,
EG_TEX_INST_SET_GRADIENTS_V = 12,
EG_TEX_INST_Reserved_13 = 13,
EG_TEX_INST_Reserved_14 = 14,
EG_TEX_INST_Reserved_15 = 15,
EG_TEX_INST_SAMPLE = 16,
EG_TEX_INST_SAMPLE_L = 17,
EG_TEX_INST_SAMPLE_LB = 18,
EG_TEX_INST_SAMPLE_LZ = 19,
EG_TEX_INST_SAMPLE_G = 20,
EG_TEX_INST_GATHER4 = 21,
EG_TEX_INST_SAMPLE_G_LB = 22,
EG_TEX_INST_GATHER4_O = 23,
EG_TEX_INST_SAMPLE_C = 24,
EG_TEX_INST_SAMPLE_C_L = 25,
EG_TEX_INST_SAMPLE_C_LB = 26,
EG_TEX_INST_SAMPLE_C_LZ = 27,
EG_TEX_INST_SAMPLE_C_G = 28,
EG_TEX_INST_GATHER4_C = 29,
EG_TEX_INST_SAMPLE_C_G_LB = 30,
EG_TEX_INST_GATHER4_C_O = 31,
EG_TEX_WORD1__DST_GPR_shift = 0, //7 bits
EG_TEX_WORD1__DST_GPR_mask = 0x7F,
EG_TEX_WORD1__DST_REL_shift = 7, //1 bit
EG_TEX_WORD1__DST_REL_bit = 1 << 7,
EG_TEX_WORD1__Reserved_shift = 8, //1 bit
EG_TEX_WORD1__Reserved_bit = 1 << 8,
EG_TEX_WORD1__DST_SEL_X_shift = 9, //3 bits
EG_TEX_WORD1__DST_SEL_X_mask = 0x7 << 9,
EG_TEX_WORD1__DST_SEL_Y_shift = 12,//3 bits
EG_TEX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
EG_TEX_WORD1__DST_SEL_Z_shift = 15,//3 bits
EG_TEX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
EG_TEX_WORD1__DST_SEL_W_shift = 18,//3 bits
EG_TEX_WORD1__DST_SEL_W_mask = 0x7 << 18,
EG_TEX_WORD1__LOD_BIAS_shift = 21,//7 bits
EG_TEX_WORD1__LOD_BIAS_mask = 0x7F << 21,
EG_TEX_WORD1__COORD_TYPE_X_shift = 28,//1 bit
EG_TEX_WORD1__COORD_TYPE_X_bit = 1 << 28,
EG_TEX_WORD1__COORD_TYPE_Y_shift = 29,//1 bit
EG_TEX_WORD1__COORD_TYPE_Y_bit = 1 << 29,
EG_TEX_WORD1__COORD_TYPE_Z_shift = 30,//1 bit
EG_TEX_WORD1__COORD_TYPE_Z_bit = 1 << 30,
EG_TEX_WORD1__COORD_TYPE_W_shift = 31,//1 bit
EG_TEX_WORD1__COORD_TYPE_W_bit = 1 << 31,
EG_TEX_WORD2__OFFSET_X_shift = 0, //5 bits
EG_TEX_WORD2__OFFSET_X_mask = 0x1F,
EG_TEX_WORD2__OFFSET_Y_shift = 5, //5 bits
EG_TEX_WORD2__OFFSET_Y_mask = 0x1F << 5,
EG_TEX_WORD2__OFFSET_Z_shift = 10,//5 bits
EG_TEX_WORD2__OFFSET_Z_mask = 0x1F << 10,
EG_TEX_WORD2__SAMPLER_ID_shift = 15,//5 bits
EG_TEX_WORD2__SAMPLER_ID_mask = 0x1F << 15,
EG_TEX_WORD2__SRC_SEL_X_shift = 20,//3 bits
EG_TEX_WORD2__SRC_SEL_X_mask = 0x7 << 20,
EG_TEX_WORD2__SRC_SEL_Y_shift = 23,//3 bits
EG_TEX_WORD2__SRC_SEL_Y_mask = 0x7 << 23,
EG_TEX_WORD2__SRC_SEL_Z_shift = 26,//3 bits
EG_TEX_WORD2__SRC_SEL_Z_mask = 0x7 << 26,
EG_TEX_WORD2__SRC_SEL_W_shift = 29,//3 bits
EG_TEX_WORD2__SRC_SEL_W_mask = 0x7 << 29,
//VTX
EG_VTX_WORD0__VC_INST_shift = 0, //5 bits
EG_VTX_WORD0__VC_INST_mask = 0x1F,
EG_VTX_WORD0__FETCH_TYPE_shift = 5, //2 bits
EG_VTX_WORD0__FETCH_TYPE_mask = 0x3 << 5,
EG_VTX_WORD0__FWQ_shift = 7, //1 bit
EG_VTX_WORD0__FWQ_bit = 1 << 7,
EG_VTX_WORD0__BUFFER_ID_shift = 8, //8 bits
EG_VTX_WORD0__BUFFER_ID_mask = 0xFF << 8,
EG_VTX_WORD0__SRC_GPR_shift = 16,//7 bits
EG_VTX_WORD0__SRC_GPR_mask = 0x7F << 16,
EG_VTX_WORD0__SRC_REL_shift = 23,//1 bit
EG_VTX_WORD0__SRC_REL_bit = 1 << 23,
EG_VTX_WORD0__SRC_SEL_X_shift = 24,//2 bits
EG_VTX_WORD0__SRC_SEL_X_mask = 0x3 << 24,
EG_VTX_WORD0__MFC_shift = 26,//6 bits
EG_VTX_WORD0__MFC_mask = 0x3F << 26,
EG_VC_INST_FETCH = 0,
EG_VC_INST_SEMANTIC = 1,
EG_VC_INST_Reserved_2 = 2,
EG_VC_INST_Reserved_3 = 3,
EG_VC_INST_Reserved_4 = 4,
EG_VC_INST_Reserved_5 = 5,
EG_VC_INST_Reserved_6 = 6,
EG_VC_INST_Reserved_7 = 7,
EG_VC_INST_Reserved_8 = 8,
EG_VC_INST_Reserved_9 = 9,
EG_VC_INST_Reserved_10 = 10,
EG_VC_INST_Reserved_11 = 11,
EG_VC_INST_Reserved_12 = 12,
EG_VC_INST_Reserved_13 = 13,
EG_VC_INST_GET_BUFFER_RESINFO = 14,
EG_VTX_FETCH_VERTEX_DATA = 0,
EG_VTX_FETCH_INSTANCE_DATA = 1,
EG_VTX_FETCH_NO_INDEX_OFFSET = 2,
EG_VTX_WORD1_SEM__SEMANTIC_ID_shift = 0, //8 bits
EG_VTX_WORD1_SEM__SEMANTIC_ID_mask = 0xFF,
EG_VTX_WORD1_GPR__DST_GPR_shift = 0, //7 bits
EG_VTX_WORD1_GPR__DST_GPR_mask = 0x7F,
EG_VTX_WORD1_GPR__DST_REL_shift = 7, //1 bit
EG_VTX_WORD1_GPR__DST_REL_bit = 1 << 7,
EG_VTX_WORD1__Reserved_shift = 8, //1 bit
EG_VTX_WORD1__Reserved_bit = 1 << 8,
EG_VTX_WORD1__DST_SEL_X_shift = 9, //3 bits
EG_VTX_WORD1__DST_SEL_X_mask = 0x7 << 9,
EG_VTX_WORD1__DST_SEL_Y_shift = 12,//3 bits
EG_VTX_WORD1__DST_SEL_Y_mask = 0x7 << 12,
EG_VTX_WORD1__DST_SEL_Z_shift = 15,//3 bits
EG_VTX_WORD1__DST_SEL_Z_mask = 0x7 << 15,
EG_VTX_WORD1__DST_SEL_W_shift = 18,//3 bits
EG_VTX_WORD1__DST_SEL_W_mask = 0x7 << 18,
EG_VTX_WORD1__UCF_shift = 21,//1 bit
EG_VTX_WORD1__UCF_bit = 1 << 21,
EG_VTX_WORD1__DATA_FORMAT_shift = 22,//6 bits
EG_VTX_WORD1__DATA_FORMAT_mask = 0x3F << 22,
EG_VTX_WORD1__NFA_shift = 28,//2 bits
EG_VTX_WORD1__NFA_mask = 0x3 << 28,
EG_VTX_WORD1__FCA_shift = 30,//1 bit
EG_VTX_WORD1__FCA_bit = 1 << 30,
EG_VTX_WORD1__SMA_shift = 31,//1 bit
EG_VTX_WORD1__SMA_bit = 1 << 31,
EG_VTX_WORD2__OFFSET_shift = 0, //16 bits
EG_VTX_WORD2__OFFSET_mask = 0xFFFF,
EG_VTX_WORD2__ENDIAN_SWAP_shift = 16,//2 bits
EG_VTX_WORD2__ENDIAN_SWAP_mask = 0x3 << 16,
EG_VTX_WORD2__CBNS_shift = 18,//1 bit
EG_VTX_WORD2__CBNS_bit = 1 << 18,
EG_VTX_WORD2__MEGA_FETCH_shift = 19,//1 bit
EG_VTX_WORD2__MEGA_FETCH_mask = 1 << 19,
EG_VTX_WORD2__ALT_CONST_shift = 20,//1 bit
EG_VTX_WORD2__ALT_CONST_mask = 1 << 20,
EG_VTX_WORD2__BIM_shift = 21,//2 bits
EG_VTX_WORD2__BIM_mask = 0x3 << 21,
EG_VTX_WORD2__Reserved_shift = 23,//9 bits
EG_VTX_WORD2__Reserved_mask = 0x1FF << 23,
//CF_ALU
EG_CF_ALU_WORD0__ADDR_shift = 0, //22 bits
EG_CF_ALU_WORD0__ADDR_mask = 0x3FFFFF,
EG_CF_ALU_WORD0__KCACHE_BANK0_shift = 22,//4 bits
EG_CF_ALU_WORD0__KCACHE_BANK0_mask = 0xF << 22,
EG_CF_ALU_WORD0__KCACHE_BANK1_shift = 26,//4 bits
EG_CF_ALU_WORD0__KCACHE_BANK1_mask = 0xF << 26,
EG_CF_ALU_WORD0__KCACHE_MODE0_shift = 30,//2 bits
EG_CF_ALU_WORD0__KCACHE_MODE0_mask = 0x3 << 30,
EG_CF_ALU_WORD1__KCACHE_MODE1_shift = 0, //2 bits
EG_CF_ALU_WORD1__KCACHE_MODE1_mask = 0x3,
EG_CF_ALU_WORD1__KCACHE_ADDR0_shift = 2, //8 bits
EG_CF_ALU_WORD1__KCACHE_ADDR0_mask = 0xFF << 2,
EG_CF_ALU_WORD1__KCACHE_ADDR1_shift = 10, //8 bits
EG_CF_ALU_WORD1__KCACHE_ADDR1_mask = 0xFF << 10,
EG_CF_ALU_WORD1__COUNT_shift = 18, //7 bits
EG_CF_ALU_WORD1__COUNT_mask = 0x7F << 18,
EG_CF_ALU_WORD1__ALT_CONST_shift = 25, //1 bit
EG_CF_ALU_WORD1__ALT_CONST_bit = 1 << 25,
EG_CF_ALU_WORD1__CF_INST_shift = 26, //4 bits
EG_CF_ALU_WORD1__CF_INST_mask = 0xF << 26,
EG_CF_ALU_WORD1__WQM_shift = 30, //1 bit
EG_CF_ALU_WORD1__WQM_bit = 1 << 30,
EG_CF_ALU_WORD1__BARRIER_shift = 31, //1 bit
EG_CF_ALU_WORD1__BARRIER_bit = 1 << 31,
EG_CF_INST_ALU = 8,
EG_CF_INST_ALU_PUSH_BEFORE = 9,
EG_CF_INST_ALU_POP_AFTER = 10,
EG_CF_INST_ALU_POP2_AFTER = 11,
EG_CF_INST_ALU_EXTENDED = 12,
EG_CF_INST_ALU_CONTINUE = 13,
EG_CF_INST_ALU_BREAK = 14,
EG_CF_INST_ALU_ELSE_AFTER = 15,
EG_CF_ALU_WORD0_EXT__Reserved0_shift = 0, //4 bits
EG_CF_ALU_WORD0_EXT__Reserved0_mask = 0xF,
EG_CF_ALU_WORD0_EXT__KBIM0_shift = 4, //2 bits
EG_CF_ALU_WORD0_EXT__KBIM0_mask = 0x3 << 4,
EG_CF_ALU_WORD0_EXT__KBIM1_shift = 6, //2 bits
EG_CF_ALU_WORD0_EXT__KBIM1_mask = 0x3 << 6,
EG_CF_ALU_WORD0_EXT__KBIM2_shift = 8, //2 bits
EG_CF_ALU_WORD0_EXT__KBIM2_mask = 0x3 << 8,
EG_CF_ALU_WORD0_EXT__KBIM3_shift = 10,//2 bits
EG_CF_ALU_WORD0_EXT__KBIM3_mask = 0x3 << 10,
EG_CF_ALU_WORD0_EXT__Reserved12_shift = 12,//10 bits
EG_CF_ALU_WORD0_EXT__Reserved12_mask = 0x3FF << 12,
EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_shift = 22,//4 bits
EG_CF_ALU_WORD0_EXT__KCACHE_BANK2_mask = 0xF << 22,
EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_shift = 26,//4 bits
EG_CF_ALU_WORD0_EXT__KCACHE_BANK3_mask = 0xF << 26,
EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_shift = 30,//2 btis
EG_CF_ALU_WORD0_EXT__KCACHE_MODE2_mask = 0x3 << 30,
EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_shift = 0, //2 bits
EG_CF_ALU_WORD1_EXT__KCACHE_MODE3_mask = 0x3,
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_shift = 2, //8 bits
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR2_mask = 0xFF << 2,
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_shift = 10, //8 bits
EG_CF_ALU_WORD1_EXT__KCACHE_ADDR3_mask = 0xFF << 10,
EG_CF_ALU_WORD1_EXT__Reserved18_shift = 18, //8 bits
EG_CF_ALU_WORD1_EXT__Reserved18_mask = 0xFF << 18,
EG_CF_ALU_WORD1_EXT__CF_INST_shift = 26, //4 bits
EG_CF_ALU_WORD1_EXT__CF_INST_mask = 0xF << 26,
EG_CF_ALU_WORD1_EXT__Reserved30_shift = 30, //1 bit
EG_CF_ALU_WORD1_EXT__Reserved30_bit = 1 << 30,
EG_CF_ALU_WORD1_EXT__BARRIER_shift = 31, //1 bit
EG_CF_ALU_WORD1_EXT__BARRIER_bit = 1 << 31,
//ALU
EG_ALU_WORD0__SRC0_SEL_shift = 0, //9 bits
EG_ALU_WORD0__SRC0_SEL_mask = 0x1FF,
EG_ALU_WORD0__SRC1_SEL_shift = 13,//9 bits
EG_ALU_WORD0__SRC1_SEL_mask = 0x1FF << 13,
EG_ALU_WORD0__SRC0_REL_shift = 9, //1 bit
EG_ALU_WORD0__SRC0_REL_bit = 1 << 9,
EG_ALU_WORD0__SRC1_REL_shift = 22,//1 bit
EG_ALU_WORD0__SRC1_REL_bit = 1 << 22,
EG_ALU_WORD0__SRC0_CHAN_shift = 10,//2 bits
EG_ALU_WORD0__SRC0_CHAN_mask = 0x3 << 10,
EG_ALU_WORD0__SRC1_CHAN_shift = 23,//2 bits
EG_ALU_WORD0__SRC1_CHAN_mask = 0x3 << 23,
EG_ALU_WORD0__SRC0_NEG_shift = 12,//1 bit
EG_ALU_WORD0__SRC0_NEG_bit = 1 << 12,
EG_ALU_WORD0__SRC1_NEG_shift = 25,//1 bit
EG_ALU_WORD0__SRC1_NEG_bit = 1 << 25,
EG_ALU_WORD0__INDEX_MODE_shift = 26,//3 bits
EG_ALU_WORD0__INDEX_MODE_mask = 0x7 << 26,
EG_ALU_WORD0__PRED_SEL_shift = 29,//2 bits
EG_ALU_WORD0__PRED_SEL_mask = 0x3 << 29,
EG_ALU_WORD0__LAST_shift = 31,//1 bit
EG_ALU_WORD0__LAST_bit = 1 << 31,
EG_ALU_WORD1_OP2__SRC0_ABS_shift = 0, //1 bit
EG_ALU_WORD1_OP2__SRC0_ABS_bit = 1,
EG_ALU_WORD1_OP2__SRC1_ABS_shift = 1, //1 bit
EG_ALU_WORD1_OP2__SRC1_ABS_bit = 1 << 1,
EG_ALU_WORD1_OP2__UEM_shift = 2, //1 bit
EG_ALU_WORD1_OP2__UEM_bit = 1 << 2,
EG_ALU_WORD1_OP2__UPDATE_PRED_shift = 3, //1 bit
EG_ALU_WORD1_OP2__UPDATE_PRED_bit = 1 << 3,
EG_ALU_WORD1_OP2__WRITE_MASK_shift = 4, //1 bit
EG_ALU_WORD1_OP2__WRITE_MASK_bit = 1 << 4,
EG_ALU_WORD1_OP2__OMOD_shift = 5, //2 bits
EG_ALU_WORD1_OP2__OMOD_mask = 0x3 << 5,
EG_ALU_WORD1_OP2__ALU_INST_shift = 7, //11 bits
EG_ALU_WORD1_OP2__ALU_INST_mask = 0x7FF << 7,
EG_ALU_WORD1__BANK_SWIZZLE_shift = 18,//3 bits
EG_ALU_WORD1__BANK_SWIZZLE_mask = 0x7 << 18,
EG_ALU_WORD1__DST_GPR_shift = 21,//7 bits
EG_ALU_WORD1__DST_GPR_mask = 0x7F << 21,
EG_ALU_WORD1__DST_REL_shift = 28,//1 bit
EG_ALU_WORD1__DST_REL_mask = 1 << 28,
EG_ALU_WORD1__DST_CHAN_shift = 29,//2 bits
EG_ALU_WORD1__DST_CHAN_mask = 0x3 << 29,
EG_ALU_WORD1__CLAMP_shift = 31,//1 bits
EG_ALU_WORD1__CLAMP_mask = 1 << 31,
EG_ALU_WORD1_OP3__SRC2_SEL_shift = 0, //9 bits
EG_ALU_WORD1_OP3__SRC2_SEL_mask = 0x1FF,
EG_ALU_WORD1_OP3__SRC2_REL_shift = 9, //1 bit
EG_ALU_WORD1_OP3__SRC2_REL_bit = 1 << 9,
EG_ALU_WORD1_OP3__SRC2_CHAN_shift = 10,//2 bits
EG_ALU_WORD1_OP3__SRC2_CHAN_mask = 0x3 << 10,
EG_ALU_WORD1_OP3__SRC2_NEG_shift = 12,//1 bit
EG_ALU_WORD1_OP3__SRC2_NEG_bit = 1 << 12,
EG_ALU_WORD1_OP3__ALU_INST_shift = 13,//5 bits
EG_ALU_WORD1_OP3__ALU_INST_mask = 0x1F << 13,
EG_OP3_INST_BFE_UINT = 4,
EG_OP3_INST_BFE_INT = 5,
EG_OP3_INST_BFI_INT = 6,
EG_OP3_INST_FMA = 7,
EG_OP3_INST_CNDNE_64 = 9,
EG_OP3_INST_FMA_64 = 10,
EG_OP3_INST_LERP_UINT = 11,
EG_OP3_INST_BIT_ALIGN_INT = 12,
EG_OP3_INST_BYTE_ALIGN_INT = 13,
EG_OP3_INST_SAD_ACCUM_UINT = 14,
EG_OP3_INST_SAD_ACCUM_HI_UINT = 15,
EG_OP3_INST_MULADD_UINT24 = 16,
EG_OP3_INST_LDS_IDX_OP = 17,
EG_OP3_INST_MULADD = 20,
EG_OP3_INST_MULADD_M2 = 21,
EG_OP3_INST_MULADD_M4 = 22,
EG_OP3_INST_MULADD_D2 = 23,
EG_OP3_INST_MULADD_IEEE = 24,
EG_OP3_INST_CNDE = 25,
EG_OP3_INST_CNDGT = 26,
EG_OP3_INST_CNDGE = 27,
EG_OP3_INST_CNDE_INT = 28,
EG_OP3_INST_CMNDGT_INT = 29,
EG_OP3_INST_CMNDGE_INT = 30,
EG_OP3_INST_MUL_LIT = 31,
EG_OP2_INST_ADD = 0,
EG_OP2_INST_MUL = 1,
EG_OP2_INST_MUL_IEEE = 2,
EG_OP2_INST_MAX = 3,
EG_OP2_INST_MIN = 4,
EG_OP2_INST_MAX_DX10 = 5,
EG_OP2_INST_MIN_DX10 = 6,
EG_OP2_INST_SETE = 8,
EG_OP2_INST_SETGT = 9,
EG_OP2_INST_SETGE = 10,
EG_OP2_INST_SETNE = 11,
EG_OP2_INST_SETE_DX10 = 12,
EG_OP2_INST_SETGT_DX10 = 13,
EG_OP2_INST_SETGE_DX10 = 14,
EG_OP2_INST_SETNE_DX10 = 15,
EG_OP2_INST_FRACT = 16,
EG_OP2_INST_TRUNC = 17,
EG_OP2_INST_CEIL = 18,
EG_OP2_INST_RNDNE = 19,
EG_OP2_INST_FLOOR = 20,
EG_OP2_INST_ASHR_INT = 21,
EG_OP2_INST_LSHR_INT = 22,
EG_OP2_INST_LSHL_INT = 23,
EG_OP2_INST_MOV = 25,
EG_OP2_INST_NOP = 26,
EG_OP2_INST_MUL_64 = 27,
EG_OP2_INST_FLT64_TO_FLT32 = 28,
EG_OP2_INST_FLT32_TO_FLT64 = 29,
EG_OP2_INST_PRED_SETGT_UINT = 30,
EG_OP2_INST_PRED_SETGE_UINT = 31,
EG_OP2_INST_PRED_SETE = 32,
EG_OP2_INST_PRED_SETGT = 33,
EG_OP2_INST_PRED_SETGE = 34,
EG_OP2_INST_PRED_SETNE = 35,
EG_OP2_INST_PRED_SET_INV = 36,
EG_OP2_INST_PRED_SET_POP = 37,
EG_OP2_INST_PRED_SET_CLR = 38,
EG_OP2_INST_PRED_SET_RESTORE = 39,
EG_OP2_INST_PRED_SETE_PUSH = 40,
EG_OP2_INST_PRED_SETGT_PUSH = 41,
EG_OP2_INST_PRED_SETGE_PUSH = 42,
EG_OP2_INST_PRED_SETNE_PUSH = 43,
EG_OP2_INST_KILLE = 44,
EG_OP2_INST_KILLGT = 45,
EG_OP2_INST_KILLGE = 46,
EG_OP2_INST_KILLNE = 47,
EG_OP2_INST_AND_INT = 48,
EG_OP2_INST_OR_INT = 49,
EG_OP2_INST_XOR_INT = 50,
EG_OP2_INST_NOT_INT = 51,
EG_OP2_INST_ADD_INT = 52,
EG_OP2_INST_SUB_INT = 53,
EG_OP2_INST_MAX_INT = 54,
EG_OP2_INST_MIN_INT = 55,
EG_OP2_INST_MAX_UINT = 56,
EG_OP2_INST_MIN_UINT = 57,
EG_OP2_INST_SETE_INT = 58,
EG_OP2_INST_SETGT_INT = 59,
EG_OP2_INST_SETGE_INT = 60,
EG_OP2_INST_SETNE_INT = 61,
EG_OP2_INST_SETGT_UINT = 62,
EG_OP2_INST_SETGE_UINT = 63,
EG_OP2_INST_KILLGT_UINT = 64,
EG_OP2_INST_KILLGE_UINT = 65,
EG_OP2_INST_PREDE_INT = 66,
EG_OP2_INST_PRED_SETGT_INT = 67,
EG_OP2_INST_PRED_SETGE_INT = 68,
EG_OP2_INST_PRED_SETNE_INT = 69,
EG_OP2_INST_KILLE_INT = 70,
EG_OP2_INST_KILLGT_INT = 71,
EG_OP2_INST_KILLGE_INT = 72,
EG_OP2_INST_KILLNE_INT = 73,
EG_OP2_INST_PRED_SETE_PUSH_INT = 74,
EG_OP2_INST_PRED_SETGT_PUSH_INT = 75,
EG_OP2_INST_PRED_SETGE_PUSH_INT = 76,
EG_OP2_INST_PRED_SETNE_PUSH_INT = 77,
EG_OP2_INST_PRED_SETLT_PUSH_INT = 78,
EG_OP2_INST_PRED_SETLE_PUSH_INT = 79,
EG_OP2_INST_FLT_TO_INT = 80,
EG_OP2_INST_BFREV_INT = 81,
EG_OP2_INST_ADDC_UINT = 82,
EG_OP2_INST_SUBB_UINT = 83,
EG_OP2_INST_GROUP_BARRIER = 84,
EG_OP2_INST_GROUP_SEQ_BEGIN = 85,
EG_OP2_INST_GROUP_SEQ_END = 86,
EG_OP2_INST_SET_MODE = 87,
EG_OP2_INST_SET_CF_IDX0 = 88,
EG_OP2_INST_SET_CF_IDX1 = 89,
EG_OP2_INST_SET_LDS_SIZE = 90,
EG_OP2_INST_EXP_IEEE = 129,
EG_OP2_INST_LOG_CLAMPED = 130,
EG_OP2_INST_LOG_IEEE = 131,
EG_OP2_INST_RECIP_CLAMPED = 132,
EG_OP2_INST_RECIP_FF = 133,
EG_OP2_INST_RECIP_IEEE = 134,
EG_OP2_INST_RECIPSQRT_CLAMPED = 135,
EG_OP2_INST_RECIPSQRT_FF = 136,
EG_OP2_INST_RECIPSQRT_IEEE = 137,
EG_OP2_INST_SQRT_IEEE = 138,
EG_OP2_INST_SIN = 141,
EG_OP2_INST_COS = 142,
EG_OP2_INST_MULLO_INT = 143,
EG_OP2_INST_MULHI_INT = 144,
EG_OP2_INST_MULLO_UINT = 145,
EG_OP2_INST_MULHI_UINT = 146,
EG_OP2_INST_RECIP_INT = 147,
EG_OP2_INST_RECIP_UINT = 148,
EG_OP2_INST_RECIP_64 = 149,
EG_OP2_INST_RECIP_CLAMPED_64 = 150,
EG_OP2_INST_RECIPSQRT_64 = 151,
EG_OP2_INST_RECIPSQRT_CLAMPED_64 = 152,
EG_OP2_INST_SQRT_64 = 153,
EG_OP2_INST_FLT_TO_UINT = 154,
EG_OP2_INST_INT_TO_FLT = 155,
EG_OP2_INST_UINT_TO_FLT = 156,
EG_OP2_INST_BFM_INT = 160,
EG_OP2_INST_FLT32_TO_FLT16 = 162,
EG_OP2_INST_FLT16_TO_FLT32 = 163,
EG_OP2_INST_UBYTE0_FLT = 164,
EG_OP2_INST_UBYTE1_FLT = 165,
EG_OP2_INST_UBYTE2_FLT = 166,
EG_OP2_INST_UBYTE3_FLT = 167,
EG_OP2_INST_BCNT_INT = 170,
EG_OP2_INST_FFBH_UINT = 171,
EG_OP2_INST_FFBL_INT = 172,
EG_OP2_INST_FFBH_INT = 173,
EG_OP2_INST_FLT_TO_UINT4 = 174,
EG_OP2_INST_DOT_IEEE = 175,
EG_OP2_INST_FLT_TO_INT_RPI = 176,
EG_OP2_INST_FLT_TO_INT_FLOOR = 177,
EG_OP2_INST_MULHI_UINT24 = 178,
EG_OP2_INST_MBCNT_32HI_INT = 179,
EG_OP2_INST_OFFSET_TO_FLT = 180,
EG_OP2_INST_MUL_UINT24 = 181,
EG_OP2_INST_BCNT_ACCUM_PREV_INT = 182,
EG_OP2_INST_MBCNT_32LO_ACCUM_PREV_INT = 183,
EG_OP2_INST_SETE_64 = 184,
EG_OP2_INST_SETNE_64 = 185,
EG_OP2_INST_SETGT_64 = 186,
EG_OP2_INST_SETGE_64 = 187,
EG_OP2_INST_MIN_64 = 188,
EG_OP2_INST_MAX_64 = 189,
EG_OP2_INST_DOT4 = 190,
EG_OP2_INST_DOT4_IEEE = 191,
EG_OP2_INST_CUBE = 192,
EG_OP2_INST_MAX4 = 193,
EG_OP2_INST_FREXP_64 = 196,
EG_OP2_INST_LDEXP_64 = 197,
EG_OP2_INST_FRACT_64 = 198,
EG_OP2_INST_PRED_SETGT_64 = 199,
EG_OP2_INST_PRED_SETE_64 = 200,
EG_OP2_INST_PRED_SETGE_64 = 201,
EG_OP2_INST_MUL_64_2 = 202, //same as prev?
EG_OP2_INST_ADD_64 = 203,
EG_OP2_INST_MOVA_INT = 204,
EG_OP2_INST_FLT64_TO_FLT32_2 = 205, //same as prev?
EG_OP2_INST_FLT32_TO_FLT64_2 = 206, //same as prev?
EG_OP2_INST_SAD_ACCUM_PREV_UINT = 207,
EG_OP2_INST_DOT = 208,
EG_OP2_INST_MUL_PREV = 209,
EG_OP2_INST_MUL_IEEE_PREV = 210,
EG_OP2_INST_ADD_PREV = 211,
EG_OP2_INST_MULADD_PREV = 212,
EG_OP2_INST_MULADD_IEEE_PREV = 213,
EG_OP2_INST_INTERP_XY = 214,
EG_OP2_INST_INTERP_ZW = 215,
EG_OP2_INST_INTERP_X = 216,
EG_OP2_INST_INTERP_Z = 217,
EG_OP2_INST_STORE_FLAGS = 218,
EG_OP2_INST_LOAD_STORE_FLAGS = 219,
EG_OP2_INST_LDS_1A = 220,
EG_OP2_INST_LDS_1A1D = 221,
EG_OP2_INST_LDS_2A = 223,
EG_OP2_INST_INTERP_LOAD_P0 = 224,
EG_OP2_INST_INTERP_LOAD_P10 = 225,
EG_OP2_INST_INTERP_LOAD_P20 = 226,
EG_SRC_SEL__GPR_start = 0,
EG_SRC_SEL__GPR_end = 127,
EG_SRC_SEL__KCONST_BANK0_start = 128,
EG_SRC_SEL__KCONST_BANK0_end = 159,
EG_SRC_SEL__KCONST_BANK1_start = 160,
EG_SRC_SEL__KCONST_BANK1_end = 191,
EG_SRC_SEL__INLINE_satrt = 192,
EG_SRC_SEL__INLINE_end = 255,
EG_SRC_SEL__KCONST_BANK2_start = 256,
EG_SRC_SEL__KCONST_BANK2_end = 287,
EG_SRC_SEL__KCONST_BANK3_start = 288,
EG_SRC_SEL__KCONST_BANK3_end = 319,
EG_SRC_SEL__ALU_SRC_LDS_OQ_A = 219,
EG_SRC_SEL__ALU_SRC_LDS_OQ_B = 220,
EG_SRC_SEL__ALU_SRC_LDS_OQ_A_POP = 221,
EG_SRC_SEL__ALU_SRC_LDS_OQ_B_POP = 222,
EG_SRC_SEL__ALU_SRC_LDS_DIRECT_A = 223,
EG_SRC_SEL__ALU_SRC_LDS_DIRECT_B = 224,
EG_SRC_SEL__ALU_SRC_TIME_HI = 227,
EG_SRC_SEL__ALU_SRC_TIME_LO = 228,
EG_SRC_SEL__ALU_SRC_MASK_HI = 229,
EG_SRC_SEL__ALU_SRC_MASK_LO = 230,
EG_SRC_SEL__ALU_SRC_HW_WAVE_ID = 231,
EG_SRC_SEL__ALU_SRC_SIMD_ID = 232,
EG_SRC_SEL__ALU_SRC_SE_ID = 233,
EG_SRC_SEL__ALU_SRC_HW_THREADGRP_ID = 234,
EG_SRC_SEL__ALU_SRC_WAVE_ID_IN_GRP = 235,
EG_SRC_SEL__ALU_SRC_NUM_THREADGRP_WAVES = 236,
EG_SRC_SEL__ALU_SRC_HW_ALU_ODD = 237,
EG_SRC_SEL__ALU_SRC_LOOP_IDX = 238,
EG_SRC_SEL__ALU_SRC_PARAM_BASE_ADDR = 240,
EG_SRC_SEL__ALU_SRC_NEW_PRIM_MASK = 241,
EG_SRC_SEL__ALU_SRC_PRIM_MASK_HI = 242,
EG_SRC_SEL__ALU_SRC_PRIM_MASK_LO = 243,
EG_SRC_SEL__ALU_SRC_1_DBL_L = 244,
EG_SRC_SEL__ALU_SRC_1_DBL_M = 245,
EG_SRC_SEL__ALU_SRC_0_5_DBL_L = 246,
EG_SRC_SEL__ALU_SRC_0_5_DBL_M = 247,
EG_SRC_SEL__ALU_SRC_0 = 248,
EG_SRC_SEL__ALU_SRC_1 = 249,
EG_SRC_SEL__ALU_SRC_1_INT = 250,
EG_SRC_SEL__ALU_SRC_M_1_INT = 251,
EG_SRC_SEL__ALU_SRC_0_5 = 252,
EG_SRC_SEL__ALU_SRC_LITERAL = 253,
EG_SRC_SEL__ALU_SRC_PV = 254,
EG_SRC_SEL__ALU_SRC_PS = 255,
//ALLOC_EXPORT
EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_shift = 0, //13 bits
EG_CF_ALLOC_EXPORT_WORD0__ARRAY_BASE_mask = 0x1FFF,
EG_CF_ALLOC_EXPORT_WORD0__TYPE_shift = 13,//2 bits
EG_CF_ALLOC_EXPORT_WORD0__TYPE_mask = 0x3 << 13,
EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_shift = 15,//7 bits
EG_CF_ALLOC_EXPORT_WORD0__RW_GPR_mask = 0x7F << 15,
EG_CF_ALLOC_EXPORT_WORD0__RW_REL_shift = 22,//1 bit
EG_CF_ALLOC_EXPORT_WORD0__RW_REL_bit = 1 << 22,
EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_shift = 23,//7 bits
EG_CF_ALLOC_EXPORT_WORD0__INDEX_GPR_mask = 0x7F << 23,
EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_shift = 30,//2 bits
EG_CF_ALLOC_EXPORT_WORD0__ELEM_SIZE_mask = 0x3 << 30,
EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_shift = 0, //12 bits
EG_CF_ALLOC_EXPORT_WORD1_BUF__ARRAY_SIZE_mask = 0xFFF,
EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_shift = 12, //4 bits
EG_CF_ALLOC_EXPORT_WORD1_BUF__COMP_MASK_mask = 0xF << 12,
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_shift = 0, //3 bits
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_X_mask = 0x7,
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_shift = 3, //3 bits
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Y_mask = 0x7 << 3,
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_shift = 6, //3 bits
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_Z_mask = 0x7 << 6,
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_shift = 9, //3 bits
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__SEL_W_mask = 0x7 << 9,
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_shift = 12,//4 bits
EG_CF_ALLOC_EXPORT_WORD1_SWIZ__Resreve_mask = 0xF << 12,
EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_shift = 16, //4 bits
EG_CF_ALLOC_EXPORT_WORD1__BURST_COUNT_mask = 0xF << 16,
EG_CF_ALLOC_EXPORT_WORD1__VPM_shift = 20, //1 bit
EG_CF_ALLOC_EXPORT_WORD1__VPM_bit = 1 << 20,
EG_CF_ALLOC_EXPORT_WORD1__EOP_shift = 21, //1 bit
EG_CF_ALLOC_EXPORT_WORD1__EOP_bit = 1 << 21,
EG_CF_ALLOC_EXPORT_WORD1__CF_INST_shift = 22, //8 bits
EG_CF_ALLOC_EXPORT_WORD1__CF_INST_mask = 0xFF << 22,
EG_CF_ALLOC_EXPORT_WORD1__MARK_shift = 30, //1 bit
EG_CF_ALLOC_EXPORT_WORD1__MARK_bit = 1 << 30,
EG_CF_ALLOC_EXPORT_WORD1__BARRIER_shift = 31, //1 bit
EG_CF_ALLOC_EXPORT_WORD1__BARRIER_bit = 1 << 31,
EG_CF_INST_MEM_STREAM0_BUF0 = 64 ,
EG_CF_INST_MEM_STREAM0_BUF1 = 65,
EG_CF_INST_MEM_STREAM0_BUF2 = 66,
EG_CF_INST_MEM_STREAM0_BUF3 = 67,
EG_CF_INST_MEM_STREAM1_BUF0 = 68,
EG_CF_INST_MEM_STREAM1_BUF1 = 69,
EG_CF_INST_MEM_STREAM1_BUF2 = 70,
EG_CF_INST_MEM_STREAM1_BUF3 = 71,
EG_CF_INST_MEM_STREAM2_BUF0 = 72,
EG_CF_INST_MEM_STREAM2_BUF1 = 73,
EG_CF_INST_MEM_STREAM2_BUF2 = 74,
EG_CF_INST_MEM_STREAM2_BUF3 = 75,
EG_CF_INST_MEM_STREAM3_BUF0 = 76,
EG_CF_INST_MEM_STREAM3_BUF1 = 77,
EG_CF_INST_MEM_STREAM3_BUF2 = 78,
EG_CF_INST_MEM_STREAM3_BUF3 = 79,
EG_CF_INST_MEM_WR_SCRATCH = 80,
EG_CF_INST_MEM_RING = 82,
EG_CF_INST_EXPORT = 83,
EG_CF_INST_EXPORT_DONE = 84,
EG_CF_INST_MEM_EXPORT = 85,
EG_CF_INST_MEM_RAT = 86,
EG_CF_INST_MEM_RAT_CACHELESS = 87,
EG_CF_INST_MEM_RING1 = 88,
EG_CF_INST_MEM_RING2 = 89,
EG_CF_INST_MEM_RING3 = 90,
EG_CF_INST_MEM_EXPORT_COMBINED = 91,
EG_CF_INST_MEM_RAT_COMBINED_CACHELESS = 92,
EG_EXPORT_PIXEL = 0,
EG_EXPORT_WRITE = 0,
EG_EXPORT_POS = 1,
EG_EXPORT_WRITE_IND = 1,
EG_EXPORT_PARAM = 2,
EG_EXPORT_WRITE_ACK = 2,
EG_EXPORT_WRITE_IND_ACK = 3,
/* PS interp param source */
EG_ALU_SRC_PARAM_BASE = 0x000001c0,
EG_ALU_SRC_PARAM_SIZE = 0x00000021,
};
#endif //_EVERGREEN_SQ_H_

1937
src/mesa/drivers/dri/r600/evergreen_state.c
View file

File diff suppressed because it is too large Load diff

47
src/mesa/drivers/dri/r600/evergreen_state.h
View file

@ -1,47 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_STATE_H_
#define _EVERGREEN_STATE_H_
#include "main/mtypes.h"
#include "r600_context.h"
extern void evergreenUpdateStateParameters(struct gl_context * ctx, GLuint new_state);
extern void evergreenUpdateShaders(struct gl_context * ctx);
extern void evergreenUpdateShaderStates(struct gl_context * ctx);
extern void evergreeUpdateShaders(struct gl_context * ctx);
extern void evergreenUpdateViewportOffset(struct gl_context * ctx);
extern void evergreenInitState(struct gl_context * ctx);
extern void evergreenInitStateFuncs (radeonContextPtr radeon, struct dd_function_table *functions);
extern void evergreenSetScissor(context_t *context);
#endif /* _EVERGREEN_STATE_H_ */

1667
src/mesa/drivers/dri/r600/evergreen_tex.c
View file

File diff suppressed because it is too large Load diff

38
src/mesa/drivers/dri/r600/evergreen_tex.h
View file

@ -1,38 +0,0 @@
/*
* Copyright (C) 2008-2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_TEX_H_
#define _EVERGREEN_TEX_H_
extern GLboolean evergreenValidateBuffers(struct gl_context * ctx);
extern void evergreenUpdateTextureState(struct gl_context * ctx);
extern void evergreenInitTextureFuncs(radeonContextPtr radeon, struct dd_function_table *functions);
extern void evergreenSetTexOffset(__DRIcontext * pDRICtx, GLint texname,
unsigned long long offset, GLint depth, GLuint pitch);
extern void evergreenSetTexBuffer(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_format, __DRIdrawable *dPriv);
#endif /* _EVERGREEN_TEX_H_ */

735
src/mesa/drivers/dri/r600/evergreen_vertprog.c
View file

@ -1,735 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#include <stdio.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include "main/imports.h"
#include "main/mtypes.h"
#include "tnl/t_context.h"
#include "program/program.h"
#include "program/prog_parameter.h"
#include "program/prog_statevars.h"
#include "radeon_debug.h"
#include "r600_context.h"
#include "r600_cmdbuf.h"
#include "r600_emit.h"
#include "program/programopt.h"
#include "evergreen_vertprog.h"
unsigned int evergreen_Map_Vertex_Output(r700_AssemblerBase *pAsm,
struct gl_vertex_program *mesa_vp,
unsigned int unStart)
{
unsigned int i;
unsigned int unBit;
unsigned int unTotal = unStart;
//!!!!!!! THE ORDER MATCH FS INPUT
unBit = 1 << VERT_RESULT_HPOS;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_HPOS] = unTotal++;
}
unBit = 1 << VERT_RESULT_COL0;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_COL0] = unTotal++;
}
unBit = 1 << VERT_RESULT_COL1;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_COL1] = unTotal++;
}
//TODO : dealing back face.
unBit = 1 << VERT_RESULT_BFC0;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_BFC0] = unTotal++;
}
unBit = 1 << VERT_RESULT_BFC1;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_BFC1] = unTotal++;
}
//TODO : dealing fog.
unBit = 1 << VERT_RESULT_FOGC;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_FOGC] = unTotal++;
}
//TODO : dealing point size.
unBit = 1 << VERT_RESULT_PSIZ;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_PSIZ] = unTotal++;
}
for(i=0; i<8; i++)
{
unBit = 1 << (VERT_RESULT_TEX0 + i);
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[VERT_RESULT_TEX0 + i] = unTotal++;
}
}
for(i=VERT_RESULT_VAR0; i<VERT_RESULT_MAX; i++)
{
unBit = 1 << i;
if(mesa_vp->Base.OutputsWritten & unBit)
{
pAsm->ucVP_OutputMap[i] = unTotal++;
}
}
return (unTotal - unStart);
}
unsigned int evergreen_Map_Vertex_Input(r700_AssemblerBase *pAsm,
struct gl_vertex_program *mesa_vp,
unsigned int unStart)
{
int i;
unsigned int unBit;
unsigned int unTotal = unStart;
for(i=0; i<VERT_ATTRIB_MAX; i++)
{
unBit = 1 << i;
if(mesa_vp->Base.InputsRead & unBit)
{
pAsm->ucVP_AttributeMap[i] = unTotal++;
}
}
return (unTotal - unStart);
}
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions(
struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp)
{
int i;
unsigned int unBit;
VTX_FETCH_METHOD vtxFetchMethod;
vtxFetchMethod.bEnableMini = GL_FALSE;
vtxFetchMethod.mega_fetch_remainder = 0;
for(i=0; i<VERT_ATTRIB_MAX; i++)
{
unBit = 1 << i;
if(mesa_vp->Base.InputsRead & unBit)
{
assemble_vfetch_instruction(&vp->r700AsmCode,
i,
vp->r700AsmCode.ucVP_AttributeMap[i],
vp->aos_desc[i].size,
vp->aos_desc[i].type,
&vtxFetchMethod);
}
}
return GL_TRUE;
}
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions2(
struct gl_context *ctx,
struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp)
{
int i;
context_t *context = R700_CONTEXT(ctx);
VTX_FETCH_METHOD vtxFetchMethod;
vtxFetchMethod.bEnableMini = GL_FALSE;
vtxFetchMethod.mega_fetch_remainder = 0;
for(i=0; i<context->nNumActiveAos; i++)
{
EG_assemble_vfetch_instruction(&vp->r700AsmCode,
vp->r700AsmCode.ucVP_AttributeMap[context->stream_desc[i].element],
context->stream_desc[i].type,
context->stream_desc[i].size,
context->stream_desc[i].element,
context->stream_desc[i]._signed,
context->stream_desc[i].normalize,
context->stream_desc[i].format,
&vtxFetchMethod);
}
return GL_TRUE;
}
void evergreen_Map_Vertex_Program(struct gl_context *ctx,
struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp)
{
r700_AssemblerBase *pAsm = &(vp->r700AsmCode);
unsigned int num_inputs;
// R0 will always be used for index into vertex buffer
pAsm->number_used_registers = 1;
pAsm->starting_vfetch_register_number = pAsm->number_used_registers;
// Map Inputs: Add 1 to mapping since R0 is used for index
num_inputs = evergreen_Map_Vertex_Input(pAsm, mesa_vp, pAsm->number_used_registers);
pAsm->number_used_registers += num_inputs;
// Create VFETCH instructions for inputs
if (GL_TRUE != evergreen_Process_Vertex_Program_Vfetch_Instructions2(ctx, vp, mesa_vp) )
{
radeon_error("Calling evergreen_Process_Vertex_Program_Vfetch_Instructions2 return error. \n");
return;
}
// Map Outputs
pAsm->number_of_exports = evergreen_Map_Vertex_Output(pAsm, mesa_vp, pAsm->number_used_registers);
pAsm->starting_export_register_number = pAsm->number_used_registers;
pAsm->number_used_registers += pAsm->number_of_exports;
/* Map temporary registers (GPRs) */
pAsm->starting_temp_register_number = pAsm->number_used_registers;
if(mesa_vp->Base.NumNativeTemporaries >= mesa_vp->Base.NumTemporaries)
{ /* arb uses NumNativeTemporaries */
pAsm->number_used_registers += mesa_vp->Base.NumNativeTemporaries;
}
else
{ /* fix func t_vp uses NumTemporaries */
pAsm->number_used_registers += mesa_vp->Base.NumTemporaries;
}
pAsm->flag_reg_index = pAsm->number_used_registers++;
pAsm->uFirstHelpReg = pAsm->number_used_registers;
}
GLboolean evergreen_Find_Instruction_Dependencies_vp(struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp)
{
GLuint i, j;
GLint * puiTEMPwrites;
struct prog_instruction *pILInst;
InstDeps *pInstDeps;
puiTEMPwrites = (GLint*) MALLOC(sizeof(GLuint)*mesa_vp->Base.NumTemporaries);
for(i=0; i<mesa_vp->Base.NumTemporaries; i++)
{
puiTEMPwrites[i] = -1;
}
pInstDeps = (InstDeps*)MALLOC(sizeof(InstDeps)*mesa_vp->Base.NumInstructions);
for(i=0; i<mesa_vp->Base.NumInstructions; i++)
{
pInstDeps[i].nDstDep = -1;
pILInst = &(mesa_vp->Base.Instructions[i]);
//Dst
if(pILInst->DstReg.File == PROGRAM_TEMPORARY)
{
//Set lastwrite for the temp
puiTEMPwrites[pILInst->DstReg.Index] = i;
}
//Src
for(j=0; j<3; j++)
{
if(pILInst->SrcReg[j].File == PROGRAM_TEMPORARY)
{
//Set dep.
pInstDeps[i].nSrcDeps[j] = puiTEMPwrites[pILInst->SrcReg[j].Index];
}
else
{
pInstDeps[i].nSrcDeps[j] = -1;
}
}
}
vp->r700AsmCode.pInstDeps = pInstDeps;
FREE(puiTEMPwrites);
return GL_TRUE;
}
struct evergreen_vertex_program* evergreenTranslateVertexShader(struct gl_context *ctx,
struct gl_vertex_program *mesa_vp)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct evergreen_vertex_program *vp;
unsigned int i;
vp = calloc(1, sizeof(*vp));
vp->mesa_program = _mesa_clone_vertex_program(ctx, mesa_vp);
vp->constbo0 = NULL;
if (mesa_vp->IsPositionInvariant)
{
_mesa_insert_mvp_code(ctx, vp->mesa_program);
}
for(i=0; i<context->nNumActiveAos; i++)
{
vp->aos_desc[i].size = context->stream_desc[i].size;
vp->aos_desc[i].stride = context->stream_desc[i].stride;
vp->aos_desc[i].type = context->stream_desc[i].type;
vp->aos_desc[i].format = context->stream_desc[i].format;
}
if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
{
vp->r700AsmCode.bR6xx = 1;
}
//Init_Program
Init_r700_AssemblerBase(SPT_VP, &(vp->r700AsmCode), &(vp->r700Shader) );
vp->r700AsmCode.bUseMemConstant = GL_TRUE;
vp->r700AsmCode.unAsic = 8;
evergreen_Map_Vertex_Program(ctx, vp, vp->mesa_program );
if(GL_FALSE == evergreen_Find_Instruction_Dependencies_vp(vp, vp->mesa_program))
{
return NULL;
}
InitShaderProgram(&(vp->r700AsmCode));
for(i=0; i < MAX_SAMPLERS; i++)
{
vp->r700AsmCode.SamplerUnits[i] = vp->mesa_program->Base.SamplerUnits[i];
}
vp->r700AsmCode.unCurNumILInsts = vp->mesa_program->Base.NumInstructions;
if(GL_FALSE == AssembleInstr(0,
0,
vp->mesa_program->Base.NumInstructions,
&(vp->mesa_program->Base.Instructions[0]),
&(vp->r700AsmCode)) )
{
return NULL;
}
if(GL_FALSE == Process_Vertex_Exports(&(vp->r700AsmCode), vp->mesa_program->Base.OutputsWritten) )
{
return NULL;
}
if( GL_FALSE == RelocProgram(&(vp->r700AsmCode), &(vp->mesa_program->Base)) )
{
return GL_FALSE;
}
vp->r700Shader.nRegs = (vp->r700AsmCode.number_used_registers == 0) ? 0
: (vp->r700AsmCode.number_used_registers - 1);
vp->r700Shader.nParamExports = vp->r700AsmCode.number_of_exports;
vp->translated = GL_TRUE;
return vp;
}
void evergreenSelectVertexShader(struct gl_context *ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct evergreen_vertex_program_cont *vpc;
struct evergreen_vertex_program *vp;
unsigned int i;
GLboolean match;
GLbitfield InputsRead;
vpc = (struct evergreen_vertex_program_cont *)ctx->VertexProgram._Current;
InputsRead = vpc->mesa_program.Base.InputsRead;
if (vpc->mesa_program.IsPositionInvariant)
{
InputsRead |= VERT_BIT_POS;
}
for (vp = vpc->progs; vp; vp = vp->next)
{
match = GL_TRUE;
for(i=0; i<context->nNumActiveAos; i++)
{
if (vp->aos_desc[i].size != context->stream_desc[i].size ||
vp->aos_desc[i].format != context->stream_desc[i].format)
{
match = GL_FALSE;
break;
}
}
if (match)
{
context->selected_vp = (struct r700_vertex_program *) vp;
return;
}
}
vp = evergreenTranslateVertexShader(ctx, &(vpc->mesa_program));
if(!vp)
{
radeon_error("Failed to translate vertex shader. \n");
return;
}
vp->next = vpc->progs;
vpc->progs = vp;
context->selected_vp = (struct r700_vertex_program *) vp;
return;
}
int evergreen_getTypeSize(GLenum type)
{
switch (type)
{
case GL_DOUBLE:
return sizeof(GLdouble);
case GL_FLOAT:
return sizeof(GLfloat);
case GL_INT:
return sizeof(GLint);
case GL_UNSIGNED_INT:
return sizeof(GLuint);
case GL_SHORT:
return sizeof(GLshort);
case GL_UNSIGNED_SHORT:
return sizeof(GLushort);
case GL_BYTE:
return sizeof(GLbyte);
case GL_UNSIGNED_BYTE:
return sizeof(GLubyte);
default:
assert(0);
return 0;
}
}
static void evergreenTranslateAttrib(struct gl_context *ctx, GLuint unLoc, int count, const struct gl_client_array *input)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
StreamDesc * pStreamDesc = &(context->stream_desc[context->nNumActiveAos]);
GLuint stride;
stride = (input->StrideB == 0) ? evergreen_getTypeSize(input->Type) * input->Size
: input->StrideB;
if (input->Type == GL_DOUBLE || input->Type == GL_UNSIGNED_INT || input->Type == GL_INT
#if MESA_BIG_ENDIAN
|| evergreen_getTypeSize(input->Type) != 4
#endif
)
{
pStreamDesc->type = GL_FLOAT;
if (input->StrideB == 0)
{
pStreamDesc->stride = 0;
}
else
{
pStreamDesc->stride = sizeof(GLfloat) * input->Size;
}
pStreamDesc->dwords = input->Size;
pStreamDesc->is_named_bo = GL_FALSE;
}
else
{
pStreamDesc->type = input->Type;
pStreamDesc->dwords = (evergreen_getTypeSize(input->Type) * input->Size + 3)/ 4;
if (!input->BufferObj->Name)
{
if (input->StrideB == 0)
{
pStreamDesc->stride = 0;
}
else
{
pStreamDesc->stride = (evergreen_getTypeSize(pStreamDesc->type) * input->Size + 3) & ~3;
}
pStreamDesc->is_named_bo = GL_FALSE;
}
}
pStreamDesc->size = input->Size;
pStreamDesc->dst_loc = context->nNumActiveAos;
pStreamDesc->element = unLoc;
pStreamDesc->format = input->Format;
switch (pStreamDesc->type)
{ //GetSurfaceFormat
case GL_FLOAT:
pStreamDesc->_signed = 0;
pStreamDesc->normalize = GL_FALSE;
break;
case GL_SHORT:
pStreamDesc->_signed = 1;
pStreamDesc->normalize = input->Normalized;
break;
case GL_BYTE:
pStreamDesc->_signed = 1;
pStreamDesc->normalize = input->Normalized;
break;
case GL_UNSIGNED_SHORT:
pStreamDesc->_signed = 0;
pStreamDesc->normalize = input->Normalized;
break;
case GL_UNSIGNED_BYTE:
pStreamDesc->_signed = 0;
pStreamDesc->normalize = input->Normalized;
break;
default:
case GL_INT:
case GL_UNSIGNED_INT:
case GL_DOUBLE:
assert(0);
break;
}
context->nNumActiveAos++;
}
void evergreenSetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct evergreen_vertex_program *vpc
= (struct evergreen_vertex_program *)ctx->VertexProgram._Current;
struct gl_vertex_program * mesa_vp = (struct gl_vertex_program *)&(vpc->mesa_program);
unsigned int unLoc = 0;
unsigned int unBit = mesa_vp->Base.InputsRead;
context->nNumActiveAos = 0;
if (mesa_vp->IsPositionInvariant)
{
unBit |= VERT_BIT_POS;
}
while(unBit)
{
if(unBit & 1)
{
evergreenTranslateAttrib(ctx, unLoc, count, arrays[unLoc]);
}
unBit >>= 1;
++unLoc;
}
context->radeon.tcl.aos_count = context->nNumActiveAos;
}
void * evergreenGetActiveVpShaderBo(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
if (vp)
return vp->shaderbo;
else
return NULL;
}
void * evergreenGetActiveVpShaderConstBo(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
if (vp)
return vp->constbo0;
else
return NULL;
}
GLboolean evergreenSetupVertexProgram(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
if(GL_FALSE == vp->loaded)
{
if(vp->r700Shader.bNeedsAssembly == GL_TRUE)
{
Assemble( &(vp->r700Shader) );
}
/* Load vp to gpu */
r600EmitShader(ctx,
&(vp->shaderbo),
(GLvoid *)(vp->r700Shader.pProgram),
vp->r700Shader.uShaderBinaryDWORDSize,
"VS");
vp->loaded = GL_TRUE;
}
EVERGREEN_STATECHANGE(context, vs);
/* TODO : enable this after MemUse fixed *=
(context->chipobj.MemUse)(context, vp->shadercode.buf->id);
*/
evergreen->SQ_PGM_RESOURCES_VS.u32All = 0;
SETbit(evergreen->SQ_PGM_RESOURCES_VS.u32All, PGM_RESOURCES__PRIME_CACHE_ON_DRAW_bit);
evergreen->vs.SQ_ALU_CONST_CACHE_VS_0.u32All = 0; /* set from buffer object. */
evergreen->vs.SQ_PGM_START_VS.u32All = 0;
SETfield(evergreen->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.nRegs + 1,
NUM_GPRS_shift, NUM_GPRS_mask);
if(vp->r700Shader.uStackSize) /* we don't use branch for now, it should be zero. */
{
SETfield(evergreen->SQ_PGM_RESOURCES_VS.u32All, vp->r700Shader.uStackSize,
STACK_SIZE_shift, STACK_SIZE_mask);
}
EVERGREEN_STATECHANGE(context, spi);
SETfield(evergreen->SPI_VS_OUT_CONFIG.u32All,
vp->r700Shader.nParamExports ? (vp->r700Shader.nParamExports - 1) : 0,
VS_EXPORT_COUNT_shift, VS_EXPORT_COUNT_mask);
SETfield(evergreen->SPI_PS_IN_CONTROL_0.u32All, vp->r700Shader.nParamExports,
NUM_INTERP_shift, NUM_INTERP_mask);
/*
SETbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, PERSP_GRADIENT_ENA_bit);
CLEARbit(evergreen->SPI_PS_IN_CONTROL_0.u32All, LINEAR_GRADIENT_ENA_bit);
*/
return GL_TRUE;
}
GLboolean evergreenSetupVPconstants(struct gl_context * ctx)
{
context_t *context = EVERGREEN_CONTEXT(ctx);
EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context);
struct evergreen_vertex_program *vp = (struct evergreen_vertex_program *) context->selected_vp;
struct gl_program_parameter_list *paramList;
unsigned int unNumParamData;
unsigned int ui;
int alloc_size;
/* sent out shader constants. */
paramList = vp->mesa_program->Base.Parameters;
if(NULL != paramList) {
/* vp->mesa_program was cloned, not updated by glsl shader api. */
/* _mesa_reference_program has already checked glsl shProg is ok and set ctx->VertexProgem._Current */
/* so, use ctx->VertexProgem._Current */
struct gl_program_parameter_list *paramListOrginal =
ctx->VertexProgram._Current->Base.Parameters;
_mesa_load_state_parameters(ctx, paramList);
if (paramList->NumParameters > EVERGREEN_MAX_DX9_CONSTS)
return GL_FALSE;
EVERGREEN_STATECHANGE(context, vs);
evergreen->vs.num_consts = paramList->NumParameters;
unNumParamData = paramList->NumParameters;
/* alloc multiple of 16 constants */
alloc_size = ((unNumParamData * 4 * 4) + 255) & ~255;
for(ui=0; ui<unNumParamData; ui++) {
if(paramList->Parameters[ui].Type == PROGRAM_UNIFORM)
{
evergreen->vs.consts[ui][0].f32All = paramListOrginal->ParameterValues[ui][0].f;
evergreen->vs.consts[ui][1].f32All = paramListOrginal->ParameterValues[ui][1].f;
evergreen->vs.consts[ui][2].f32All = paramListOrginal->ParameterValues[ui][2].f;
evergreen->vs.consts[ui][3].f32All = paramListOrginal->ParameterValues[ui][3].f;
}
else
{
evergreen->vs.consts[ui][0].f32All = paramList->ParameterValues[ui][0].f;
evergreen->vs.consts[ui][1].f32All = paramList->ParameterValues[ui][1].f;
evergreen->vs.consts[ui][2].f32All = paramList->ParameterValues[ui][2].f;
evergreen->vs.consts[ui][3].f32All = paramList->ParameterValues[ui][3].f;
}
}
radeonAllocDmaRegion(&context->radeon,
&context->vp_Constbo,
&context->vp_bo_offset,
alloc_size,
256);
r600EmitShaderConsts(ctx,
context->vp_Constbo,
context->vp_bo_offset,
(GLvoid *)&(evergreen->vs.consts[0][0]),
unNumParamData * 4 * 4);
} else
evergreen->vs.num_consts = 0;
COMPILED_SUB * pCompiledSub;
GLuint uj;
GLuint unConstOffset = evergreen->vs.num_consts;
for(ui=0; ui<vp->r700AsmCode.unNumPresub; ui++)
{
pCompiledSub = vp->r700AsmCode.presubs[ui].pCompiledSub;
evergreen->vs.num_consts += pCompiledSub->NumParameters;
for(uj=0; uj<pCompiledSub->NumParameters; uj++)
{
evergreen->vs.consts[uj + unConstOffset][0].f32All = pCompiledSub->ParameterValues[uj][0];
evergreen->vs.consts[uj + unConstOffset][1].f32All = pCompiledSub->ParameterValues[uj][1];
evergreen->vs.consts[uj + unConstOffset][2].f32All = pCompiledSub->ParameterValues[uj][2];
evergreen->vs.consts[uj + unConstOffset][3].f32All = pCompiledSub->ParameterValues[uj][3];
}
unConstOffset += pCompiledSub->NumParameters;
}
return GL_TRUE;
}

109
src/mesa/drivers/dri/r600/evergreen_vertprog.h
View file

@ -1,109 +0,0 @@
/*
* Copyright (C) 2008-2009 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Authors:
* Richard Li <RichardZ.Li@amd.com>, <richardradeon@gmail.com>
*/
#ifndef _EVERGREEN_VERTPROG_H_
#define _EVERGREEN_VERTPROG_H_
#include "main/glheader.h"
#include "main/mtypes.h"
#include "r700_shader.h"
#include "r700_assembler.h"
typedef struct evergreenArrayDesc //TEMP
{
GLint size; //number of data element
GLenum type; //data element type
GLsizei stride;
GLenum format; //GL_RGBA or GL_BGRA
} evergreenArrayDesc;
struct evergreen_vertex_program
{
struct gl_vertex_program *mesa_program; /* Must be first */
struct evergreen_vertex_program *next;
r700_AssemblerBase r700AsmCode;
R700_Shader r700Shader;
GLboolean translated;
GLboolean loaded;
void * shaderbo;
GLuint K0used;
void * constbo0;
evergreenArrayDesc aos_desc[VERT_ATTRIB_MAX];
};
struct evergreen_vertex_program_cont
{
struct gl_vertex_program mesa_program;
struct evergreen_vertex_program *progs;
};
//Internal
unsigned int evergreen_Map_Vertex_Output(r700_AssemblerBase *pAsm,
struct gl_vertex_program *mesa_vp,
unsigned int unStart);
unsigned int evergreen_Map_Vertex_Input(r700_AssemblerBase *pAsm,
struct gl_vertex_program *mesa_vp,
unsigned int unStart);
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions(
struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp);
GLboolean evergreen_Process_Vertex_Program_Vfetch_Instructions2(
struct gl_context *ctx,
struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp);
void evergreen_Map_Vertex_Program(struct gl_context *ctx,
struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp);
GLboolean evergreen_Find_Instruction_Dependencies_vp(struct evergreen_vertex_program *vp,
struct gl_vertex_program *mesa_vp);
struct evergreen_vertex_program* evergreenTranslateVertexShader(struct gl_context *ctx,
struct gl_vertex_program *mesa_vp);
/* Interface */
extern void evergreenSelectVertexShader(struct gl_context *ctx);
extern void evergreenSetVertexFormat(struct gl_context *ctx, const struct gl_client_array *arrays[], int count);
extern GLboolean evergreenSetupVertexProgram(struct gl_context * ctx);
extern GLboolean evergreenSetupVPconstants(struct gl_context * ctx);
extern void * evergreenGetActiveVpShaderBo(struct gl_context * ctx);
extern void * evergreenGetActiveVpShaderConstBo(struct gl_context * ctx);
extern int evergreen_getTypeSize(GLenum type);
#endif /* _EVERGREEN_VERTPROG_H_ */

1767
src/mesa/drivers/dri/r600/r600_blit.c
View file

File diff suppressed because it is too large Load diff

54
src/mesa/drivers/dri/r600/r600_blit.h
View file

@ -1,54 +0,0 @@
/*
* Copyright (C) 2009 Advanced Micro Devices, Inc.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial
* portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef R600_BLIT_H
#define R600_BLIT_H
unsigned r600_check_blit(gl_format mesa_format);
unsigned r600_blit(struct gl_context *ctx,
struct radeon_bo *src_bo,
intptr_t src_offset,
gl_format src_mesaformat,
unsigned src_pitch,
unsigned src_width,
unsigned src_height,
unsigned src_x_offset,
unsigned src_y_offset,
struct radeon_bo *dst_bo,
intptr_t dst_offset,
gl_format dst_mesaformat,
unsigned dst_pitch,
unsigned dst_width,
unsigned dst_height,
unsigned dst_x_offset,
unsigned dst_y_offset,
unsigned w,
unsigned h,
unsigned flip_y);
#endif // R600_BLIT_H

Some files were not shown because too many files have changed in this diff Show more