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aco/gfx12: disallow SCC and most constants for BUF SOFFSET

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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29330>
This commit is contained in:
Rhys Perry 2024-05-21 14:40:57 +01:00 • committed by Marge Bot
parent 12b4bdc134
commit de07fd384d
2 changed files with 5 additions and 0 deletions
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2
src/amd/compiler/aco_register_allocation.cpp
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@ -2089,6 +2089,8 @@ operand_can_use_reg(amd_gfx_level gfx_level, aco_ptr<Instruction>& instr, unsign
(reg != m0 || idx == 1 || idx == 3) && /* offset can be m0 */
(reg != vcc || (instr->definitions.empty() && idx == 2) ||
gfx_level >= GFX10); /* sdata can be vcc */
case Format::MUBUF:
case Format::MTBUF: return idx != 2 || gfx_level < GFX12 || reg != scc;
default:
// TODO: there are more instructions with restrictions on registers
return true;

3
src/amd/compiler/aco_validate.cpp
View file

@ -722,6 +722,9 @@ validate_ir(Program* program)
instr.get());
check(instr->operands.size() < 4 || instr->operands[3].isOfType(RegType::vgpr),
"VMEM write data must be vgpr", instr.get());
if (instr->operands.size() >= 3 && instr->operands[2].isConstant())
check(program->gfx_level < GFX12 || instr->operands[2].constantValue() == 0,
"VMEM SOFFSET must not be non-zero constant on GFX12+", instr.get());
const bool d16 =
instr->opcode ==