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intel/compiler: Use array to iterate the scheduler nodes
For all the preparation data collection before the scheduling actually happens, it is possible to walk the schedule nodes in order by iterating on the range of the array dedicated to a given block. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25841>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
fe6ac5a184
commit
ddff6428c5
1 changed files with 68 additions and 57 deletions
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@ -620,7 +620,7 @@ public:
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this->post_reg_alloc = (mode == SCHEDULE_POST);
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this->mode = mode;
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this->reg_pressure = 0;
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this->block_idx = 0;
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this->last_grf_write = linear_zalloc_array(lin_ctx, schedule_node *, grf_count * grf_write_scale);
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if (!post_reg_alloc) {
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this->reg_pressure_in = linear_zalloc_array(lin_ctx, int, block_count);
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@ -678,6 +678,12 @@ public:
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n++;
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}
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assert(n == nodes + nodes_len);
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current.block = NULL;
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current.start = NULL;
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current.end = NULL;
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current.len = 0;
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current.time = 0;
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}
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~instruction_scheduler()
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@ -690,7 +696,7 @@ public:
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void add_dep(schedule_node *before, schedule_node *after);
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void run(cfg_t *cfg);
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void add_insts_from_block(bblock_t *block);
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void set_current_block(bblock_t *block);
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void compute_delays();
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void compute_exits();
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virtual void calculate_deps() = 0;
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@ -710,7 +716,7 @@ public:
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virtual void update_register_pressure(backend_instruction *inst) = 0;
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virtual int get_register_pressure_benefit(backend_instruction *inst) = 0;
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void schedule_instructions(bblock_t *block);
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void schedule_instructions();
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void *mem_ctx;
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linear_ctx *lin_ctx;
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@ -718,11 +724,24 @@ public:
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schedule_node *nodes;
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int nodes_len;
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/* Current block being processed. */
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struct {
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bblock_t *block;
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/* Range of nodes in the block. End will point to first node
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* address after the block, i.e. the range is [start, end).
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*/
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schedule_node *start;
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schedule_node *end;
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int len;
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int time;
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} current;
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bool post_reg_alloc;
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int grf_count;
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unsigned hw_reg_count;
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int reg_pressure;
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int block_idx;
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exec_list instructions;
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const backend_shader *bs;
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@ -928,6 +947,7 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be)
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{
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fs_inst *inst = (fs_inst *)be;
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int benefit = 0;
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const int block_idx = current.block->num;
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if (inst->dst.file == VGRF) {
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if (!BITSET_TEST(livein[block_idx], inst->dst.nr) &&
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@ -1003,19 +1023,25 @@ vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *)
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}
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void
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instruction_scheduler::add_insts_from_block(bblock_t *block)
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instruction_scheduler::set_current_block(bblock_t *block)
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{
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schedule_node *start = nodes + block->start_ip;
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schedule_node *end = nodes + block->end_ip + 1;
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for (schedule_node *n = start; n < end; n++)
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current.block = block;
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current.start = nodes + block->start_ip;
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current.len = block->end_ip - block->start_ip + 1;
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current.end = current.start + current.len;
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current.time = 0;
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assert(instructions.is_empty());
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for (schedule_node *n = current.start; n < current.end; n++) {
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instructions.push_tail(n);
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}
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}
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/** Computation of the delay member of each node. */
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void
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instruction_scheduler::compute_delays()
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{
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foreach_in_list_reverse(schedule_node, n, &instructions) {
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for (schedule_node *n = current.end - 1; n >= current.start; n--) {
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if (!n->child_count) {
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n->delay = issue_time(n->inst);
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} else {
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@ -1034,7 +1060,7 @@ instruction_scheduler::compute_exits()
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* graph. This is analogous to the node's critical path but calculated
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* from the top instead of from the bottom of the block.
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*/
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foreach_in_list(schedule_node, n, &instructions) {
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for (schedule_node *n = current.start; n < current.end; n++) {
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for (int i = 0; i < n->child_count; i++) {
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n->children[i]->unblocked_time =
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MAX2(n->children[i]->unblocked_time,
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@ -1047,7 +1073,7 @@ instruction_scheduler::compute_exits()
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* nodes of its children which can be unblocked first according to the
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* optimistic unblocked time estimate calculated above.
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*/
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foreach_in_list_reverse(schedule_node, n, &instructions) {
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for (schedule_node *n = current.end - 1; n >= current.start; n--) {
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n->exit = (n->inst->opcode == BRW_OPCODE_HALT ? n : NULL);
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for (int i = 0; i < n->child_count; i++) {
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@ -1150,25 +1176,16 @@ has_cross_lane_access(const fs_inst *inst)
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void
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instruction_scheduler::add_barrier_deps(schedule_node *n)
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{
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schedule_node *prev = (schedule_node *)n->prev;
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schedule_node *next = (schedule_node *)n->next;
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if (prev) {
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while (!prev->is_head_sentinel()) {
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add_dep(prev, n, 0);
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if (is_scheduling_barrier(prev->inst))
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break;
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prev = (schedule_node *)prev->prev;
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}
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for (schedule_node *prev = n - 1; prev >= current.start; prev--) {
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add_dep(prev, n, 0);
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if (is_scheduling_barrier(prev->inst))
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break;
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}
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if (next) {
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while (!next->is_tail_sentinel()) {
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add_dep(n, next, 0);
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if (is_scheduling_barrier(next->inst))
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break;
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next = (schedule_node *)next->next;
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}
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for (schedule_node *next = n + 1; next < current.end; next++) {
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add_dep(n, next, 0);
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if (is_scheduling_barrier(next->inst))
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break;
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}
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}
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@ -1180,14 +1197,9 @@ instruction_scheduler::add_barrier_deps(schedule_node *n)
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void
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instruction_scheduler::add_cross_lane_deps(schedule_node *n)
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{
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schedule_node *prev = (schedule_node *)n->prev;
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if (prev) {
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while (!prev->is_head_sentinel()) {
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if (has_cross_lane_access((fs_inst *)prev->inst))
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add_dep(prev, n, 0);
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prev = (schedule_node *)prev->prev;
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}
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for (schedule_node *prev = n - 1; prev >= current.start; prev--) {
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if (has_cross_lane_access((fs_inst*)prev->inst))
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add_dep(prev, n, 0);
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}
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}
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@ -1215,7 +1227,7 @@ void
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fs_instruction_scheduler::clear_last_grf_write()
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{
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if (!post_reg_alloc) {
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foreach_in_list(schedule_node, n, &instructions) {
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for (schedule_node *n = current.start; n < current.end; n++) {
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fs_inst *inst = (fs_inst *)n->inst;
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if (inst->dst.file == VGRF) {
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@ -1248,7 +1260,7 @@ fs_instruction_scheduler::calculate_deps()
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memset(last_mrf_write, 0, sizeof(last_mrf_write));
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/* top-to-bottom dependencies: RAW and WAW. */
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foreach_in_list(schedule_node, n, &instructions) {
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for (schedule_node *n = current.start; n < current.end; n++) {
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fs_inst *inst = (fs_inst *)n->inst;
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if (is_scheduling_barrier(inst))
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@ -1385,7 +1397,7 @@ fs_instruction_scheduler::calculate_deps()
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last_accumulator_write = NULL;
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last_fixed_grf_write = NULL;
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foreach_in_list_reverse_safe(schedule_node, n, &instructions) {
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for (schedule_node *n = current.end - 1; n >= current.start; n--) {
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fs_inst *inst = (fs_inst *)n->inst;
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/* write-after-read deps. */
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@ -1516,7 +1528,7 @@ vec4_instruction_scheduler::calculate_deps()
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memset(last_mrf_write, 0, sizeof(last_mrf_write));
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/* top-to-bottom dependencies: RAW and WAW. */
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foreach_in_list(schedule_node, n, &instructions) {
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for (schedule_node *n = current.start; n < current.end; n++) {
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vec4_instruction *inst = (vec4_instruction *)n->inst;
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if (is_scheduling_barrier(inst))
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@ -1605,7 +1617,7 @@ vec4_instruction_scheduler::calculate_deps()
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last_accumulator_write = NULL;
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last_fixed_grf_write = NULL;
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foreach_in_list_reverse_safe(schedule_node, n, &instructions) {
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for (schedule_node *n = current.end - 1; n >= current.start; n--) {
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vec4_instruction *inst = (vec4_instruction *)n->inst;
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/* write-after-read deps. */
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@ -1842,18 +1854,17 @@ vec4_instruction_scheduler::issue_time(backend_instruction *)
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}
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void
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instruction_scheduler::schedule_instructions(bblock_t *block)
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instruction_scheduler::schedule_instructions()
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{
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const struct intel_device_info *devinfo = bs->devinfo;
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int time = 0;
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int instructions_to_schedule = block->end_ip - block->start_ip + 1;
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if (!post_reg_alloc)
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reg_pressure = reg_pressure_in[block->num];
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block_idx = block->num;
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reg_pressure = reg_pressure_in[current.block->num];
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int scheduled = 0;
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/* Remove non-DAG heads from the list. */
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foreach_in_list_safe(schedule_node, n, &instructions) {
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for (schedule_node *n = current.start; n < current.end; n++) {
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if (n->parent_count != 0)
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n->remove();
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}
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@ -1866,8 +1877,8 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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assert(chosen);
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chosen->remove();
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chosen->inst->exec_node::remove();
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block->instructions.push_tail(chosen->inst);
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instructions_to_schedule--;
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current.block->instructions.push_tail(chosen->inst);
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scheduled++;
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if (!post_reg_alloc) {
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reg_pressure -= get_register_pressure_benefit(chosen->inst);
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@ -1880,15 +1891,15 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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* we're unblocked. After this, we have the time when the chosen
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* instruction will start executing.
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*/
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time = MAX2(time, chosen->unblocked_time);
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current.time = MAX2(current.time, chosen->unblocked_time);
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/* Update the clock for how soon an instruction could start after the
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* chosen one.
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*/
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time += issue_time(chosen->inst);
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current.time += issue_time(chosen->inst);
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if (debug) {
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fprintf(stderr, "clock %4d, scheduled: ", time);
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fprintf(stderr, "clock %4d, scheduled: ", current.time);
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bs->dump_instruction(chosen->inst);
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if (!post_reg_alloc)
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fprintf(stderr, "(register pressure %d)\n", reg_pressure);
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@ -1903,7 +1914,7 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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schedule_node *child = chosen->children[i];
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child->unblocked_time = MAX2(child->unblocked_time,
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time + chosen->child_latency[i]);
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current.time + chosen->child_latency[i]);
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if (debug) {
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fprintf(stderr, "\tchild %d, %d parents: ", i, child->parent_count);
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@ -1930,12 +1941,12 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
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foreach_in_list(schedule_node, n, &instructions) {
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if (n->inst->is_math())
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n->unblocked_time = MAX2(n->unblocked_time,
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time + chosen->latency);
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current.time + chosen->latency);
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}
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}
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}
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assert(instructions_to_schedule == 0);
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assert(scheduled == current.len);
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}
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void
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@ -1964,14 +1975,14 @@ instruction_scheduler::run(cfg_t *cfg)
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count_reads_remaining(inst);
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}
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add_insts_from_block(block);
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set_current_block(block);
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calculate_deps();
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compute_delays();
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compute_exits();
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schedule_instructions(block);
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schedule_instructions();
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}
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if (debug && !post_reg_alloc) {
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