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winsys/amdgpu: userq job log fwm packet debug count
Add WRITE_DATA packet before and after FENCE_WAIT_MULTI packet. Based on the last number written in WRITE_DATA packet buffer, it can be found if FENCE_WAIT_MULTI packet passed or not in CP firmware. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39206>
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2547fd0f59
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3 changed files with 39 additions and 5 deletions
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@ -1416,6 +1416,15 @@ struct cond_exec_skip_count {
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uint64_t start_wptr;
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};
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#define add_dbg_count_write_data_pkt(number) do { \
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amdgpu_pkt_add_dw(PKT3(PKT3_WRITE_DATA, 4, 0)); \
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amdgpu_pkt_add_dw(WRITE_DATA_DST_SEL(5) | WRITE_DATA_WR_CONFIRM | WRITE_DATA_CACHE_POLICY(3)); \
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amdgpu_pkt_add_dw(userq->write_data_pkt_dbg_count_va); \
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amdgpu_pkt_add_dw(userq->write_data_pkt_dbg_count_va >> 32); \
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amdgpu_pkt_add_dw(number); \
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amdgpu_pkt_add_dw((uint64_t)number >> 32); \
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} while (0)
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static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws,
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struct amdgpu_userq *userq,
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struct amdgpu_cs_context *csc,
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@ -1441,6 +1450,9 @@ static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws,
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cond_exec_skip_counts[0].start_wptr = amdgpu_pkt_get_next_wptr();
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}
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if (aws->userq_job_log)
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add_dbg_count_write_data_pkt(1);
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if (num_fences) {
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unsigned max_num_fences_fwm;
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unsigned num_fences_in_iter;
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@ -1473,6 +1485,9 @@ static void amdgpu_cs_add_userq_packets(struct amdgpu_winsys *aws,
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}
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}
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if (aws->userq_job_log)
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add_dbg_count_write_data_pkt(2);
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amdgpu_pkt_add_dw(PKT3(PKT3_HDP_FLUSH, 0, 0));
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amdgpu_pkt_add_dw(0x0);
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@ -29,7 +29,8 @@ static bool
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amdgpu_userq_ring_init(struct amdgpu_winsys *aws, struct amdgpu_userq *userq,
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uint64_t *vm_timeline_point_to_wait)
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{
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/* Allocate ring and user fence in one buffer. */
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/* Allocate ring and user fence in one buffer. Also allocate for wait packet debug count
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* variable. */
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uint32_t gtt_bo_size = AMDGPU_USERQ_RING_SIZE + aws->info.gart_page_size;
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userq->gtt_bo = amdgpu_bo_create(aws, gtt_bo_size, 256, RADEON_DOMAIN_GTT,
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RADEON_FLAG_GL2_BYPASS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
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@ -59,6 +60,12 @@ amdgpu_userq_ring_init(struct amdgpu_winsys *aws, struct amdgpu_userq *userq,
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*userq->wptr_bo_map = 0;
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userq->next_wptr = 0;
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userq->write_data_pkt_dbg_count_ptr = (uint64_t*)(userq->gtt_bo_map +
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AMDGPU_USERQ_RING_SIZE + 8);
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userq->write_data_pkt_dbg_count_va = amdgpu_bo_get_va(userq->gtt_bo) +
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AMDGPU_USERQ_RING_SIZE + 8;
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*userq->write_data_pkt_dbg_count_ptr = 0;
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/* Allocate memory for rptr. */
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userq->vram_bo = amdgpu_bo_create(aws, aws->info.gart_page_size, 256, RADEON_DOMAIN_VRAM,
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RADEON_FLAG_CLEAR_VRAM | RADEON_FLAG_GL2_BYPASS |
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@ -85,14 +92,18 @@ userq_job_log_thread(void *data)
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if (userq->userq_handle) {
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uint64_t last_submitted_job = *userq->wptr_bo_map;
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uint64_t last_completed_job = *userq->user_fence_ptr;
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uint64_t last_write_data_pkt_dbg_count = *userq->write_data_pkt_dbg_count_ptr;
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if (userq->last_submitted_job != last_submitted_job ||
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userq->last_completed_job != last_completed_job) {
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mesa_logi("amdgpu: uq_log: %s: submitted_job=%llx completed_job=%llx\n",
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amdgpu_userq_str[i], (long long)last_submitted_job,
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(long long)last_completed_job);
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userq->last_completed_job != last_completed_job ||
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userq->last_write_data_pkt_dbg_count != last_write_data_pkt_dbg_count) {
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mesa_logi("amdgpu: uq_log: %s: submitted_job=%llx completed_job=%llx"
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" write_data_pkt_dbg_count=%llx\n", amdgpu_userq_str[i],
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(long long)last_submitted_job, (long long)last_completed_job,
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(long long)last_write_data_pkt_dbg_count);
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userq->last_submitted_job = last_submitted_job;
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userq->last_completed_job = last_completed_job;
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userq->last_write_data_pkt_dbg_count = last_write_data_pkt_dbg_count;
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}
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}
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}
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@ -79,6 +79,13 @@ struct amdgpu_userq {
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struct pb_buffer_lean *doorbell_bo;
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uint64_t *doorbell_bo_map;
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/* For debugging where the ring is stuck, WRITE_DATA packet with unique number is
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* inserted in the ring. The number will indicate the packets that are parsed by CP.
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* This value is printed in job log.
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*/
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uint64_t *write_data_pkt_dbg_count_ptr;
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uint64_t write_data_pkt_dbg_count_va;
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/* In case of gfx11.5 shadow register address has to be initialized using LOAD_* packet.
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* Also for every new ib/job submission, the shadowed registers has to be loaded using LOAD_*
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* packets.
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@ -103,6 +110,7 @@ struct amdgpu_userq {
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/* Used in userq job log thread to only print if data has changed */
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uint64_t last_submitted_job;
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uint64_t last_completed_job;
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uint64_t last_write_data_pkt_dbg_count;
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};
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void
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