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i965/vec4: inline generate_vec4_instruction() within generate_code()
Suggested by Matt. This patch combines and moves back the code-generation functions from generate_vec4_instruction() into generate_code(). Makes generate_code() a bit larger, but helps us to count loops in a straightforward manner. Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
This commit is contained in:
Abdiel Janulgue
parent
e34a363a78
commit
ddc1d297bc
2 changed files with 320 additions and 340 deletions
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@ -627,9 +627,6 @@ public:
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private:
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void generate_code(const cfg_t *cfg);
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void generate_vec4_instruction(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg *src);
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void generate_math1_gen4(vec4_instruction *inst,
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struct brw_reg dst,
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@ -977,342 +977,6 @@ vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
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brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
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}
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/**
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* Generate assembly for a Vec4 IR instruction.
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*
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* \param instruction The Vec4 IR instruction to generate code for.
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* \param dst The destination register.
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* \param src An array of up to three source registers.
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*/
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void
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vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
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struct brw_reg dst,
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struct brw_reg *src)
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{
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vec4_instruction *inst = (vec4_instruction *) instruction;
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if (dst.width == BRW_WIDTH_4) {
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/* This happens in attribute fixups for "dual instanced" geometry
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* shaders, since they use attributes that are vec4's. Since the exec
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* width is only 4, it's essential that the caller set
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* force_writemask_all in order to make sure the instruction is executed
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* regardless of which channels are enabled.
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*/
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assert(inst->force_writemask_all);
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/* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
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* the following register region restrictions (from Graphics BSpec:
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* 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
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* > Register Region Restrictions)
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*
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* 1. ExecSize must be greater than or equal to Width.
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*
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* 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
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* to Width * HorzStride."
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*/
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for (int i = 0; i < 3; i++) {
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if (src[i].file == BRW_GENERAL_REGISTER_FILE)
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src[i] = stride(src[i], 4, 4, 1);
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}
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}
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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brw_MOV(p, dst, src[0]);
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break;
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case BRW_OPCODE_ADD:
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brw_ADD(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MUL:
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brw_MUL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MACH:
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brw_MACH(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MAD:
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assert(brw->gen >= 6);
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brw_MAD(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_FRC:
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brw_FRC(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDD:
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brw_RNDD(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDE:
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brw_RNDE(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDZ:
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brw_RNDZ(p, dst, src[0]);
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break;
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case BRW_OPCODE_AND:
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brw_AND(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_OR:
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brw_OR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_XOR:
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brw_XOR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_NOT:
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brw_NOT(p, dst, src[0]);
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break;
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case BRW_OPCODE_ASR:
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brw_ASR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHR:
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brw_SHR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHL:
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brw_SHL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_CMP:
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brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
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break;
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case BRW_OPCODE_SEL:
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brw_SEL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DPH:
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brw_DPH(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP4:
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brw_DP4(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP3:
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brw_DP3(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP2:
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brw_DP2(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_F32TO16:
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assert(brw->gen >= 7);
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brw_F32TO16(p, dst, src[0]);
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break;
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case BRW_OPCODE_F16TO32:
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assert(brw->gen >= 7);
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brw_F16TO32(p, dst, src[0]);
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break;
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case BRW_OPCODE_LRP:
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assert(brw->gen >= 6);
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brw_LRP(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_BFREV:
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assert(brw->gen >= 7);
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/* BFREV only supports UD type for src and dst. */
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brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
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retype(src[0], BRW_REGISTER_TYPE_UD));
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break;
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case BRW_OPCODE_FBH:
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assert(brw->gen >= 7);
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/* FBH only supports UD type for dst. */
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brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_FBL:
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assert(brw->gen >= 7);
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/* FBL only supports UD type for dst. */
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brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_CBIT:
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assert(brw->gen >= 7);
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/* CBIT only supports UD type for dst. */
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brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_ADDC:
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assert(brw->gen >= 7);
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brw_ADDC(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SUBB:
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assert(brw->gen >= 7);
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brw_SUBB(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MAC:
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brw_MAC(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_BFE:
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assert(brw->gen >= 7);
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brw_BFE(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_BFI1:
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assert(brw->gen >= 7);
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brw_BFI1(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_BFI2:
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assert(brw->gen >= 7);
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brw_BFI2(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_IF:
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if (inst->src[0].file != BAD_FILE) {
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/* The instruction has an embedded compare (only allowed on gen6) */
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assert(brw->gen == 6);
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gen6_IF(p, inst->conditional_mod, src[0], src[1]);
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} else {
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brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
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brw_inst_set_pred_control(brw, if_inst, inst->predicate);
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}
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break;
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case BRW_OPCODE_ELSE:
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brw_ELSE(p);
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break;
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case BRW_OPCODE_ENDIF:
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brw_ENDIF(p);
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break;
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case BRW_OPCODE_DO:
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brw_DO(p, BRW_EXECUTE_8);
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break;
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case BRW_OPCODE_BREAK:
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brw_BREAK(p);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
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break;
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case BRW_OPCODE_CONTINUE:
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brw_CONT(p);
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brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
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break;
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case BRW_OPCODE_WHILE:
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brw_WHILE(p);
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break;
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SQRT:
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case SHADER_OPCODE_EXP2:
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case SHADER_OPCODE_LOG2:
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case SHADER_OPCODE_SIN:
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case SHADER_OPCODE_COS:
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if (brw->gen >= 7) {
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gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
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brw_null_reg());
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} else if (brw->gen == 6) {
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generate_math_gen6(inst, dst, src[0], brw_null_reg());
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} else {
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generate_math1_gen4(inst, dst, src[0]);
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}
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break;
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case SHADER_OPCODE_POW:
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case SHADER_OPCODE_INT_QUOTIENT:
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case SHADER_OPCODE_INT_REMAINDER:
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if (brw->gen >= 7) {
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gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
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} else if (brw->gen == 6) {
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generate_math_gen6(inst, dst, src[0], src[1]);
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} else {
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generate_math2_gen4(inst, dst, src[0], src[1]);
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}
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break;
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case SHADER_OPCODE_TEX:
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case SHADER_OPCODE_TXD:
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case SHADER_OPCODE_TXF:
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case SHADER_OPCODE_TXF_CMS:
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case SHADER_OPCODE_TXF_MCS:
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case SHADER_OPCODE_TXL:
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case SHADER_OPCODE_TXS:
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case SHADER_OPCODE_TG4:
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case SHADER_OPCODE_TG4_OFFSET:
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generate_tex(inst, dst, src[0], src[1]);
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break;
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case VS_OPCODE_URB_WRITE:
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generate_vs_urb_write(inst);
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break;
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case SHADER_OPCODE_GEN4_SCRATCH_READ:
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generate_scratch_read(inst, dst, src[0]);
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break;
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case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
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generate_scratch_write(inst, dst, src[0], src[1]);
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break;
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case VS_OPCODE_PULL_CONSTANT_LOAD:
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generate_pull_constant_load(inst, dst, src[0], src[1]);
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break;
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case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
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generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
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break;
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case GS_OPCODE_URB_WRITE:
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generate_gs_urb_write(inst);
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break;
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case GS_OPCODE_THREAD_END:
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generate_gs_thread_end(inst);
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break;
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case GS_OPCODE_SET_WRITE_OFFSET:
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generate_gs_set_write_offset(dst, src[0], src[1]);
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break;
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case GS_OPCODE_SET_VERTEX_COUNT:
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generate_gs_set_vertex_count(dst, src[0]);
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break;
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case GS_OPCODE_SET_DWORD_2_IMMED:
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generate_gs_set_dword_2_immed(dst, src[0]);
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break;
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case GS_OPCODE_PREPARE_CHANNEL_MASKS:
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generate_gs_prepare_channel_masks(dst);
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break;
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case GS_OPCODE_SET_CHANNEL_MASKS:
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generate_gs_set_channel_masks(dst, src[0]);
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break;
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case GS_OPCODE_GET_INSTANCE_ID:
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generate_gs_get_instance_id(dst);
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break;
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case SHADER_OPCODE_SHADER_TIME_ADD:
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brw_shader_time_add(p, src[0],
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prog_data->base.binding_table.shader_time_start);
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brw_mark_surface_used(&prog_data->base,
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prog_data->base.binding_table.shader_time_start);
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break;
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case SHADER_OPCODE_UNTYPED_ATOMIC:
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generate_untyped_atomic(inst, dst, src[0], src[1]);
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break;
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case SHADER_OPCODE_UNTYPED_SURFACE_READ:
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generate_untyped_surface_read(inst, dst, src[0]);
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break;
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case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
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generate_unpack_flags(inst, dst);
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break;
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default:
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if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
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_mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
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opcode_descs[inst->opcode].name);
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} else {
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_mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
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}
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abort();
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}
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}
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void
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vec4_generator::generate_code(const cfg_t *cfg)
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{
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@ -1338,7 +1002,326 @@ vec4_generator::generate_code(const cfg_t *cfg)
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unsigned pre_emit_nr_insn = p->nr_insn;
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generate_vec4_instruction(inst, dst, src);
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if (dst.width == BRW_WIDTH_4) {
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/* This happens in attribute fixups for "dual instanced" geometry
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* shaders, since they use attributes that are vec4's. Since the exec
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* width is only 4, it's essential that the caller set
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* force_writemask_all in order to make sure the instruction is executed
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* regardless of which channels are enabled.
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*/
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assert(inst->force_writemask_all);
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/* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
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* the following register region restrictions (from Graphics BSpec:
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* 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
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* > Register Region Restrictions)
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*
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* 1. ExecSize must be greater than or equal to Width.
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*
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* 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
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* to Width * HorzStride."
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*/
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for (int i = 0; i < 3; i++) {
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if (src[i].file == BRW_GENERAL_REGISTER_FILE)
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src[i] = stride(src[i], 4, 4, 1);
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}
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}
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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brw_MOV(p, dst, src[0]);
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break;
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case BRW_OPCODE_ADD:
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brw_ADD(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MUL:
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brw_MUL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MACH:
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brw_MACH(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MAD:
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assert(brw->gen >= 6);
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brw_MAD(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_FRC:
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brw_FRC(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDD:
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brw_RNDD(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDE:
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brw_RNDE(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDZ:
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brw_RNDZ(p, dst, src[0]);
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break;
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case BRW_OPCODE_AND:
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brw_AND(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_OR:
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brw_OR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_XOR:
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brw_XOR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_NOT:
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brw_NOT(p, dst, src[0]);
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break;
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case BRW_OPCODE_ASR:
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brw_ASR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHR:
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brw_SHR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHL:
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brw_SHL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_CMP:
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brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
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break;
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case BRW_OPCODE_SEL:
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brw_SEL(p, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_DPH:
|
||||
brw_DPH(p, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_DP4:
|
||||
brw_DP4(p, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_DP3:
|
||||
brw_DP3(p, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_DP2:
|
||||
brw_DP2(p, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_F32TO16:
|
||||
assert(brw->gen >= 7);
|
||||
brw_F32TO16(p, dst, src[0]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_F16TO32:
|
||||
assert(brw->gen >= 7);
|
||||
brw_F16TO32(p, dst, src[0]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_LRP:
|
||||
assert(brw->gen >= 6);
|
||||
brw_LRP(p, dst, src[0], src[1], src[2]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_BFREV:
|
||||
assert(brw->gen >= 7);
|
||||
/* BFREV only supports UD type for src and dst. */
|
||||
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
|
||||
retype(src[0], BRW_REGISTER_TYPE_UD));
|
||||
break;
|
||||
case BRW_OPCODE_FBH:
|
||||
assert(brw->gen >= 7);
|
||||
/* FBH only supports UD type for dst. */
|
||||
brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
|
||||
break;
|
||||
case BRW_OPCODE_FBL:
|
||||
assert(brw->gen >= 7);
|
||||
/* FBL only supports UD type for dst. */
|
||||
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
|
||||
break;
|
||||
case BRW_OPCODE_CBIT:
|
||||
assert(brw->gen >= 7);
|
||||
/* CBIT only supports UD type for dst. */
|
||||
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
|
||||
break;
|
||||
case BRW_OPCODE_ADDC:
|
||||
assert(brw->gen >= 7);
|
||||
brw_ADDC(p, dst, src[0], src[1]);
|
||||
break;
|
||||
case BRW_OPCODE_SUBB:
|
||||
assert(brw->gen >= 7);
|
||||
brw_SUBB(p, dst, src[0], src[1]);
|
||||
break;
|
||||
case BRW_OPCODE_MAC:
|
||||
brw_MAC(p, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_BFE:
|
||||
assert(brw->gen >= 7);
|
||||
brw_BFE(p, dst, src[0], src[1], src[2]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_BFI1:
|
||||
assert(brw->gen >= 7);
|
||||
brw_BFI1(p, dst, src[0], src[1]);
|
||||
break;
|
||||
case BRW_OPCODE_BFI2:
|
||||
assert(brw->gen >= 7);
|
||||
brw_BFI2(p, dst, src[0], src[1], src[2]);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_IF:
|
||||
if (inst->src[0].file != BAD_FILE) {
|
||||
/* The instruction has an embedded compare (only allowed on gen6) */
|
||||
assert(brw->gen == 6);
|
||||
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
|
||||
} else {
|
||||
brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
|
||||
brw_inst_set_pred_control(brw, if_inst, inst->predicate);
|
||||
}
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_ELSE:
|
||||
brw_ELSE(p);
|
||||
break;
|
||||
case BRW_OPCODE_ENDIF:
|
||||
brw_ENDIF(p);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_DO:
|
||||
brw_DO(p, BRW_EXECUTE_8);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_BREAK:
|
||||
brw_BREAK(p);
|
||||
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
|
||||
break;
|
||||
case BRW_OPCODE_CONTINUE:
|
||||
brw_CONT(p);
|
||||
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
|
||||
break;
|
||||
|
||||
case BRW_OPCODE_WHILE:
|
||||
brw_WHILE(p);
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_RCP:
|
||||
case SHADER_OPCODE_RSQ:
|
||||
case SHADER_OPCODE_SQRT:
|
||||
case SHADER_OPCODE_EXP2:
|
||||
case SHADER_OPCODE_LOG2:
|
||||
case SHADER_OPCODE_SIN:
|
||||
case SHADER_OPCODE_COS:
|
||||
if (brw->gen >= 7) {
|
||||
gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
|
||||
brw_null_reg());
|
||||
} else if (brw->gen == 6) {
|
||||
generate_math_gen6(inst, dst, src[0], brw_null_reg());
|
||||
} else {
|
||||
generate_math1_gen4(inst, dst, src[0]);
|
||||
}
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_POW:
|
||||
case SHADER_OPCODE_INT_QUOTIENT:
|
||||
case SHADER_OPCODE_INT_REMAINDER:
|
||||
if (brw->gen >= 7) {
|
||||
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
|
||||
} else if (brw->gen == 6) {
|
||||
generate_math_gen6(inst, dst, src[0], src[1]);
|
||||
} else {
|
||||
generate_math2_gen4(inst, dst, src[0], src[1]);
|
||||
}
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_TEX:
|
||||
case SHADER_OPCODE_TXD:
|
||||
case SHADER_OPCODE_TXF:
|
||||
case SHADER_OPCODE_TXF_CMS:
|
||||
case SHADER_OPCODE_TXF_MCS:
|
||||
case SHADER_OPCODE_TXL:
|
||||
case SHADER_OPCODE_TXS:
|
||||
case SHADER_OPCODE_TG4:
|
||||
case SHADER_OPCODE_TG4_OFFSET:
|
||||
generate_tex(inst, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case VS_OPCODE_URB_WRITE:
|
||||
generate_vs_urb_write(inst);
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_GEN4_SCRATCH_READ:
|
||||
generate_scratch_read(inst, dst, src[0]);
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
|
||||
generate_scratch_write(inst, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case VS_OPCODE_PULL_CONSTANT_LOAD:
|
||||
generate_pull_constant_load(inst, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
|
||||
generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_URB_WRITE:
|
||||
generate_gs_urb_write(inst);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_THREAD_END:
|
||||
generate_gs_thread_end(inst);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_SET_WRITE_OFFSET:
|
||||
generate_gs_set_write_offset(dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_SET_VERTEX_COUNT:
|
||||
generate_gs_set_vertex_count(dst, src[0]);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_SET_DWORD_2_IMMED:
|
||||
generate_gs_set_dword_2_immed(dst, src[0]);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_PREPARE_CHANNEL_MASKS:
|
||||
generate_gs_prepare_channel_masks(dst);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_SET_CHANNEL_MASKS:
|
||||
generate_gs_set_channel_masks(dst, src[0]);
|
||||
break;
|
||||
|
||||
case GS_OPCODE_GET_INSTANCE_ID:
|
||||
generate_gs_get_instance_id(dst);
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_SHADER_TIME_ADD:
|
||||
brw_shader_time_add(p, src[0],
|
||||
prog_data->base.binding_table.shader_time_start);
|
||||
brw_mark_surface_used(&prog_data->base,
|
||||
prog_data->base.binding_table.shader_time_start);
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_UNTYPED_ATOMIC:
|
||||
generate_untyped_atomic(inst, dst, src[0], src[1]);
|
||||
break;
|
||||
|
||||
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
|
||||
generate_untyped_surface_read(inst, dst, src[0]);
|
||||
break;
|
||||
|
||||
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
|
||||
generate_unpack_flags(inst, dst);
|
||||
break;
|
||||
|
||||
default:
|
||||
if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
|
||||
_mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
|
||||
opcode_descs[inst->opcode].name);
|
||||
} else {
|
||||
_mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
|
||||
}
|
||||
abort();
|
||||
}
|
||||
|
||||
if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
|
||||
assert(p->nr_insn == pre_emit_nr_insn + 1 ||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue