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intel/vec4: Delete vec4_visitor::emit_lrp
Effectivley unused since dd7135d55d ("intel/compiler: Use the flrp
lowering pass for all stages on Gen4 and Gen5"). I had intended to
remove this code as part of that series, but I forgot.
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
parent
5450fd7a36
commit
dd2dc7e707
3 changed files with 5 additions and 32 deletions
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@ -236,9 +236,6 @@ public:
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vec4_instruction *emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
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src_reg src0, src_reg src1);
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vec4_instruction *emit_lrp(const dst_reg &dst, const src_reg &x,
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const src_reg &y, const src_reg &a);
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/**
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* Copy any live channel from \p src to the first channel of the
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* result.
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@ -1926,7 +1926,11 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
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break;
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case nir_op_flrp:
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inst = emit_lrp(dst, op[0], op[1], op[2]);
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op[0] = fix_3src_operand(op[0]);
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op[1] = fix_3src_operand(op[1]);
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op[2] = fix_3src_operand(op[2]);
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inst = emit(LRP(dst, op[2], op[1], op[0]));
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inst->saturate = instr->dest.saturate;
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break;
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@ -736,34 +736,6 @@ vec4_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
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return inst;
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}
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vec4_instruction *
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vec4_visitor::emit_lrp(const dst_reg &dst,
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const src_reg &x, const src_reg &y, const src_reg &a)
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{
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if (devinfo->gen >= 6 && devinfo->gen <= 10) {
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/* Note that the instruction's argument order is reversed from GLSL
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* and the IR.
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*/
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return emit(LRP(dst, fix_3src_operand(a), fix_3src_operand(y),
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fix_3src_operand(x)));
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} else {
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/* Earlier generations don't support three source operations, so we
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* need to emit x*(1-a) + y*a.
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*/
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dst_reg y_times_a = dst_reg(this, glsl_type::vec4_type);
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dst_reg one_minus_a = dst_reg(this, glsl_type::vec4_type);
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dst_reg x_times_one_minus_a = dst_reg(this, glsl_type::vec4_type);
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y_times_a.writemask = dst.writemask;
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one_minus_a.writemask = dst.writemask;
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x_times_one_minus_a.writemask = dst.writemask;
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emit(MUL(y_times_a, y, a));
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emit(ADD(one_minus_a, negate(a), brw_imm_f(1.0f)));
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emit(MUL(x_times_one_minus_a, x, src_reg(one_minus_a)));
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return emit(ADD(dst, src_reg(x_times_one_minus_a), src_reg(y_times_a)));
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}
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}
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/**
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* Emits the instructions needed to perform a pull constant load. before_block
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* and before_inst can be NULL in which case the instruction will be appended
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