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r600/sfn: Stop passing around nir_dest and nir_alu_dest

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We want to get rid of nir_dest and nir_alu_dest so back-ends need to
stop storing it in structs and passing it through helpers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24674>
This commit is contained in:
Faith Ekstrand 2023-08-14 09:53:12 -05:00 • committed by Marge Bot
parent 734b15186b
commit dd2178060d
13 changed files with 137 additions and 156 deletions
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100
src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp
View file

@ -1926,13 +1926,13 @@ emit_alu_op1_64bit(const nir_alu_instr& alu,
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest, 2 * i, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_chan),
value_factory.src64(alu.src[0], i, swz[0]),
{alu_write});
group->add_instruction(ir);
ir = new AluInstr(opcode,
value_factory.dest(alu.dest, 2 * i + 1, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 2 * i + 1, pin_chan),
value_factory.src64(alu.src[0], i, swz[1]),
{alu_write});
group->add_instruction(ir);
@ -1953,7 +1953,7 @@ emit_alu_mov_64bit(const nir_alu_instr& alu, Shader& shader)
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
for (unsigned c = 0; c < 2; ++c) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, 2 * i + c, pin_free),
value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_free),
value_factory.src64(alu.src[0], i, c),
{alu_write});
shader.emit_instruction(ir);
@ -1974,7 +1974,7 @@ emit_alu_neg(const nir_alu_instr& alu, Shader& shader)
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
for (unsigned c = 0; c < 2; ++c) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, 2 * i + c, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_chan),
value_factory.src64(alu.src[0], i, c),
{alu_write});
shader.emit_instruction(ir);
@ -1995,12 +1995,12 @@ emit_alu_abs64(const nir_alu_instr& alu, Shader& shader)
assert(nir_dest_num_components(alu.dest.dest) == 1);
shader.emit_instruction(new AluInstr(op1_mov,
value_factory.dest(alu.dest, 0, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 0),
AluInstr::write));
auto ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, 1, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
AluInstr::last_write);
ir->set_source_mod(0, AluInstr::mod_abs);
@ -2048,13 +2048,13 @@ emit_alu_fsat64(const nir_alu_instr& alu, Shader& shader)
if (try_propagat_fsat64(alu, shader)) {
auto ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, 0, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 0),
AluInstr::write);
shader.emit_instruction(ir);
shader.emit_instruction(new AluInstr(op1_mov,
value_factory.dest(alu.dest, 1, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
AluInstr::last_write));
} else {
@ -2064,7 +2064,7 @@ emit_alu_fsat64(const nir_alu_instr& alu, Shader& shader)
auto group = new AluGroup();
auto ir = new AluInstr(op2_add_64,
value_factory.dest(alu.dest, 0, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
value_factory.literal(0),
AluInstr::write);
@ -2072,7 +2072,7 @@ emit_alu_fsat64(const nir_alu_instr& alu, Shader& shader)
group->add_instruction(ir);
group->add_instruction(new AluInstr(op2_add_64,
value_factory.dest(alu.dest, 1, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
value_factory.src64(alu.src[0], 0, 0),
value_factory.literal(0),
AluInstr::last_write));
@ -2105,7 +2105,7 @@ emit_alu_op2_64bit(const nir_alu_instr& alu,
for (unsigned k = 0; k < nir_dest_num_components(alu.dest.dest); ++k) {
int i = 0;
for (; i < num_emit0; ++i) {
auto dest = i < 2 ? value_factory.dest(alu.dest, i, pin_chan)
auto dest = i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan)
: value_factory.dummy_dest(i);
ir = new AluInstr(opcode,
@ -2117,7 +2117,7 @@ emit_alu_op2_64bit(const nir_alu_instr& alu,
}
auto dest =
i == 1 ? value_factory.dest(alu.dest, i, pin_chan) : value_factory.dummy_dest(i);
i == 1 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) : value_factory.dummy_dest(i);
ir = new AluInstr(opcode,
dest,
@ -2150,7 +2150,7 @@ emit_alu_op2_64bit_one_dst(const nir_alu_instr& alu,
AluInstr::SrcValues src(4);
for (unsigned k = 0; k < nir_dest_num_components(alu.dest.dest); ++k) {
auto dest = value_factory.dest(alu.dest, 2 * k, pin_chan);
auto dest = value_factory.dest(alu.dest.dest.ssa, 2 * k, pin_chan);
src[0] = value_factory.src64(alu.src[order[0]], k, 1);
src[1] = value_factory.src64(alu.src[order[1]], k, 1);
src[2] = value_factory.src64(alu.src[order[0]], k, 0);
@ -2175,7 +2175,7 @@ emit_alu_op1_64bit_trans(const nir_alu_instr& alu, EAluOp opcode, Shader& shader
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 3; ++i) {
ir = new AluInstr(opcode,
i < 2 ? value_factory.dest(alu.dest, i, pin_chan)
i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan)
: value_factory.dummy_dest(i),
value_factory.src64(alu.src[0], 0, 1),
value_factory.src64(alu.src[0], 0, 0),
@ -2201,7 +2201,7 @@ emit_alu_fma_64bit(const nir_alu_instr& alu, EAluOp opcode, Shader& shader)
int chan = i < 3 ? 1 : 0;
auto dest =
i < 2 ? value_factory.dest(alu.dest, i, pin_chan) : value_factory.dummy_dest(i);
i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) : value_factory.dummy_dest(i);
ir = new AluInstr(opcode,
dest,
@ -2226,14 +2226,14 @@ emit_alu_b2f64(const nir_alu_instr& alu, Shader& shader)
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(op2_and_int,
value_factory.dest(alu.dest, 2 * i, pin_group),
value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_group),
value_factory.src(alu.src[0], i),
value_factory.zero(),
{alu_write});
group->add_instruction(ir);
ir = new AluInstr(op2_and_int,
value_factory.dest(alu.dest, 2 * i + 1, pin_group),
value_factory.dest(alu.dest.dest.ssa, 2 * i + 1, pin_group),
value_factory.src(alu.src[0], i),
value_factory.literal(0x3ff00000),
{alu_write});
@ -2292,13 +2292,13 @@ emit_alu_i2f64(const nir_alu_instr& alu, EAluOp op, Shader& shader)
group = new AluGroup();
ir = new AluInstr(op2_add_64,
value_factory.dest(alu.dest, 0, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
tmpy3,
tmpw3,
AluInstr::write);
group->add_instruction(ir);
ir = new AluInstr(op2_add_64,
value_factory.dest(alu.dest, 1, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
tmpx3,
tmpz3,
AluInstr::write);
@ -2318,12 +2318,12 @@ emit_alu_f2f64(const nir_alu_instr& alu, Shader& shader)
assert(nir_dest_num_components(alu.dest.dest) == 1);
ir = new AluInstr(op1_flt32_to_flt64,
value_factory.dest(alu.dest, 0, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
value_factory.src(alu.src[0], 0),
AluInstr::write);
group->add_instruction(ir);
ir = new AluInstr(op1_flt32_to_flt64,
value_factory.dest(alu.dest, 1, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 1, pin_chan),
value_factory.zero(),
AluInstr::last_write);
group->add_instruction(ir);
@ -2339,7 +2339,7 @@ emit_alu_f2f32(const nir_alu_instr& alu, Shader& shader)
AluInstr *ir = nullptr;
ir = new AluInstr(op1v_flt64_to_flt32,
value_factory.dest(alu.dest, 0, pin_chan),
value_factory.dest(alu.dest.dest.ssa, 0, pin_chan),
value_factory.src64(alu.src[0], 0, 1),
{alu_write});
group->add_instruction(ir);
@ -2362,7 +2362,7 @@ emit_alu_b2x(const nir_alu_instr& alu, AluInlineConstants mask, Shader& shader)
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
auto src = value_factory.src(alu.src[0], i);
ir = new AluInstr(op2_and_int,
value_factory.dest(alu.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
src,
value_factory.inline_const(mask, 0),
{alu_write});
@ -2386,7 +2386,7 @@ emit_alu_op1(const nir_alu_instr& alu,
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(alu.src[0], i),
{alu_write});
switch (mod) {
@ -2428,7 +2428,7 @@ emit_alu_op2(const nir_alu_instr& alu,
AluInstr *ir = nullptr;
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(*src0, i),
value_factory.src(*src1, i),
{alu_write});
@ -2466,7 +2466,7 @@ emit_alu_op3(const nir_alu_instr& alu,
AluInstr *ir = nullptr;
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(*src[0], i),
value_factory.src(*src[1], i),
value_factory.src(*src[2], i),
@ -2501,7 +2501,7 @@ emit_any_all_fcomp2(const nir_alu_instr& alu, EAluOp opcode, Shader& shader)
opcode = (opcode == op2_setne_dx10) ? op2_or_int : op2_and_int;
ir = new AluInstr(opcode,
value_factory.dest(alu.dest, 0, pin_free),
value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
tmp[0],
tmp[1],
AluInstr::last_write);
@ -2556,7 +2556,7 @@ emit_any_all_fcomp(const nir_alu_instr& alu, EAluOp op, int nc, bool all, Shader
op = (op == op2_sete) ? op2_setne_dx10 : op2_sete_dx10;
ir = new AluInstr(op,
value_factory.dest(alu.dest, 0, pin_free),
value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
max_val,
value_factory.inline_const(ALU_SRC_1, 0),
AluInstr::last_write);
@ -2576,7 +2576,7 @@ emit_any_all_icomp(const nir_alu_instr& alu, EAluOp op, int nc, bool all, Shader
AluInstr *ir = nullptr;
PRegister v[6];
auto dest = value_factory.dest(alu.dest.dest, 0, pin_free);
auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free);
for (int i = 0; i < nc + nc / 2; ++i)
v[i] = value_factory.temp_register();
@ -2628,7 +2628,7 @@ emit_dot(const nir_alu_instr& alu, int n, Shader& shader)
const nir_alu_src& src0 = alu.src[0];
const nir_alu_src& src1 = alu.src[1];
auto dest = value_factory.dest(alu.dest.dest, 0, pin_chan);
auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_chan);
AluInstr::SrcValues srcs(2 * n);
@ -2652,7 +2652,7 @@ emit_dot4(const nir_alu_instr& alu, int nelm, Shader& shader)
const nir_alu_src& src0 = alu.src[0];
const nir_alu_src& src1 = alu.src[1];
auto dest = value_factory.dest(alu.dest.dest, 0, pin_free);
auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free);
AluInstr::SrcValues srcs(8);
@ -2679,7 +2679,7 @@ emit_fdph(const nir_alu_instr& alu, Shader& shader)
const nir_alu_src& src0 = alu.src[0];
const nir_alu_src& src1 = alu.src[1];
auto dest = value_factory.dest(alu.dest.dest, 0, pin_free);
auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free);
AluInstr::SrcValues srcs(8);
@ -2704,7 +2704,7 @@ emit_create_vec(const nir_alu_instr& instr, unsigned nc, Shader& shader)
for (unsigned i = 0; i < nc; ++i) {
auto src = value_factory.src(instr.src[i].src, instr.src[i].swizzle[0]);
auto dst = value_factory.dest(instr.dest.dest, i, pin_none);
auto dst = value_factory.dest(instr.dest.dest.ssa, i, pin_none);
shader.emit_instruction(new AluInstr(op1_mov, dst, src, {alu_write}));
}
@ -2721,7 +2721,7 @@ emit_alu_comb_with_zero(const nir_alu_instr& alu, EAluOp opcode, Shader& shader)
auto pin = pin_for_components(alu);
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.zero(),
value_factory.src(alu.src[0], i),
AluInstr::write);
@ -2740,7 +2740,7 @@ emit_pack_64_2x32_split(const nir_alu_instr& alu, Shader& shader)
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, i, pin_none),
value_factory.dest(alu.dest.dest.ssa, i, pin_none),
value_factory.src(alu.src[i], 0),
AluInstr::write);
shader.emit_instruction(ir);
@ -2756,7 +2756,7 @@ emit_pack_64_2x32(const nir_alu_instr& alu, Shader& shader)
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, i, pin_none),
value_factory.dest(alu.dest.dest.ssa, i, pin_none),
value_factory.src(alu.src[0], i),
AluInstr::write);
shader.emit_instruction(ir);
@ -2772,7 +2772,7 @@ emit_unpack_64_2x32(const nir_alu_instr& alu, Shader& shader)
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, i, pin_none),
value_factory.dest(alu.dest.dest.ssa, i, pin_none),
value_factory.src64(alu.src[0], 0, i),
AluInstr::write);
shader.emit_instruction(ir);
@ -2788,14 +2788,14 @@ emit_alu_vec2_64(const nir_alu_instr& alu, Shader& shader)
AluInstr *ir = nullptr;
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, i, pin_chan),
value_factory.dest(alu.dest.dest.ssa, i, pin_chan),
value_factory.src64(alu.src[0], 0, i),
AluInstr::write);
shader.emit_instruction(ir);
}
for (unsigned i = 0; i < 2; ++i) {
ir = new AluInstr(op1_mov,
value_factory.dest(alu.dest, i + 2, pin_chan),
value_factory.dest(alu.dest.dest.ssa, i + 2, pin_chan),
value_factory.src64(alu.src[1], 1, i),
AluInstr::write);
shader.emit_instruction(ir);
@ -2823,7 +2823,7 @@ emit_pack_32_2x16_split(const nir_alu_instr& alu, Shader& shader)
new AluInstr(op2_lshl_int, yy, y, value_factory.literal(16), AluInstr::last_write));
shader.emit_instruction(new AluInstr(op2_or_int,
value_factory.dest(alu.dest, 0, pin_free),
value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
x,
yy,
AluInstr::last_write));
@ -2835,7 +2835,7 @@ emit_unpack_64_2x32_split(const nir_alu_instr& alu, int comp, Shader& shader)
{
auto& value_factory = shader.value_factory();
shader.emit_instruction(new AluInstr(op1_mov,
value_factory.dest(alu.dest, 0, pin_free),
value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
value_factory.src64(alu.src[0], 0, comp),
AluInstr::last_write));
return true;
@ -2846,7 +2846,7 @@ emit_unpack_32_2x16_split_x(const nir_alu_instr& alu, Shader& shader)
{
auto& value_factory = shader.value_factory();
shader.emit_instruction(new AluInstr(op1_flt16_to_flt32,
value_factory.dest(alu.dest, 0, pin_free),
value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
value_factory.src(alu.src[0], 0),
AluInstr::last_write));
return true;
@ -2863,7 +2863,7 @@ emit_unpack_32_2x16_split_y(const nir_alu_instr& alu, Shader& shader)
AluInstr::last_write));
shader.emit_instruction(new AluInstr(op1_flt16_to_flt32,
value_factory.dest(alu.dest, 0, pin_free),
value_factory.dest(alu.dest.dest.ssa, 0, pin_free),
tmp,
AluInstr::last_write));
return true;
@ -2880,7 +2880,7 @@ emit_alu_trans_op1_eg(const nir_alu_instr& alu, EAluOp opcode, Shader& shader)
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(src0, i),
AluInstr::last_write);
ir->set_alu_flag(alu_is_trans);
@ -2912,7 +2912,7 @@ emit_alu_f2i32_or_u32_eg(const nir_alu_instr& alu, EAluOp opcode, Shader& shader
auto pin = pin_for_components(alu);
for (int i = 0; i < num_comp; ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
reg[i],
AluInstr::write);
if (opcode == op1_flt_to_uint) {
@ -2939,7 +2939,7 @@ emit_alu_trans_op1_cayman(const nir_alu_instr& alu, EAluOp opcode, Shader& shade
unsigned ncomp = j == 3 ? 4 : 3;
AluInstr::SrcValues srcs(ncomp);
PRegister dest = value_factory.dest(alu.dest.dest, j, pin, (1 << ncomp) - 1);
PRegister dest = value_factory.dest(alu.dest.dest.ssa, j, pin, (1 << ncomp) - 1);
for (unsigned i = 0; i < ncomp; ++i)
srcs[i] = value_factory.src(src0, j);
@ -2963,7 +2963,7 @@ emit_alu_trans_op2_eg(const nir_alu_instr& alu, EAluOp opcode, Shader& shader)
auto pin = pin_for_components(alu);
for (unsigned i = 0; i < nir_dest_num_components(alu.dest.dest); ++i) {
ir = new AluInstr(opcode,
value_factory.dest(alu.dest.dest, i, pin),
value_factory.dest(alu.dest.dest.ssa, i, pin),
value_factory.src(src0, i),
value_factory.src(src1, i),
AluInstr::last_write);
@ -2987,7 +2987,7 @@ emit_alu_trans_op2_cayman(const nir_alu_instr& alu, EAluOp opcode, Shader& shade
for (unsigned k = 0; k < nir_dest_num_components(alu.dest.dest); ++k) {
AluInstr::SrcValues srcs(2 * last_slot);
PRegister dest = value_factory.dest(alu.dest.dest, k, pin_free);
PRegister dest = value_factory.dest(alu.dest.dest.ssa, k, pin_free);
for (unsigned i = 0; i < last_slot; ++i) {
srcs[2 * i] = value_factory.src(src0, k);
@ -3025,7 +3025,7 @@ emit_tex_fdd(const nir_alu_instr& alu, TexInstr::Opcode opcode, bool fine, Shade
if (mv)
mv->set_alu_flag(alu_last_instr);
auto dst = value_factory.dest_vec4(alu.dest.dest, pin_group);
auto dst = value_factory.dest_vec4(alu.dest.dest.ssa, pin_group);
RegisterVec4::Swizzle dst_swz = {7, 7, 7, 7};
for (auto i = 0; i < ncomp; ++i) {
dst_swz[i] = i;
@ -3055,7 +3055,7 @@ emit_alu_cube(const nir_alu_instr& alu, Shader& shader)
for (int i = 0; i < 4; ++i) {
ir = new AluInstr(op2_cube,
value_factory.dest(alu.dest.dest, i, pin_chan),
value_factory.dest(alu.dest.dest.ssa, i, pin_chan),
value_factory.src(alu.src[0], src0_chan[i]),
value_factory.src(alu.src[0], src1_chan[i]),
AluInstr::write);

26
src/gallium/drivers/r600/sfn/sfn_instr_mem.cpp
View file

@ -205,7 +205,7 @@ GDSInstr::emit_atomic_op2(nir_intrinsic_instr *instr, Shader& shader)
}
offset += nir_intrinsic_base(instr);
auto dest = read_result ? vf.dest(instr->dest, 0, pin_free) : nullptr;
auto dest = read_result ? vf.dest(instr->dest.ssa, 0, pin_free) : nullptr;
PRegister src_as_register = nullptr;
auto src_val = vf.src(instr->src[1], 0);
@ -226,7 +226,7 @@ GDSInstr::emit_atomic_op2(nir_intrinsic_instr *instr, Shader& shader)
ir = new GDSInstr(op, dest, src, offset, uav_id);
} else {
auto dest = vf.dest(instr->dest, 0, pin_free);
auto dest = vf.dest(instr->dest.ssa, 0, pin_free);
auto tmp = vf.temp_vec4(pin_group, {0, 1, 7, 7});
if (uav_id)
shader.emit_instruction(new AluInstr(op3_muladd_uint24,
@ -256,7 +256,7 @@ GDSInstr::emit_atomic_read(nir_intrinsic_instr *instr, Shader& shader)
}
offset += shader.remap_atomic_base(nir_intrinsic_base(instr));
auto dest = vf.dest(instr->dest, 0, pin_free);
auto dest = vf.dest(instr->dest.ssa, 0, pin_free);
GDSInstr *ir = nullptr;
@ -295,7 +295,7 @@ GDSInstr::emit_atomic_inc(nir_intrinsic_instr *instr, Shader& shader)
offset += shader.remap_atomic_base(nir_intrinsic_base(instr));
GDSInstr *ir = nullptr;
auto dest = read_result ? vf.dest(instr->dest, 0, pin_free) : nullptr;
auto dest = read_result ? vf.dest(instr->dest.ssa, 0, pin_free) : nullptr;
if (shader.chip_class() < ISA_CC_CAYMAN) {
RegisterVec4 src(nullptr, shader.atomic_update(), nullptr, nullptr, pin_chan);
@ -366,7 +366,7 @@ GDSInstr::emit_atomic_pre_dec(nir_intrinsic_instr *instr, Shader& shader)
shader.emit_instruction(ir);
if (read_result)
shader.emit_instruction(new AluInstr(op2_sub_int,
vf.dest(instr->dest, 0, pin_free),
vf.dest(instr->dest.ssa, 0, pin_free),
tmp_dest,
vf.one_i(),
AluInstr::last_write));
@ -534,7 +534,7 @@ bool
RatInstr::emit_ssbo_load(nir_intrinsic_instr *intr, Shader& shader)
{
auto& vf = shader.value_factory();
auto dest = vf.dest_vec4(intr->dest, pin_group);
auto dest = vf.dest_vec4(intr->dest.ssa, pin_group);
/** src0 not used, should be some offset */
auto addr = vf.src(intr->src[1], 0);
@ -707,7 +707,7 @@ RatInstr::emit_ssbo_atomic_op(nir_intrinsic_instr *intr, Shader& shader)
atomic->set_ack();
if (read_result) {
atomic->set_instr_flag(ack_rat_return_write);
auto dest = vf.dest_vec4(intr->dest, pin_group);
auto dest = vf.dest_vec4(intr->dest.ssa, pin_group);
auto fetch = new FetchInstr(vc_fetch,
dest,
@ -737,7 +737,7 @@ bool
RatInstr::emit_ssbo_size(nir_intrinsic_instr *intr, Shader& shader)
{
auto& vf = shader.value_factory();
auto dest = vf.dest_vec4(intr->dest, pin_group);
auto dest = vf.dest_vec4(intr->dest.ssa, pin_group);
auto const_offset = nir_src_as_const_value(intr->src[0]);
int res_id = R600_IMAGE_REAL_RESOURCE_OFFSET;
@ -847,7 +847,7 @@ RatInstr::emit_image_load_or_atomic(nir_intrinsic_instr *intrin, Shader& shader)
atomic->set_ack();
if (read_result) {
atomic->set_instr_flag(ack_rat_return_write);
auto dest = vf.dest_vec4(intrin->dest, pin_group);
auto dest = vf.dest_vec4(intrin->dest.ssa, pin_group);
pipe_format format = nir_intrinsic_format(intrin);
unsigned fmt = fmt_32;
@ -903,7 +903,7 @@ RatInstr::emit_image_size(nir_intrinsic_instr *intrin, Shader& shader)
dyn_offset = shader.emit_load_to_register(vf.src(intrin->src[0], 0));
if (nir_intrinsic_image_dim(intrin) == GLSL_SAMPLER_DIM_BUF) {
auto dest = vf.dest_vec4(intrin->dest, pin_group);
auto dest = vf.dest_vec4(intrin->dest.ssa, pin_group);
shader.emit_instruction(new QueryBufferSizeInstr(dest, {0, 1, 2, 3}, res_id));
return true;
} else {
@ -913,7 +913,7 @@ RatInstr::emit_image_size(nir_intrinsic_instr *intrin, Shader& shader)
nir_dest_num_components(intrin->dest) > 2) {
/* Need to load the layers from a const buffer */
auto dest = vf.dest_vec4(intrin->dest, pin_group);
auto dest = vf.dest_vec4(intrin->dest.ssa, pin_group);
shader.emit_instruction(new TexInstr(TexInstr::get_resinfo,
dest,
{0, 1, 7, 3},
@ -977,7 +977,7 @@ RatInstr::emit_image_size(nir_intrinsic_instr *intrin, Shader& shader)
op3_cnde_int, dest[2], low_bit, comp1, comp2, AluInstr::last_write));
}
} else {
auto dest = vf.dest_vec4(intrin->dest, pin_group);
auto dest = vf.dest_vec4(intrin->dest.ssa, pin_group);
shader.emit_instruction(new TexInstr(TexInstr::get_resinfo,
dest,
{0, 1, 2, 3},
@ -998,7 +998,7 @@ RatInstr::emit_image_samples(nir_intrinsic_instr *intrin, Shader& shader)
auto src = RegisterVec4(0, true, {4, 4, 4, 4});
auto tmp = shader.value_factory().temp_vec4(pin_group);
auto dest = shader.value_factory().dest(intrin->dest, 0, pin_free);
auto dest = shader.value_factory().dest(intrin->dest.ssa, 0, pin_free);
auto const_offset = nir_src_as_const_value(intrin->src[0]);
PRegister dyn_offset = nullptr;

10
src/gallium/drivers/r600/sfn/sfn_instr_tex.cpp
View file

@ -535,7 +535,7 @@ TexInstr::emit_lowered_tex(nir_tex_instr *tex, Inputs& src, Shader& shader)
int32_t inst_mode = params[2].i32;
uint32_t dst_swz_packed = params[3].u32;
auto dst = vf.dest_vec4(tex->dest, pin_group);
auto dst = vf.dest_vec4(tex->dest.ssa, pin_group);
RegisterVec4::Swizzle src_swizzle = {0};
for (int i = 0; i < 4; ++i)
@ -580,7 +580,7 @@ bool
TexInstr::emit_buf_txf(nir_tex_instr *tex, Inputs& src, Shader& shader)
{
auto& vf = shader.value_factory();
auto dst = vf.dest_vec4(tex->dest, pin_group);
auto dst = vf.dest_vec4(tex->dest.ssa, pin_group);
PRegister tex_offset = nullptr;
if (src.resource_offset)
@ -633,7 +633,7 @@ TexInstr::emit_buf_txf(nir_tex_instr *tex, Inputs& src, Shader& shader)
bool
TexInstr::emit_tex_texture_samples(nir_tex_instr *instr, Inputs& src, Shader& shader)
{
RegisterVec4 dest = shader.value_factory().dest_vec4(instr->dest, pin_chan);
RegisterVec4 dest = shader.value_factory().dest_vec4(instr->dest.ssa, pin_chan);
RegisterVec4 help{
0, true, {4, 4, 4, 4}
};
@ -655,7 +655,7 @@ TexInstr::emit_tex_txs(nir_tex_instr *tex,
{
auto& vf = shader.value_factory();
auto dest = vf.dest_vec4(tex->dest, pin_group);
auto dest = vf.dest_vec4(tex->dest.ssa, pin_group);
if (tex->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
if (shader.chip_class() >= ISA_CC_EVERGREEN) {
@ -885,7 +885,7 @@ TexInstr::emit_tex_lod(nir_tex_instr *tex, Inputs& src, Shader& shader)
auto sampler = get_sampler_id(tex->sampler_index, src.sampler_deref);
assert(!sampler.indirect && "Indirect sampler selection not yet supported");
auto dst = shader.value_factory().dest_vec4(tex->dest, pin_group);
auto dst = shader.value_factory().dest_vec4(tex->dest.ssa, pin_group);
auto swizzle = src.swizzle_from_ncomps(tex->coord_components);

30
src/gallium/drivers/r600/sfn/sfn_shader.cpp
View file

@ -1058,7 +1058,7 @@ void RegisterReadHandler::visit(LocalArray& array)
for (int i = 0; i < ir->dest.ssa.num_components; ++i) {
for (int s = 0; s < slots; ++s) {
int chan = i * slots + s;
auto dest = sh.value_factory().dest(ir->dest, chan, pin);
auto dest = sh.value_factory().dest(ir->dest.ssa, chan, pin);
auto src = array.element(nir_intrinsic_base(ir), addr, chan);
sh.emit_instruction(new AluInstr(op1_mov, dest, src, AluInstr::write));
}
@ -1067,7 +1067,7 @@ void RegisterReadHandler::visit(LocalArray& array)
void RegisterReadHandler::visit(Register& reg)
{
auto dest = sh.value_factory().dest(ir->dest, 0, pin_free);
auto dest = sh.value_factory().dest(ir->dest.ssa, 0, pin_free);
sh.emit_instruction(new AluInstr(op1_mov, dest, &reg, AluInstr::write));
}
@ -1104,7 +1104,7 @@ Shader::emit_atomic_local_shared(nir_intrinsic_instr *instr)
auto& vf = value_factory();
auto dest_value = uses_retval ? vf.dest(instr->dest, 0, pin_free) : nullptr;
auto dest_value = uses_retval ? vf.dest(instr->dest.ssa, 0, pin_free) : nullptr;
auto op = lds_op_from_intrinsic(nir_intrinsic_atomic_op(instr), uses_retval);
@ -1113,7 +1113,7 @@ Shader::emit_atomic_local_shared(nir_intrinsic_instr *instr)
* value from read queue. */
if (!uses_retval &&
(op == LDS_XCHG_RET || op == LDS_CMP_XCHG_RET)) {
dest_value = vf.dest(instr->dest, 0, pin_free);
dest_value = vf.dest(instr->dest.ssa, 0, pin_free);
}
auto address = vf.src(instr->src[0], 0);
@ -1217,7 +1217,7 @@ bool
Shader::emit_load_scratch(nir_intrinsic_instr *intr)
{
auto addr = value_factory().src(intr->src[0], 0);
auto dest = value_factory().dest_vec4(intr->dest, pin_group);
auto dest = value_factory().dest_vec4(intr->dest.ssa, pin_group);
if (chip_class() >= ISA_CC_R700) {
RegisterVec4::Swizzle dest_swz = {7, 7, 7, 7};
@ -1265,7 +1265,7 @@ Shader::emit_load_scratch(nir_intrinsic_instr *intr)
bool Shader::emit_load_global(nir_intrinsic_instr *intr)
{
auto dest = value_factory().dest_vec4(intr->dest, pin_group);
auto dest = value_factory().dest_vec4(intr->dest.ssa, pin_group);
auto src_value = value_factory().src(intr->src[0], 0);
auto src = src_value->as_register();
@ -1312,7 +1312,7 @@ bool
Shader::emit_local_load(nir_intrinsic_instr *instr)
{
auto address = value_factory().src_vec(instr->src[0], instr->num_components);
auto dest_value = value_factory().dest_vec(instr->dest, instr->num_components);
auto dest_value = value_factory().dest_vec(instr->dest.ssa, instr->num_components);
emit_instruction(new LDSReadInstr(dest_value, address));
return true;
}
@ -1450,7 +1450,7 @@ Shader::emit_load_tcs_param_base(nir_intrinsic_instr *instr, int offset)
emit_instruction(
new AluInstr(op1_mov, src, value_factory().zero(), AluInstr::last_write));
auto dest = value_factory().dest_vec4(instr->dest, pin_group);
auto dest = value_factory().dest_vec4(instr->dest.ssa, pin_group);
auto fetch = new LoadFromBuffer(dest,
{0, 1, 2, 3},
src,
@ -1471,11 +1471,11 @@ Shader::emit_shader_clock(nir_intrinsic_instr *instr)
auto& vf = value_factory();
auto group = new AluGroup();
group->add_instruction(new AluInstr(op1_mov,
vf.dest(instr->dest, 0, pin_chan),
vf.dest(instr->dest.ssa, 0, pin_chan),
vf.inline_const(ALU_SRC_TIME_LO, 0),
AluInstr::write));
group->add_instruction(new AluInstr(op1_mov,
vf.dest(instr->dest, 1, pin_chan),
vf.dest(instr->dest.ssa, 1, pin_chan),
vf.inline_const(ALU_SRC_TIME_HI, 0),
AluInstr::last_write));
emit_instruction(group);
@ -1536,7 +1536,7 @@ Shader::load_ubo(nir_intrinsic_instr *instr)
auto addr = value_factory().src(instr->src[1], 0)->as_register();
RegisterVec4::Swizzle dest_swz{7, 7, 7, 7};
auto dest = value_factory().dest_vec4(instr->dest, pin_group);
auto dest = value_factory().dest_vec4(instr->dest.ssa, pin_group);
for (unsigned i = 0; i < nir_dest_num_components(instr->dest); ++i) {
dest_swz[i] = i + nir_intrinsic_component(instr);
@ -1571,7 +1571,7 @@ Shader::load_ubo(nir_intrinsic_instr *instr)
auto uniform =
value_factory().uniform(512 + buf_offset->u32, i + buf_cmp, bufid->u32);
ir = new AluInstr(op1_mov,
value_factory().dest(instr->dest, i, pin),
value_factory().dest(instr->dest.ssa, i, pin),
uniform,
{alu_write});
emit_instruction(ir);
@ -1588,7 +1588,7 @@ Shader::load_ubo(nir_intrinsic_instr *instr)
int cmp = buf_cmp + i;
auto u =
new UniformValue(512 + buf_offset->u32, cmp, kc_id, nir_intrinsic_base(instr));
auto dest = value_factory().dest(instr->dest, i, pin_none);
auto dest = value_factory().dest(instr->dest.ssa, i, pin_none);
ir = new AluInstr(op1_mov, dest, u, AluInstr::write);
emit_instruction(ir);
}
@ -1608,9 +1608,9 @@ Shader::start_new_block(int depth)
}
bool
Shader::emit_simple_mov(nir_dest& dest, int chan, PVirtualValue src, Pin pin)
Shader::emit_simple_mov(nir_def& def, int chan, PVirtualValue src, Pin pin)
{
auto dst = value_factory().dest(dest, chan, pin);
auto dst = value_factory().dest(def, chan, pin);
emit_instruction(new AluInstr(op1_mov, dst, src, AluInstr::last_write));
return true;
}

2
src/gallium/drivers/r600/sfn/sfn_shader.h
View file

@ -278,7 +278,7 @@ protected:
const ShaderInput& input(int base) const;
bool emit_simple_mov(nir_dest& dest, int chan, PVirtualValue src, Pin pin = pin_free);
bool emit_simple_mov(nir_def& def, int chan, PVirtualValue src, Pin pin = pin_free);
template <typename T>
using IOMap = std::map<int, T, std::less<int>, Allocator<std::pair<const int, T>>>;

4
src/gallium/drivers/r600/sfn/sfn_shader_cs.cpp
View file

@ -102,7 +102,7 @@ ComputeShader::emit_load_from_info_buffer(nir_intrinsic_instr *instr, int offset
AluInstr::last_write));
}
auto dest = value_factory().dest_vec4(instr->dest, pin_group);
auto dest = value_factory().dest_vec4(instr->dest.ssa, pin_group);
auto ir = new LoadFromBuffer(dest,
{0, 1, 2, 7},
@ -126,7 +126,7 @@ ComputeShader::emit_load_3vec(nir_intrinsic_instr *instr,
auto& vf = value_factory();
for (int i = 0; i < 3; ++i) {
auto dest = vf.dest(instr->dest, i, pin_none);
auto dest = vf.dest(instr->dest.ssa, i, pin_none);
emit_instruction(new AluInstr(
op1_mov, dest, src[i], i == 2 ? AluInstr::last_write : AluInstr::write));
}

38
src/gallium/drivers/r600/sfn/sfn_shader_fs.cpp
View file

@ -80,7 +80,7 @@ FragmentShader::load_input(nir_intrinsic_instr *intr)
AluInstr *ir = nullptr;
for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
ir = new AluInstr(op1_mov,
vf.dest(intr->dest, i, pin_none),
vf.dest(intr->dest.ssa, i, pin_none),
m_pos_input[i],
AluInstr::write);
emit_instruction(ir);
@ -91,7 +91,7 @@ FragmentShader::load_input(nir_intrinsic_instr *intr)
if (location == VARYING_SLOT_FACE) {
auto ir = new AluInstr(op2_setgt_dx10,
vf.dest(intr->dest, 0, pin_none),
vf.dest(intr->dest.ssa, 0, pin_none),
m_face_input,
vf.inline_const(ALU_SRC_0, 0),
AluInstr::last_write);
@ -181,9 +181,9 @@ FragmentShader::process_stage_intrinsic(nir_intrinsic_instr *intr)
if (m_apply_sample_mask) {
return emit_load_sample_mask_in(intr);
} else
return emit_simple_mov(intr->dest, 0, m_sample_mask_reg);
return emit_simple_mov(intr->dest.ssa, 0, m_sample_mask_reg);
case nir_intrinsic_load_sample_id:
return emit_simple_mov(intr->dest, 0, m_sample_id_reg);
return emit_simple_mov(intr->dest.ssa, 0, m_sample_id_reg);
case nir_intrinsic_load_helper_invocation:
return emit_load_helper_invocation(intr);
case nir_intrinsic_load_sample_pos:
@ -201,7 +201,7 @@ FragmentShader::load_interpolated_input(nir_intrinsic_instr *intr)
switch (loc) {
case VARYING_SLOT_POS:
for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i)
vf.inject_value(intr->dest, i, m_pos_input[i]);
vf.inject_value(intr->dest.ssa, i, m_pos_input[i]);
return true;
case VARYING_SLOT_FACE:
return false;
@ -301,7 +301,7 @@ bool
FragmentShader::emit_load_sample_mask_in(nir_intrinsic_instr *instr)
{
auto& vf = value_factory();
auto dest = vf.dest(instr->dest, 0, pin_free);
auto dest = vf.dest(instr->dest.ssa, 0, pin_free);
auto tmp = vf.temp_register();
assert(m_sample_id_reg);
assert(m_sample_mask_reg);
@ -332,7 +332,7 @@ FragmentShader::emit_load_helper_invocation(nir_intrinsic_instr *instr)
vtx->set_fetch_flag(FetchInstr::vpm);
vtx->set_fetch_flag(FetchInstr::use_tc);
vtx->set_always_keep();
auto dst = value_factory().dest(instr->dest, 0, pin_free);
auto dst = value_factory().dest(instr->dest.ssa, 0, pin_free);
auto ir = new AluInstr(op1_mov, dst, m_helper_invocation, AluInstr::last_write);
ir->add_required_instr(vtx);
emit_instruction(vtx);
@ -570,7 +570,7 @@ FragmentShader::emit_export_pixel(nir_intrinsic_instr& intr)
bool
FragmentShader::emit_load_sample_pos(nir_intrinsic_instr *instr)
{
auto dest = value_factory().dest_vec4(instr->dest, pin_group);
auto dest = value_factory().dest_vec4(instr->dest.ssa, pin_group);
auto fetch = new LoadFromBuffer(dest,
{0, 1, 2, 3},
@ -689,7 +689,7 @@ FragmentShaderR600::load_input_hw(nir_intrinsic_instr *intr)
<< *m_interpolated_inputs[nir_intrinsic_base(intr)][i] << "\n";
unsigned index = nir_intrinsic_component(intr) + i;
assert(index < 4);
vf.inject_value(intr->dest,
vf.inject_value(intr->dest.ssa,
i,
m_interpolated_inputs[nir_intrinsic_base(intr)][index]);
}
@ -736,11 +736,11 @@ FragmentShaderEG::load_input_hw(nir_intrinsic_instr *intr)
AluInstr::last_write);
emit_instruction(ir);
emit_instruction(new AluInstr(
op1_mov, vf.dest(intr->dest, i, pin_chan), tmp, AluInstr::last_write));
op1_mov, vf.dest(intr->dest.ssa, i, pin_chan), tmp, AluInstr::last_write));
} else {
ir = new AluInstr(op1_interp_load_p0,
vf.dest(intr->dest, i, pin_chan),
vf.dest(intr->dest.ssa, i, pin_chan),
new InlineConstant(ALU_SRC_PARAM_BASE + io.lds_pos(), i),
AluInstr::write);
emit_instruction(ir);
@ -786,8 +786,8 @@ FragmentShaderEG::process_stage_intrinsic_hw(nir_intrinsic_instr *intr)
case nir_intrinsic_load_barycentric_pixel:
case nir_intrinsic_load_barycentric_sample: {
unsigned ij = barycentric_ij_index(intr);
vf.inject_value(intr->dest, 0, m_interpolator[ij].i);
vf.inject_value(intr->dest, 1, m_interpolator[ij].j);
vf.inject_value(intr->dest.ssa, 0, m_interpolator[ij].i);
vf.inject_value(intr->dest.ssa, 1, m_interpolator[ij].j);
return true;
}
case nir_intrinsic_load_barycentric_at_offset:
@ -810,7 +810,7 @@ FragmentShaderEG::load_interpolated_input_hw(nir_intrinsic_instr *intr)
int start_comp = nir_intrinsic_component(intr);
bool need_temp = start_comp > 0;
auto dst = need_temp ? vf.temp_vec4(pin_chan) : vf.dest_vec4(intr->dest, pin_chan);
auto dst = need_temp ? vf.temp_vec4(pin_chan) : vf.dest_vec4(intr->dest.ssa, pin_chan);
InterpolateParams params;
@ -824,7 +824,7 @@ FragmentShaderEG::load_interpolated_input_hw(nir_intrinsic_instr *intr)
if (need_temp) {
AluInstr *ir = nullptr;
for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
auto real_dst = vf.dest(intr->dest, i, pin_chan);
auto real_dst = vf.dest(intr->dest.ssa, i, pin_chan);
ir = new AluInstr(op1_mov, real_dst, dst[i + start_comp], AluInstr::write);
emit_instruction(ir);
}
@ -936,13 +936,13 @@ FragmentShaderEG::load_barycentric_at_sample(nir_intrinsic_instr *instr)
op3_muladd, tmp1, grad[1], slope[2], interpolator.i, {alu_write, alu_last_instr}));
emit_instruction(new AluInstr(op3_muladd,
vf.dest(instr->dest, 0, pin_none),
vf.dest(instr->dest.ssa, 0, pin_none),
grad[3],
slope[3],
tmp1,
{alu_write}));
emit_instruction(new AluInstr(op3_muladd,
vf.dest(instr->dest, 1, pin_none),
vf.dest(instr->dest.ssa, 1, pin_none),
grad[2],
slope[3],
tmp0,
@ -987,9 +987,9 @@ FragmentShaderEG::load_barycentric_at_offset(nir_intrinsic_instr *instr)
emit_instruction(new AluInstr(
op3_muladd, tmp1, help[1], ofs_x, interpolator.i, {alu_write, alu_last_instr}));
emit_instruction(new AluInstr(
op3_muladd, vf.dest(instr->dest, 0, pin_none), help[3], ofs_y, tmp1, {alu_write}));
op3_muladd, vf.dest(instr->dest.ssa, 0, pin_none), help[3], ofs_y, tmp1, {alu_write}));
emit_instruction(new AluInstr(op3_muladd,
vf.dest(instr->dest, 1, pin_none),
vf.dest(instr->dest.ssa, 1, pin_none),
help[2],
ofs_y,
tmp0,

6
src/gallium/drivers/r600/sfn/sfn_shader_gs.cpp
View file

@ -185,9 +185,9 @@ GeometryShader::process_stage_intrinsic(nir_intrinsic_instr *intr)
case nir_intrinsic_end_primitive:
return emit_vertex(intr, true);
case nir_intrinsic_load_primitive_id:
return emit_simple_mov(intr->dest, 0, m_primitive_id);
return emit_simple_mov(intr->dest.ssa, 0, m_primitive_id);
case nir_intrinsic_load_invocation_id:
return emit_simple_mov(intr->dest, 0, m_invocation_id);
return emit_simple_mov(intr->dest.ssa, 0, m_invocation_id);
case nir_intrinsic_load_per_vertex_input:
return emit_load_per_vertex_input(intr);
default:;
@ -320,7 +320,7 @@ GeometryShader::store_output(nir_intrinsic_instr *instr)
bool
GeometryShader::emit_load_per_vertex_input(nir_intrinsic_instr *instr)
{
auto dest = value_factory().dest_vec4(instr->dest, pin_group);
auto dest = value_factory().dest_vec4(instr->dest.ssa, pin_group);
RegisterVec4::Swizzle dest_swz{7, 7, 7, 7};
for (unsigned i = 0; i < nir_dest_num_components(instr->dest); ++i) {

16
src/gallium/drivers/r600/sfn/sfn_shader_tess.cpp
View file

@ -97,13 +97,13 @@ TCSShader::process_stage_intrinsic(nir_intrinsic_instr *instr)
{
switch (instr->intrinsic) {
case nir_intrinsic_load_tcs_rel_patch_id_r600:
return emit_simple_mov(instr->dest, 0, m_rel_patch_id);
return emit_simple_mov(instr->dest.ssa, 0, m_rel_patch_id);
case nir_intrinsic_load_invocation_id:
return emit_simple_mov(instr->dest, 0, m_invocation_id);
return emit_simple_mov(instr->dest.ssa, 0, m_invocation_id);
case nir_intrinsic_load_primitive_id:
return emit_simple_mov(instr->dest, 0, m_primitive_id);
return emit_simple_mov(instr->dest.ssa, 0, m_primitive_id);
case nir_intrinsic_load_tcs_tess_factor_base_r600:
return emit_simple_mov(instr->dest, 0, m_tess_factor_base);
return emit_simple_mov(instr->dest.ssa, 0, m_tess_factor_base);
case nir_intrinsic_store_tf_r600:
return store_tess_factor(instr);
default:
@ -246,12 +246,12 @@ TESShader::process_stage_intrinsic(nir_intrinsic_instr *intr)
{
switch (intr->intrinsic) {
case nir_intrinsic_load_tess_coord_xy:
return emit_simple_mov(intr->dest, 0, m_tess_coord[0], pin_none) &&
emit_simple_mov(intr->dest, 1, m_tess_coord[1], pin_none);
return emit_simple_mov(intr->dest.ssa, 0, m_tess_coord[0], pin_none) &&
emit_simple_mov(intr->dest.ssa, 1, m_tess_coord[1], pin_none);
case nir_intrinsic_load_primitive_id:
return emit_simple_mov(intr->dest, 0, m_primitive_id);
return emit_simple_mov(intr->dest.ssa, 0, m_primitive_id);
case nir_intrinsic_load_tcs_rel_patch_id_r600:
return emit_simple_mov(intr->dest, 0, m_rel_patch_id);
return emit_simple_mov(intr->dest.ssa, 0, m_rel_patch_id);
case nir_intrinsic_store_output:
return m_export_processor->store_output(*intr);
default:

10
src/gallium/drivers/r600/sfn/sfn_shader_vs.cpp
View file

@ -505,7 +505,7 @@ VertexShader::load_input(nir_intrinsic_instr *intr)
for (unsigned i = 0; i < nir_dest_num_components(intr->dest); ++i) {
auto src = vf.allocate_pinned_register(driver_location + 1, i);
src->set_flag(Register::ssa);
vf.inject_value(intr->dest, i, src);
vf.inject_value(intr->dest.ssa, i, src);
}
if (ir)
ir->set_alu_flag(alu_last_instr);
@ -553,13 +553,13 @@ VertexShader::process_stage_intrinsic(nir_intrinsic_instr *intr)
{
switch (intr->intrinsic) {
case nir_intrinsic_load_vertex_id:
return emit_simple_mov(intr->dest, 0, m_vertex_id);
return emit_simple_mov(intr->dest.ssa, 0, m_vertex_id);
case nir_intrinsic_load_instance_id:
return emit_simple_mov(intr->dest, 0, m_instance_id);
return emit_simple_mov(intr->dest.ssa, 0, m_instance_id);
case nir_intrinsic_load_primitive_id:
return emit_simple_mov(intr->dest, 0, primitive_id());
return emit_simple_mov(intr->dest.ssa, 0, primitive_id());
case nir_intrinsic_load_tcs_rel_patch_id_r600:
return emit_simple_mov(intr->dest, 0, m_rel_vertex_id);
return emit_simple_mov(intr->dest.ssa, 0, m_rel_vertex_id);
default:
return false;
}

31
src/gallium/drivers/r600/sfn/sfn_valuefactory.cpp
View file

@ -168,21 +168,14 @@ ValueFactory::allocate_pinned_vec4(int sel, bool is_ssa)
}
void
ValueFactory::inject_value(const nir_dest& dest, int chan, PVirtualValue value)
ValueFactory::inject_value(const nir_def& def, int chan, PVirtualValue value)
{
RegisterKey key(dest.ssa.index, chan, vp_ssa);
RegisterKey key(def.index, chan, vp_ssa);
sfn_log << SfnLog::reg << "Inject value with key " << key << "\n";
assert(m_values.find(key) == m_values.end());
m_values[key] = value;
}
PRegister
ValueFactory::dest(const nir_alu_dest& dst, int chan, Pin pin_channel, uint8_t chan_mask)
{
sfn_log << SfnLog::reg << "Search (ref) " << &dst << "\n";
return dest(dst.dest, chan, pin_channel, chan_mask);
}
class TranslateRegister : public RegisterVisitor {
public:
void visit(VirtualValue& value) { (void)value; }
@ -207,12 +200,6 @@ public:
int m_chan;
};
PRegister
ValueFactory::dest(const nir_dest& dst, int chan, Pin pin_channel, uint8_t chan_mask)
{
return dest(dst.ssa, chan, pin_channel, chan_mask);
}
void
ValueFactory::allocate_const(nir_load_const_instr *load_const)
{
@ -277,14 +264,14 @@ ValueFactory::temp_vec4(Pin pin, const RegisterVec4::Swizzle& swizzle)
}
RegisterVec4
ValueFactory::dest_vec4(const nir_dest& dst, Pin pin)
ValueFactory::dest_vec4(const nir_def& def, Pin pin)
{
if (pin != pin_group && pin != pin_chgr)
pin = pin_chan;
PRegister x = dest(dst, 0, pin);
PRegister y = dest(dst, 1, pin);
PRegister z = dest(dst, 2, pin);
PRegister w = dest(dst, 3, pin);
PRegister x = dest(def, 0, pin);
PRegister y = dest(def, 1, pin);
PRegister z = dest(def, 2, pin);
PRegister w = dest(def, 3, pin);
return RegisterVec4(x, y, z, w, pin);
}
@ -475,12 +462,12 @@ ValueFactory::src_vec(const nir_src& source, int components)
}
std::vector<PRegister, Allocator<PRegister>>
ValueFactory::dest_vec(const nir_dest& dst, int num_components)
ValueFactory::dest_vec(const nir_def& def, int num_components)
{
std::vector<PRegister, Allocator<PRegister>> retval;
retval.reserve(num_components);
for (int i = 0; i < num_components; ++i)
retval.push_back(dest(dst, i, num_components > 1 ? pin_none : pin_free));
retval.push_back(dest(def, i, num_components > 1 ? pin_none : pin_free));
return retval;
}

14
src/gallium/drivers/r600/sfn/sfn_valuefactory.h
View file

@ -232,21 +232,15 @@ public:
/* Inject a predefined value for a given dest value
* (usually the result of a sysvalue load) */
void inject_value(const nir_dest& dest, int chan, PVirtualValue value);
void inject_value(const nir_def& def, int chan, PVirtualValue value);
/* Get or create a destination value of vector of values */
PRegister
dest(const nir_alu_dest& dest, int chan, Pin pin_channel, uint8_t chan_mask = 0xf);
dest(const nir_def& def, int chan, Pin pin_channel, uint8_t chan_mask = 0xf);
PRegister
dest(const nir_dest& dest, int chan, Pin pin_channel, uint8_t chan_mask = 0xf);
RegisterVec4 dest_vec4(const nir_def& dest, Pin pin);
PRegister
dest(const nir_def& dest, int chan, Pin pin_channel, uint8_t chan_mask = 0xf);
RegisterVec4 dest_vec4(const nir_dest& dest, Pin pin);
std::vector<PRegister, Allocator<PRegister>> dest_vec(const nir_dest& dest,
std::vector<PRegister, Allocator<PRegister>> dest_vec(const nir_def& dest,
int num_components);
PRegister dummy_dest(unsigned chan);

6
src/gallium/drivers/r600/sfn/tests/sfn_valuefactory_test.cpp
View file

@ -56,7 +56,7 @@ TEST_F(ValuefactoryTest, test_create_ssa)
auto alu = nir_instr_as_alu(sum->parent_instr);
sfn_log << SfnLog::reg << "Search (test) " << &alu->dest << "\n";
auto dest_value = factory->dest(alu->dest, 0, pin_none);
auto dest_value = factory->dest(alu->dest.dest.ssa, 0, pin_none);
EXPECT_EQ(dest_value->sel(), 1024);
EXPECT_EQ(dest_value->chan(), 0);
EXPECT_EQ(dest_value->pin(), pin_none);
@ -76,7 +76,7 @@ TEST_F(ValuefactoryTest, test_create_ssa_pinned_chan)
auto sum = nir_fadd(&b, c1, c2);
auto alu = nir_instr_as_alu(sum->parent_instr);
auto dest_value = factory->dest(alu->dest, 0, pin_chan);
auto dest_value = factory->dest(alu->dest.dest.ssa, 0, pin_chan);
EXPECT_EQ(dest_value->sel(), 1024);
EXPECT_EQ(dest_value->chan(), 0);
EXPECT_EQ(dest_value->pin(), pin_chan);
@ -94,7 +94,7 @@ TEST_F(ValuefactoryTest, test_create_ssa_pinned_chan_and_reg)
auto sum = nir_fadd(&b, c1, c2);
auto alu = nir_instr_as_alu(sum->parent_instr);
auto dest_value = factory->dest(alu->dest, 1, pin_chan);
auto dest_value = factory->dest(alu->dest.dest.ssa, 1, pin_chan);
EXPECT_EQ(dest_value->sel(), 1024);
EXPECT_EQ(dest_value->chan(), 1);
EXPECT_EQ(dest_value->pin(), pin_chan);