From dcf29202d48ff017e22d6b85e63be908cb6c92fe Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Fri, 19 Jan 2024 11:54:46 -0800 Subject: [PATCH] intel/elk: Remove a bunch of files that don't apply for Gfx8- Reviewed-by: Ian Romanick Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/elk/brw_fs.cpp | 4 - src/intel/compiler/elk/brw_fs_scoreboard.cpp | 1365 ------- src/intel/compiler/elk/brw_kernel.c | 790 ---- src/intel/compiler/elk/brw_kernel.h | 78 - src/intel/compiler/elk/brw_mesh.cpp | 1606 -------- src/intel/compiler/elk/brw_nir.c | 10 - .../elk/brw_nir_lower_cooperative_matrix.c | 818 ---- .../elk/brw_nir_lower_intersection_shader.c | 273 -- .../compiler/elk/brw_nir_lower_ray_queries.c | 567 --- .../elk/brw_nir_lower_rt_intrinsics.c | 386 -- .../compiler/elk/brw_nir_lower_shader_calls.c | 329 -- src/intel/compiler/elk/brw_nir_rt.c | 536 --- src/intel/compiler/elk/brw_nir_rt.h | 76 - src/intel/compiler/elk/brw_nir_rt_builder.h | 990 ----- src/intel/compiler/elk/brw_rt.h | 292 -- src/intel/compiler/elk/intel_clc.c | 676 --- src/intel/compiler/elk/meson.build | 16 - src/intel/compiler/elk/test_fs_scoreboard.cpp | 893 ---- src/intel/compiler/elk/tests/gen11/cr0.asm | 7 - .../compiler/elk/tests/gen11/cr0.expected | 7 - src/intel/compiler/elk/tests/gen11/rol.asm | 1 - .../compiler/elk/tests/gen11/rol.expected | 1 - src/intel/compiler/elk/tests/gen11/ror.asm | 1 - .../compiler/elk/tests/gen11/ror.expected | 1 - src/intel/compiler/elk/tests/gen12.5/add3.asm | 7 - .../compiler/elk/tests/gen12.5/add3.expected | 7 - src/intel/compiler/elk/tests/gen12.5/send.asm | 30 - .../compiler/elk/tests/gen12.5/send.expected | 15 - src/intel/compiler/elk/tests/gen12.5/swsb.asm | 23 - .../compiler/elk/tests/gen12.5/swsb.expected | 21 - src/intel/compiler/elk/tests/gen12/dp4a.asm | 33 - .../compiler/elk/tests/gen12/dp4a.expected | 33 - src/intel/compiler/elk/tests/gen12/send.asm | 43 - .../compiler/elk/tests/gen12/send.expected | 21 - src/intel/compiler/elk/tests/gen12/swsb.asm | 40 - .../compiler/elk/tests/gen12/swsb.expected | 38 - src/intel/compiler/elk/tests/gen12/sync.asm | 33 - .../compiler/elk/tests/gen12/sync.expected | 33 - src/intel/compiler/elk/tests/gen9/add.asm | 40 - .../compiler/elk/tests/gen9/add.expected | 40 - src/intel/compiler/elk/tests/gen9/and.asm | 29 - .../compiler/elk/tests/gen9/and.expected | 29 - src/intel/compiler/elk/tests/gen9/asr.asm | 6 - .../compiler/elk/tests/gen9/asr.expected | 6 - src/intel/compiler/elk/tests/gen9/bfe.asm | 4 - .../compiler/elk/tests/gen9/bfe.expected | 4 - src/intel/compiler/elk/tests/gen9/bfi1.asm | 2 - .../compiler/elk/tests/gen9/bfi1.expected | 2 - src/intel/compiler/elk/tests/gen9/bfi2.asm | 2 - .../compiler/elk/tests/gen9/bfi2.expected | 2 - src/intel/compiler/elk/tests/gen9/bfrev.asm | 2 - .../compiler/elk/tests/gen9/bfrev.expected | 2 - src/intel/compiler/elk/tests/gen9/break.asm | 6 - .../compiler/elk/tests/gen9/break.expected | 4 - src/intel/compiler/elk/tests/gen9/cbit.asm | 2 - .../compiler/elk/tests/gen9/cbit.expected | 2 - src/intel/compiler/elk/tests/gen9/cmp.asm | 104 - .../compiler/elk/tests/gen9/cmp.expected | 104 - src/intel/compiler/elk/tests/gen9/cont.asm | 4 - .../compiler/elk/tests/gen9/cont.expected | 2 - src/intel/compiler/elk/tests/gen9/cr0.asm | 14 - .../compiler/elk/tests/gen9/cr0.expected | 14 - src/intel/compiler/elk/tests/gen9/csel.asm | 13 - .../compiler/elk/tests/gen9/csel.expected | 13 - src/intel/compiler/elk/tests/gen9/else.asm | 4 - .../compiler/elk/tests/gen9/else.expected | 3 - src/intel/compiler/elk/tests/gen9/endif.asm | 4 - .../compiler/elk/tests/gen9/endif.expected | 3 - src/intel/compiler/elk/tests/gen9/fbh.asm | 2 - .../compiler/elk/tests/gen9/fbh.expected | 2 - src/intel/compiler/elk/tests/gen9/fbl.asm | 3 - .../compiler/elk/tests/gen9/fbl.expected | 3 - src/intel/compiler/elk/tests/gen9/frc.asm | 2 - .../compiler/elk/tests/gen9/frc.expected | 2 - src/intel/compiler/elk/tests/gen9/halt.asm | 6 - .../compiler/elk/tests/gen9/halt.expected | 4 - src/intel/compiler/elk/tests/gen9/if.asm | 7 - src/intel/compiler/elk/tests/gen9/if.expected | 5 - src/intel/compiler/elk/tests/gen9/lrp.asm | 5 - .../compiler/elk/tests/gen9/lrp.expected | 5 - src/intel/compiler/elk/tests/gen9/lzd.asm | 2 - .../compiler/elk/tests/gen9/lzd.expected | 2 - src/intel/compiler/elk/tests/gen9/mach.asm | 4 - .../compiler/elk/tests/gen9/mach.expected | 4 - src/intel/compiler/elk/tests/gen9/mad.asm | 43 - .../compiler/elk/tests/gen9/mad.expected | 43 - src/intel/compiler/elk/tests/gen9/math.asm | 31 - .../compiler/elk/tests/gen9/math.expected | 31 - src/intel/compiler/elk/tests/gen9/mov.asm | 139 - .../compiler/elk/tests/gen9/mov.expected | 139 - src/intel/compiler/elk/tests/gen9/mul.asm | 31 - .../compiler/elk/tests/gen9/mul.expected | 31 - src/intel/compiler/elk/tests/gen9/nop.asm | 1 - .../compiler/elk/tests/gen9/nop.expected | 1 - src/intel/compiler/elk/tests/gen9/not.asm | 2 - .../compiler/elk/tests/gen9/not.expected | 2 - src/intel/compiler/elk/tests/gen9/or.asm | 23 - src/intel/compiler/elk/tests/gen9/or.expected | 23 - src/intel/compiler/elk/tests/gen9/pln.asm | 10 - .../compiler/elk/tests/gen9/pln.expected | 10 - src/intel/compiler/elk/tests/gen9/rndd.asm | 5 - .../compiler/elk/tests/gen9/rndd.expected | 5 - src/intel/compiler/elk/tests/gen9/rnde.asm | 2 - .../compiler/elk/tests/gen9/rnde.expected | 2 - src/intel/compiler/elk/tests/gen9/rndz.asm | 2 - .../compiler/elk/tests/gen9/rndz.expected | 2 - src/intel/compiler/elk/tests/gen9/sel.asm | 33 - .../compiler/elk/tests/gen9/sel.expected | 33 - src/intel/compiler/elk/tests/gen9/send.asm | 3606 ----------------- .../compiler/elk/tests/gen9/send.expected | 1803 --------- src/intel/compiler/elk/tests/gen9/sendc.asm | 264 -- .../compiler/elk/tests/gen9/sendc.expected | 132 - src/intel/compiler/elk/tests/gen9/sends.asm | 268 -- .../compiler/elk/tests/gen9/sends.expected | 134 - src/intel/compiler/elk/tests/gen9/shl.asm | 13 - .../compiler/elk/tests/gen9/shl.expected | 13 - src/intel/compiler/elk/tests/gen9/shr.asm | 8 - .../compiler/elk/tests/gen9/shr.expected | 8 - src/intel/compiler/elk/tests/gen9/wait.asm | 3 - .../compiler/elk/tests/gen9/wait.expected | 3 - src/intel/compiler/elk/tests/gen9/while.asm | 5 - .../compiler/elk/tests/gen9/while.expected | 4 - src/intel/compiler/elk/tests/gen9/xor.asm | 2 - .../compiler/elk/tests/gen9/xor.expected | 2 - 124 files changed, 17536 deletions(-) delete mode 100644 src/intel/compiler/elk/brw_fs_scoreboard.cpp delete mode 100644 src/intel/compiler/elk/brw_kernel.c delete mode 100644 src/intel/compiler/elk/brw_kernel.h delete mode 100644 src/intel/compiler/elk/brw_mesh.cpp delete mode 100644 src/intel/compiler/elk/brw_nir_lower_cooperative_matrix.c delete mode 100644 src/intel/compiler/elk/brw_nir_lower_intersection_shader.c delete mode 100644 src/intel/compiler/elk/brw_nir_lower_ray_queries.c delete mode 100644 src/intel/compiler/elk/brw_nir_lower_rt_intrinsics.c delete mode 100644 src/intel/compiler/elk/brw_nir_lower_shader_calls.c delete mode 100644 src/intel/compiler/elk/brw_nir_rt.c delete mode 100644 src/intel/compiler/elk/brw_nir_rt.h delete mode 100644 src/intel/compiler/elk/brw_nir_rt_builder.h delete mode 100644 src/intel/compiler/elk/brw_rt.h delete mode 100644 src/intel/compiler/elk/intel_clc.c delete mode 100644 src/intel/compiler/elk/test_fs_scoreboard.cpp delete mode 100644 src/intel/compiler/elk/tests/gen11/cr0.asm delete mode 100644 src/intel/compiler/elk/tests/gen11/cr0.expected delete mode 100644 src/intel/compiler/elk/tests/gen11/rol.asm delete mode 100644 src/intel/compiler/elk/tests/gen11/rol.expected delete mode 100644 src/intel/compiler/elk/tests/gen11/ror.asm delete mode 100644 src/intel/compiler/elk/tests/gen11/ror.expected delete mode 100644 src/intel/compiler/elk/tests/gen12.5/add3.asm delete mode 100644 src/intel/compiler/elk/tests/gen12.5/add3.expected delete mode 100644 src/intel/compiler/elk/tests/gen12.5/send.asm delete mode 100644 src/intel/compiler/elk/tests/gen12.5/send.expected delete mode 100644 src/intel/compiler/elk/tests/gen12.5/swsb.asm delete mode 100644 src/intel/compiler/elk/tests/gen12.5/swsb.expected delete mode 100644 src/intel/compiler/elk/tests/gen12/dp4a.asm delete mode 100644 src/intel/compiler/elk/tests/gen12/dp4a.expected delete mode 100644 src/intel/compiler/elk/tests/gen12/send.asm delete mode 100644 src/intel/compiler/elk/tests/gen12/send.expected delete mode 100644 src/intel/compiler/elk/tests/gen12/swsb.asm delete mode 100644 src/intel/compiler/elk/tests/gen12/swsb.expected delete mode 100644 src/intel/compiler/elk/tests/gen12/sync.asm delete mode 100644 src/intel/compiler/elk/tests/gen12/sync.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/add.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/add.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/and.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/and.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/asr.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/asr.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/bfe.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/bfe.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/bfi1.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/bfi1.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/bfi2.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/bfi2.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/bfrev.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/bfrev.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/break.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/break.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/cbit.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/cbit.expected delete mode 100644 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src/intel/compiler/elk/tests/gen9/shr.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/wait.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/wait.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/while.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/while.expected delete mode 100644 src/intel/compiler/elk/tests/gen9/xor.asm delete mode 100644 src/intel/compiler/elk/tests/gen9/xor.expected diff --git a/src/intel/compiler/elk/brw_fs.cpp b/src/intel/compiler/elk/brw_fs.cpp index 2a9cee96c5e..fcd81fe03c1 100644 --- a/src/intel/compiler/elk/brw_fs.cpp +++ b/src/intel/compiler/elk/brw_fs.cpp @@ -3490,8 +3490,6 @@ fs_visitor::emit_repclear_shader() calculate_cfg(); this->first_non_payload_grf = payload().num_regs; - - lower_scoreboard(); } /** @@ -6823,8 +6821,6 @@ fs_visitor::allocate_registers(bool allow_spilling) */ assert(prog_data->total_scratch < max_scratch_size); } - - lower_scoreboard(); } bool diff --git a/src/intel/compiler/elk/brw_fs_scoreboard.cpp b/src/intel/compiler/elk/brw_fs_scoreboard.cpp deleted file mode 100644 index 144179941c2..00000000000 --- a/src/intel/compiler/elk/brw_fs_scoreboard.cpp +++ /dev/null @@ -1,1365 +0,0 @@ -/* - * Copyright © 2019 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -/** @file brw_fs_scoreboard.cpp - * - * Gfx12+ hardware lacks the register scoreboard logic that used to guarantee - * data coherency between register reads and writes in previous generations. - * This lowering pass runs after register allocation in order to make up for - * it. - * - * It works by performing global dataflow analysis in order to determine the - * set of potential dependencies of every instruction in the shader, and then - * inserts any required SWSB annotations and additional SYNC instructions in - * order to guarantee data coherency. - * - * WARNING - Access of the following (rarely used) ARF registers is not - * tracked here, and require the RegDist SWSB annotation to be set - * to 1 by the generator in order to avoid data races: - * - * - sp stack pointer - * - sr0 state register - * - cr0 control register - * - ip instruction pointer - * - tm0 timestamp register - * - dbg0 debug register - * - acc2-9 special accumulator registers on TGL - * - mme0-7 math macro extended accumulator registers - * - * The following ARF registers don't need to be tracked here because data - * coherency is still provided transparently by the hardware: - * - * - f0-1 flag registers - * - n0 notification register - * - tdr0 thread dependency register - */ - -#include "brw_fs.h" -#include "brw_fs_builder.h" -#include "brw_cfg.h" - -using namespace brw; - -namespace { - /** - * In-order instruction accounting. - * @{ - */ - - /** - * Return the RegDist pipeline the hardware will synchronize with if no - * pipeline information is provided in the SWSB annotation of an - * instruction (e.g. when TGL_PIPE_NONE is specified in tgl_swsb). - */ - tgl_pipe - inferred_sync_pipe(const struct intel_device_info *devinfo, const fs_inst *inst) - { - if (devinfo->verx10 >= 125) { - bool has_int_src = false, has_long_src = false; - const bool has_long_pipe = !devinfo->has_64bit_float_via_math_pipe; - - if (is_send(inst)) - return TGL_PIPE_NONE; - - for (unsigned i = 0; i < inst->sources; i++) { - if (inst->src[i].file != BAD_FILE && - !inst->is_control_source(i)) { - const brw_reg_type t = inst->src[i].type; - has_int_src |= !brw_reg_type_is_floating_point(t); - has_long_src |= type_sz(t) >= 8; - } - } - - /* Avoid the emitting (RegDist, SWSB) annotations for long - * instructions on platforms where they are unordered. It's not clear - * what the inferred sync pipe is for them or if we are even allowed - * to use these annotations in this case. Return NONE, which should - * prevent baked_{un,}ordered_dependency_mode functions from even - * trying to emit these annotations. - */ - if (!has_long_pipe && has_long_src) - return TGL_PIPE_NONE; - - return has_long_src ? TGL_PIPE_LONG : - has_int_src ? TGL_PIPE_INT : - TGL_PIPE_FLOAT; - - } else { - return TGL_PIPE_FLOAT; - } - } - - /** - * Return the RegDist pipeline that will execute an instruction, or - * TGL_PIPE_NONE if the instruction is out-of-order and doesn't use the - * RegDist synchronization mechanism. - */ - tgl_pipe - inferred_exec_pipe(const struct intel_device_info *devinfo, const fs_inst *inst) - { - const brw_reg_type t = get_exec_type(inst); - const bool is_dword_multiply = !brw_reg_type_is_floating_point(t) && - ((inst->opcode == BRW_OPCODE_MUL && - MIN2(type_sz(inst->src[0].type), type_sz(inst->src[1].type)) >= 4) || - (inst->opcode == BRW_OPCODE_MAD && - MIN2(type_sz(inst->src[1].type), type_sz(inst->src[2].type)) >= 4)); - - if (is_unordered(devinfo, inst)) - return TGL_PIPE_NONE; - else if (devinfo->verx10 < 125) - return TGL_PIPE_FLOAT; - else if (inst->is_math() && devinfo->ver >= 20) - return TGL_PIPE_MATH; - else if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT || - inst->opcode == SHADER_OPCODE_BROADCAST || - inst->opcode == SHADER_OPCODE_SHUFFLE) - return TGL_PIPE_INT; - else if (inst->opcode == FS_OPCODE_PACK_HALF_2x16_SPLIT) - return TGL_PIPE_FLOAT; - else if (devinfo->ver >= 20 && type_sz(inst->dst.type) >= 8 && - brw_reg_type_is_floating_point(inst->dst.type)) { - assert(devinfo->has_64bit_float); - return TGL_PIPE_LONG; - } else if (devinfo->ver < 20 && - (type_sz(inst->dst.type) >= 8 || type_sz(t) >= 8 || - is_dword_multiply)) { - assert(devinfo->has_64bit_float || devinfo->has_64bit_int || - devinfo->has_integer_dword_mul); - return TGL_PIPE_LONG; - } else if (brw_reg_type_is_floating_point(inst->dst.type)) - return TGL_PIPE_FLOAT; - else - return TGL_PIPE_INT; - } - - /** - * Index of the \p p pipeline counter in the ordered_address vector defined - * below. - */ -#define IDX(p) (p >= TGL_PIPE_FLOAT ? unsigned(p - TGL_PIPE_FLOAT) : \ - (abort(), ~0u)) - - /** - * Number of in-order hardware instructions for pipeline index \p contained - * in this IR instruction. This determines the increment applied to the - * RegDist counter calculated for any ordered dependency that crosses this - * instruction. - */ - unsigned - ordered_unit(const struct intel_device_info *devinfo, const fs_inst *inst, - unsigned p) - { - switch (inst->opcode) { - case BRW_OPCODE_SYNC: - case BRW_OPCODE_DO: - case SHADER_OPCODE_UNDEF: - case SHADER_OPCODE_HALT_TARGET: - case FS_OPCODE_SCHEDULING_FENCE: - return 0; - default: - /* Note that the following is inaccurate for virtual instructions - * that expand to more in-order instructions than assumed here, but - * that can only lead to suboptimal execution ordering, data - * coherency won't be impacted. Providing exact RegDist counts for - * each virtual instruction would allow better ALU performance, but - * it would require keeping this switch statement in perfect sync - * with the generator in order to avoid data corruption. Lesson is - * (again) don't use virtual instructions if you want optimal - * scheduling. - */ - if (!is_unordered(devinfo, inst) && - (p == IDX(inferred_exec_pipe(devinfo, inst)) || - p == IDX(TGL_PIPE_ALL))) - return 1; - else - return 0; - } - } - - /** - * Type for an instruction counter that increments for in-order - * instructions only, arbitrarily denoted 'jp' throughout this lowering - * pass in order to distinguish it from the regular instruction counter. - * This is represented as a vector with an independent counter for each - * asynchronous ALU pipeline in the EU. - */ - struct ordered_address { - /** - * Construct the ordered address of a dependency known to execute on a - * single specified pipeline \p p (unless TGL_PIPE_NONE or TGL_PIPE_ALL - * is provided), in which case the vector counter will be initialized - * with all components equal to INT_MIN (always satisfied) except for - * component IDX(p). - */ - ordered_address(tgl_pipe p = TGL_PIPE_NONE, int jp0 = INT_MIN) { - for (unsigned q = 0; q < IDX(TGL_PIPE_ALL); q++) - jp[q] = (p == TGL_PIPE_NONE || (IDX(p) != q && p != TGL_PIPE_ALL) ? - INT_MIN : jp0); - } - - int jp[IDX(TGL_PIPE_ALL)]; - - friend bool - operator==(const ordered_address &jp0, const ordered_address &jp1) - { - for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) { - if (jp0.jp[p] != jp1.jp[p]) - return false; - } - - return true; - } - }; - - /** - * Return true if the specified ordered address is trivially satisfied for - * all pipelines except potentially for the specified pipeline \p p. - */ - bool - is_single_pipe(const ordered_address &jp, tgl_pipe p) - { - for (unsigned q = 0; q < IDX(TGL_PIPE_ALL); q++) { - if ((p == TGL_PIPE_NONE || IDX(p) != q) && jp.jp[q] > INT_MIN) - return false; - } - - return true; - } - - /** - * Return the number of instructions in the program. - */ - unsigned - num_instructions(const backend_shader *shader) - { - return shader->cfg->blocks[shader->cfg->num_blocks - 1]->end_ip + 1; - } - - /** - * Calculate the local ordered_address instruction counter at every - * instruction of the shader for subsequent constant-time look-up. - */ - ordered_address * - ordered_inst_addresses(const fs_visitor *shader) - { - ordered_address *jps = new ordered_address[num_instructions(shader)]; - ordered_address jp(TGL_PIPE_ALL, 0); - unsigned ip = 0; - - foreach_block_and_inst(block, fs_inst, inst, shader->cfg) { - jps[ip] = jp; - for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) - jp.jp[p] += ordered_unit(shader->devinfo, inst, p); - ip++; - } - - return jps; - } - - /** - * Synchronization mode required for data manipulated by in-order - * instructions. - * - * Similar to tgl_sbid_mode, but without SET mode. Defined as a separate - * enum for additional type safety. The hardware doesn't provide control - * over the synchronization mode for RegDist annotations, this is only used - * internally in this pass in order to optimize out redundant read - * dependencies where possible. - */ - enum tgl_regdist_mode { - TGL_REGDIST_NULL = 0, - TGL_REGDIST_SRC = 1, - TGL_REGDIST_DST = 2 - }; - - /** - * Allow bitwise arithmetic of tgl_regdist_mode enums. - */ - tgl_regdist_mode - operator|(tgl_regdist_mode x, tgl_regdist_mode y) - { - return tgl_regdist_mode(unsigned(x) | unsigned(y)); - } - - tgl_regdist_mode - operator&(tgl_regdist_mode x, tgl_regdist_mode y) - { - return tgl_regdist_mode(unsigned(x) & unsigned(y)); - } - - tgl_regdist_mode & - operator|=(tgl_regdist_mode &x, tgl_regdist_mode y) - { - return x = x | y; - } - - tgl_regdist_mode & - operator&=(tgl_regdist_mode &x, tgl_regdist_mode y) - { - return x = x & y; - } - - /** @} */ - - /** - * Representation of an equivalence relation among the set of unsigned - * integers. - * - * Its initial state is the identity relation '~' such that i ~ j if and - * only if i == j for every pair of unsigned integers i and j. - */ - struct equivalence_relation { - equivalence_relation(unsigned n) : is(new unsigned[n]), n(n) - { - for (unsigned i = 0; i < n; i++) - is[i] = i; - } - - ~equivalence_relation() - { - delete[] is; - } - - /** - * Return equivalence class index of the specified element. Effectively - * this is the numeric value of an arbitrary representative from the - * equivalence class. - * - * Allows the evaluation of the equivalence relation according to the - * rule that i ~ j if and only if lookup(i) == lookup(j). - */ - unsigned - lookup(unsigned i) const - { - if (i < n && is[i] != i) - return lookup(is[i]); - else - return i; - } - - /** - * Create an array with the results of the lookup() method for - * constant-time evaluation. - */ - unsigned * - flatten() const - { - unsigned *ids = new unsigned[n]; - - for (unsigned i = 0; i < n; i++) - ids[i] = lookup(i); - - return ids; - } - - /** - * Mutate the existing equivalence relation minimally by imposing the - * additional requirement that i ~ j. - * - * The algorithm updates the internal representation recursively in - * order to guarantee transitivity while preserving the previously - * specified equivalence requirements. - */ - unsigned - link(unsigned i, unsigned j) - { - const unsigned k = lookup(i); - assign(i, k); - assign(j, k); - return k; - } - - private: - equivalence_relation(const equivalence_relation &); - - equivalence_relation & - operator=(const equivalence_relation &); - - /** - * Assign the representative of \p from to be equivalent to \p to. - * - * At the same time the data structure is partially flattened as much as - * it's possible without increasing the number of recursive calls. - */ - void - assign(unsigned from, unsigned to) - { - if (from != to) { - assert(from < n); - - if (is[from] != from) - assign(is[from], to); - - is[from] = to; - } - } - - unsigned *is; - unsigned n; - }; - - /** - * Representation of a data dependency between two instructions in the - * program. - * @{ - */ - struct dependency { - /** - * No dependency information. - */ - dependency() : ordered(TGL_REGDIST_NULL), jp(), - unordered(TGL_SBID_NULL), id(0), - exec_all(false) {} - - /** - * Construct a dependency on the in-order instruction with the provided - * ordered_address instruction counter. - */ - dependency(tgl_regdist_mode mode, const ordered_address &jp, - bool exec_all) : - ordered(mode), jp(jp), unordered(TGL_SBID_NULL), id(0), - exec_all(exec_all) {} - - /** - * Construct a dependency on the out-of-order instruction with the - * specified synchronization token. - */ - dependency(tgl_sbid_mode mode, unsigned id, bool exec_all) : - ordered(TGL_REGDIST_NULL), jp(), unordered(mode), id(id), - exec_all(exec_all) {} - - /** - * Synchronization mode of in-order dependency, or zero if no in-order - * dependency is present. - */ - tgl_regdist_mode ordered; - - /** - * Instruction counter of in-order dependency. - * - * For a dependency part of a different block in the program, this is - * relative to the specific control flow path taken between the - * dependency and the current block: It is the ordered_address such that - * the difference between it and the ordered_address of the first - * instruction of the current block is exactly the number of in-order - * instructions across that control flow path. It is not guaranteed to - * be equal to the local ordered_address of the generating instruction - * [as returned by ordered_inst_addresses()], except for block-local - * dependencies. - */ - ordered_address jp; - - /** - * Synchronization mode of unordered dependency, or zero if no unordered - * dependency is present. - */ - tgl_sbid_mode unordered; - - /** Synchronization token of out-of-order dependency. */ - unsigned id; - - /** - * Whether the dependency could be run with execution masking disabled, - * which might lead to the unwanted execution of the generating - * instruction in cases where a BB is executed with all channels - * disabled due to hardware bug Wa_1407528679. - */ - bool exec_all; - - /** - * Trivial in-order dependency that's always satisfied. - * - * Note that unlike a default-constructed dependency() which is also - * trivially satisfied, this is considered to provide dependency - * information and can be used to clear a previously pending dependency - * via shadow(). - */ - static const dependency done; - - friend bool - operator==(const dependency &dep0, const dependency &dep1) - { - return dep0.ordered == dep1.ordered && - dep0.jp == dep1.jp && - dep0.unordered == dep1.unordered && - dep0.id == dep1.id && - dep0.exec_all == dep1.exec_all; - } - - friend bool - operator!=(const dependency &dep0, const dependency &dep1) - { - return !(dep0 == dep1); - } - }; - - const dependency dependency::done = - dependency(TGL_REGDIST_DST, ordered_address(), false); - - /** - * Return whether \p dep contains any dependency information. - */ - bool - is_valid(const dependency &dep) - { - return dep.ordered || dep.unordered; - } - - /** - * Combine \p dep0 and \p dep1 into a single dependency object that is only - * satisfied when both original dependencies are satisfied. This might - * involve updating the equivalence relation \p eq in order to make sure - * that both out-of-order dependencies are assigned the same hardware SBID - * as synchronization token. - */ - dependency - merge(equivalence_relation &eq, - const dependency &dep0, const dependency &dep1) - { - dependency dep; - - if (dep0.ordered || dep1.ordered) { - dep.ordered = dep0.ordered | dep1.ordered; - for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) - dep.jp.jp[p] = MAX2(dep0.jp.jp[p], dep1.jp.jp[p]); - } - - if (dep0.unordered || dep1.unordered) { - dep.unordered = dep0.unordered | dep1.unordered; - dep.id = eq.link(dep0.unordered ? dep0.id : dep1.id, - dep1.unordered ? dep1.id : dep0.id); - } - - dep.exec_all = dep0.exec_all || dep1.exec_all; - - return dep; - } - - /** - * Override dependency information of \p dep0 with that of \p dep1. - */ - dependency - shadow(const dependency &dep0, const dependency &dep1) - { - if (dep0.ordered == TGL_REGDIST_SRC && - is_valid(dep1) && !(dep1.unordered & TGL_SBID_DST) && - !(dep1.ordered & TGL_REGDIST_DST)) { - /* As an optimization (see dependency_for_read()), - * instructions with a RaR dependency don't synchronize - * against a previous in-order read, so we need to pass - * through both ordered dependencies instead of simply - * dropping the first one. Otherwise we could encounter a - * WaR data hazard between OP0 and OP2 in cases like: - * - * OP0 r1:f r0:d - * OP1 r2:d r0:d - * OP2 r0:d r3:d - * - * since only the integer-pipeline r0 dependency from OP1 - * would be visible to OP2, even though OP0 could technically - * execute after OP1 due to the floating-point and integer - * pipelines being asynchronous on Gfx12.5+ platforms, so - * synchronizing OP2 against OP1 would be insufficient. - */ - dependency dep = dep1; - - dep.ordered |= dep0.ordered; - for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) - dep.jp.jp[p] = MAX2(dep.jp.jp[p], dep0.jp.jp[p]); - - return dep; - } else { - return is_valid(dep1) ? dep1 : dep0; - } - } - - /** - * Translate dependency information across the program. - * - * This returns a dependency on the same instruction translated to the - * ordered_address space of a different block. The correct shift for - * transporting a dependency across an edge of the CFG is the difference - * between the local ordered_address of the first instruction of the target - * block and the local ordered_address of the instruction immediately after - * the end of the origin block. - */ - dependency - transport(dependency dep, int delta[IDX(TGL_PIPE_ALL)]) - { - if (dep.ordered) { - for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) { - if (dep.jp.jp[p] > INT_MIN) - dep.jp.jp[p] += delta[p]; - } - } - - return dep; - } - - /** - * Return simplified dependency removing any synchronization modes not - * applicable to an instruction reading the same register location. - */ - dependency - dependency_for_read(dependency dep) - { - dep.ordered &= TGL_REGDIST_DST; - return dep; - } - - /** - * Return simplified dependency removing any synchronization modes not - * applicable to an instruction \p inst writing the same register location. - * - * This clears any WaR dependency for writes performed from the same - * pipeline as the read, since there is no possibility for a data hazard. - */ - dependency - dependency_for_write(const struct intel_device_info *devinfo, - const fs_inst *inst, dependency dep) - { - if (!is_unordered(devinfo, inst) && - is_single_pipe(dep.jp, inferred_exec_pipe(devinfo, inst))) - dep.ordered &= TGL_REGDIST_DST; - return dep; - } - - /** @} */ - - /** - * Scoreboard representation. This keeps track of the data dependencies of - * registers with GRF granularity. - */ - class scoreboard { - public: - /** - * Look up the most current data dependency for register \p r. - */ - dependency - get(const fs_reg &r) const - { - if (const dependency *p = const_cast(this)->dep(r)) - return *p; - else - return dependency(); - } - - /** - * Specify the most current data dependency for register \p r. - */ - void - set(const fs_reg &r, const dependency &d) - { - if (dependency *p = dep(r)) - *p = d; - } - - /** - * Component-wise merge() of corresponding dependencies from two - * scoreboard objects. \sa merge(). - */ - friend scoreboard - merge(equivalence_relation &eq, - const scoreboard &sb0, const scoreboard &sb1) - { - scoreboard sb; - - for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) - sb.grf_deps[i] = merge(eq, sb0.grf_deps[i], sb1.grf_deps[i]); - - sb.addr_dep = merge(eq, sb0.addr_dep, sb1.addr_dep); - sb.accum_dep = merge(eq, sb0.accum_dep, sb1.accum_dep); - - return sb; - } - - /** - * Component-wise shadow() of corresponding dependencies from two - * scoreboard objects. \sa shadow(). - */ - friend scoreboard - shadow(const scoreboard &sb0, const scoreboard &sb1) - { - scoreboard sb; - - for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) - sb.grf_deps[i] = shadow(sb0.grf_deps[i], sb1.grf_deps[i]); - - sb.addr_dep = shadow(sb0.addr_dep, sb1.addr_dep); - sb.accum_dep = shadow(sb0.accum_dep, sb1.accum_dep); - - return sb; - } - - /** - * Component-wise transport() of dependencies from a scoreboard - * object. \sa transport(). - */ - friend scoreboard - transport(const scoreboard &sb0, int delta[IDX(TGL_PIPE_ALL)]) - { - scoreboard sb; - - for (unsigned i = 0; i < ARRAY_SIZE(sb.grf_deps); i++) - sb.grf_deps[i] = transport(sb0.grf_deps[i], delta); - - sb.addr_dep = transport(sb0.addr_dep, delta); - sb.accum_dep = transport(sb0.accum_dep, delta); - - return sb; - } - - friend bool - operator==(const scoreboard &sb0, const scoreboard &sb1) - { - for (unsigned i = 0; i < ARRAY_SIZE(sb0.grf_deps); i++) { - if (sb0.grf_deps[i] != sb1.grf_deps[i]) - return false; - } - - if (sb0.addr_dep != sb1.addr_dep) - return false; - - if (sb0.accum_dep != sb1.accum_dep) - return false; - - return true; - } - - friend bool - operator!=(const scoreboard &sb0, const scoreboard &sb1) - { - return !(sb0 == sb1); - } - - private: - dependency grf_deps[XE2_MAX_GRF]; - dependency addr_dep; - dependency accum_dep; - - dependency * - dep(const fs_reg &r) - { - const unsigned reg = (r.file == VGRF ? r.nr + r.offset / REG_SIZE : - reg_offset(r) / REG_SIZE); - - return (r.file == VGRF || r.file == FIXED_GRF ? &grf_deps[reg] : - r.file == MRF ? &grf_deps[GFX7_MRF_HACK_START + reg] : - r.file == ARF && reg >= BRW_ARF_ADDRESS && - reg < BRW_ARF_ACCUMULATOR ? &addr_dep : - r.file == ARF && reg >= BRW_ARF_ACCUMULATOR && - reg < BRW_ARF_FLAG ? &accum_dep : - NULL); - } - }; - - /** - * Dependency list handling. - * @{ - */ - struct dependency_list { - dependency_list() : deps(NULL), n(0) {} - - ~dependency_list() - { - free(deps); - } - - void - push_back(const dependency &dep) - { - deps = (dependency *)realloc(deps, (n + 1) * sizeof(*deps)); - deps[n++] = dep; - } - - unsigned - size() const - { - return n; - } - - const dependency & - operator[](unsigned i) const - { - assert(i < n); - return deps[i]; - } - - dependency & - operator[](unsigned i) - { - assert(i < n); - return deps[i]; - } - - private: - dependency_list(const dependency_list &); - dependency_list & - operator=(const dependency_list &); - - dependency *deps; - unsigned n; - }; - - /** - * Add dependency \p dep to the list of dependencies of an instruction - * \p deps. - */ - void - add_dependency(const unsigned *ids, dependency_list &deps, dependency dep) - { - if (is_valid(dep)) { - /* Translate the unordered dependency token first in order to keep - * the list minimally redundant. - */ - if (dep.unordered) - dep.id = ids[dep.id]; - - /* Try to combine the specified dependency with any existing ones. */ - for (unsigned i = 0; i < deps.size(); i++) { - /* Don't combine otherwise matching dependencies if there is an - * exec_all mismatch which would cause a SET dependency to gain an - * exec_all flag, since that would prevent it from being baked - * into the instruction we want to allocate an SBID for. - */ - if (deps[i].exec_all != dep.exec_all && - (!deps[i].exec_all || (dep.unordered & TGL_SBID_SET)) && - (!dep.exec_all || (deps[i].unordered & TGL_SBID_SET))) - continue; - - if (dep.ordered && deps[i].ordered) { - for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) - deps[i].jp.jp[p] = MAX2(deps[i].jp.jp[p], dep.jp.jp[p]); - - deps[i].ordered |= dep.ordered; - deps[i].exec_all |= dep.exec_all; - dep.ordered = TGL_REGDIST_NULL; - } - - if (dep.unordered && deps[i].unordered && deps[i].id == dep.id) { - deps[i].unordered |= dep.unordered; - deps[i].exec_all |= dep.exec_all; - dep.unordered = TGL_SBID_NULL; - } - } - - /* Add it to the end of the list if necessary. */ - if (is_valid(dep)) - deps.push_back(dep); - } - } - - /** - * Construct a tgl_swsb annotation encoding any ordered dependencies from - * the dependency list \p deps of an instruction with ordered_address \p - * jp. If \p exec_all is false only dependencies known to be executed with - * channel masking applied will be considered in the calculation. - */ - tgl_swsb - ordered_dependency_swsb(const dependency_list &deps, - const ordered_address &jp, - bool exec_all) - { - tgl_pipe p = TGL_PIPE_NONE; - unsigned min_dist = ~0u; - - for (unsigned i = 0; i < deps.size(); i++) { - if (deps[i].ordered && exec_all >= deps[i].exec_all) { - for (unsigned q = 0; q < IDX(TGL_PIPE_ALL); q++) { - const unsigned dist = jp.jp[q] - int64_t(deps[i].jp.jp[q]); - const unsigned max_dist = (q == IDX(TGL_PIPE_LONG) ? 14 : 10); - assert(jp.jp[q] > deps[i].jp.jp[q]); - if (dist <= max_dist) { - p = (p && IDX(p) != q ? TGL_PIPE_ALL : - tgl_pipe(TGL_PIPE_FLOAT + q)); - min_dist = MIN3(min_dist, dist, 7); - } - } - } - } - - return { p ? min_dist : 0, p }; - } - - /** - * Return whether the dependency list \p deps of an instruction with - * ordered_address \p jp has any non-trivial ordered dependencies. If \p - * exec_all is false only dependencies known to be executed with channel - * masking applied will be considered in the calculation. - */ - bool - find_ordered_dependency(const dependency_list &deps, - const ordered_address &jp, - bool exec_all) - { - return ordered_dependency_swsb(deps, jp, exec_all).regdist; - } - - /** - * Return the full tgl_sbid_mode bitset for the first unordered dependency - * on the list \p deps that matches the specified tgl_sbid_mode, or zero if - * no such dependency is present. If \p exec_all is false only - * dependencies known to be executed with channel masking applied will be - * considered in the calculation. - */ - tgl_sbid_mode - find_unordered_dependency(const dependency_list &deps, - tgl_sbid_mode unordered, - bool exec_all) - { - if (unordered) { - for (unsigned i = 0; i < deps.size(); i++) { - if ((unordered & deps[i].unordered) && - exec_all >= deps[i].exec_all) - return deps[i].unordered; - } - } - - return TGL_SBID_NULL; - } - - /** - * Return the tgl_sbid_mode bitset of an unordered dependency from the list - * \p deps that can be represented directly in the SWSB annotation of the - * instruction without additional SYNC instructions, or zero if no such - * dependency is present. - */ - tgl_sbid_mode - baked_unordered_dependency_mode(const struct intel_device_info *devinfo, - const fs_inst *inst, - const dependency_list &deps, - const ordered_address &jp) - { - const bool exec_all = inst->force_writemask_all; - const bool has_ordered = find_ordered_dependency(deps, jp, exec_all); - const tgl_pipe ordered_pipe = ordered_dependency_swsb(deps, jp, - exec_all).pipe; - - if (find_unordered_dependency(deps, TGL_SBID_SET, exec_all)) - return find_unordered_dependency(deps, TGL_SBID_SET, exec_all); - else if (has_ordered && is_unordered(devinfo, inst)) - return TGL_SBID_NULL; - else if (find_unordered_dependency(deps, TGL_SBID_DST, exec_all) && - (!has_ordered || ordered_pipe == inferred_sync_pipe(devinfo, inst))) - return find_unordered_dependency(deps, TGL_SBID_DST, exec_all); - else if (!has_ordered) - return find_unordered_dependency(deps, TGL_SBID_SRC, exec_all); - else - return TGL_SBID_NULL; - } - - /** - * Return whether an ordered dependency from the list \p deps can be - * represented directly in the SWSB annotation of the instruction without - * additional SYNC instructions. - */ - bool - baked_ordered_dependency_mode(const struct intel_device_info *devinfo, - const fs_inst *inst, - const dependency_list &deps, - const ordered_address &jp) - { - const bool exec_all = inst->force_writemask_all; - const bool has_ordered = find_ordered_dependency(deps, jp, exec_all); - const tgl_pipe ordered_pipe = ordered_dependency_swsb(deps, jp, - exec_all).pipe; - const tgl_sbid_mode unordered_mode = - baked_unordered_dependency_mode(devinfo, inst, deps, jp); - - if (!has_ordered) - return false; - else if (!unordered_mode) - return true; - else - return ordered_pipe == inferred_sync_pipe(devinfo, inst) && - unordered_mode == (is_unordered(devinfo, inst) ? TGL_SBID_SET : - TGL_SBID_DST); - } - - /** @} */ - - /** - * Shader instruction dependency calculation. - * @{ - */ - - /** - * Update scoreboard object \p sb to account for the execution of - * instruction \p inst. - */ - void - update_inst_scoreboard(const fs_visitor *shader, const ordered_address *jps, - const fs_inst *inst, unsigned ip, scoreboard &sb) - { - const bool exec_all = inst->force_writemask_all; - const struct intel_device_info *devinfo = shader->devinfo; - const tgl_pipe p = inferred_exec_pipe(devinfo, inst); - const ordered_address jp = p ? ordered_address(p, jps[ip].jp[IDX(p)]) : - ordered_address(); - const bool is_ordered = ordered_unit(devinfo, inst, IDX(TGL_PIPE_ALL)); - const bool is_unordered_math = - (inst->is_math() && devinfo->ver < 20) || - (devinfo->has_64bit_float_via_math_pipe && - (get_exec_type(inst) == BRW_REGISTER_TYPE_DF || - inst->dst.type == BRW_REGISTER_TYPE_DF)); - - /* Track any source registers that may be fetched asynchronously by this - * instruction, otherwise clear the dependency in order to avoid - * subsequent redundant synchronization. - */ - for (unsigned i = 0; i < inst->sources; i++) { - const dependency rd_dep = - (inst->is_payload(i) || - inst->opcode == BRW_OPCODE_DPAS || - is_unordered_math) ? dependency(TGL_SBID_SRC, ip, exec_all) : - is_ordered ? dependency(TGL_REGDIST_SRC, jp, exec_all) : - dependency::done; - - for (unsigned j = 0; j < regs_read(inst, i); j++) { - const fs_reg r = byte_offset(inst->src[i], REG_SIZE * j); - sb.set(r, shadow(sb.get(r), rd_dep)); - } - } - - if (inst->reads_accumulator_implicitly()) - sb.set(brw_acc_reg(8), dependency(TGL_REGDIST_SRC, jp, exec_all)); - - if (is_send(inst) && inst->base_mrf != -1) { - const dependency rd_dep = dependency(TGL_SBID_SRC, ip, exec_all); - - for (unsigned j = 0; j < inst->mlen; j++) - sb.set(brw_uvec_mrf(8, inst->base_mrf + j, 0), rd_dep); - } - - /* Track any destination registers of this instruction. */ - const dependency wr_dep = - is_unordered(devinfo, inst) ? dependency(TGL_SBID_DST, ip, exec_all) : - is_ordered ? dependency(TGL_REGDIST_DST, jp, exec_all) : - dependency(); - - if (inst->writes_accumulator_implicitly(devinfo)) - sb.set(brw_acc_reg(8), wr_dep); - - if (is_valid(wr_dep) && inst->dst.file != BAD_FILE && - !inst->dst.is_null()) { - for (unsigned j = 0; j < regs_written(inst); j++) - sb.set(byte_offset(inst->dst, REG_SIZE * j), wr_dep); - } - } - - /** - * Calculate scoreboard objects locally that represent any pending (and - * unconditionally resolved) dependencies at the end of each block of the - * program. - */ - scoreboard * - gather_block_scoreboards(const fs_visitor *shader, - const ordered_address *jps) - { - scoreboard *sbs = new scoreboard[shader->cfg->num_blocks]; - unsigned ip = 0; - - foreach_block_and_inst(block, fs_inst, inst, shader->cfg) - update_inst_scoreboard(shader, jps, inst, ip++, sbs[block->num]); - - return sbs; - } - - /** - * Propagate data dependencies globally through the control flow graph - * until a fixed point is reached. - * - * Calculates the set of dependencies potentially pending at the beginning - * of each block, and returns it as an array of scoreboard objects. - */ - scoreboard * - propagate_block_scoreboards(const fs_visitor *shader, - const ordered_address *jps, - equivalence_relation &eq) - { - const scoreboard *delta_sbs = gather_block_scoreboards(shader, jps); - scoreboard *in_sbs = new scoreboard[shader->cfg->num_blocks]; - scoreboard *out_sbs = new scoreboard[shader->cfg->num_blocks]; - - for (bool progress = true; progress;) { - progress = false; - - foreach_block(block, shader->cfg) { - const scoreboard sb = shadow(in_sbs[block->num], - delta_sbs[block->num]); - - if (sb != out_sbs[block->num]) { - foreach_list_typed(bblock_link, child_link, link, - &block->children) { - scoreboard &in_sb = in_sbs[child_link->block->num]; - int delta[IDX(TGL_PIPE_ALL)]; - - for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) - delta[p] = jps[child_link->block->start_ip].jp[p] - - jps[block->end_ip].jp[p] - - ordered_unit(shader->devinfo, - static_cast(block->end()), p); - - in_sb = merge(eq, in_sb, transport(sb, delta)); - } - - out_sbs[block->num] = sb; - progress = true; - } - } - } - - delete[] delta_sbs; - delete[] out_sbs; - - return in_sbs; - } - - /** - * Return the list of potential dependencies of each instruction in the - * shader based on the result of global dependency analysis. - */ - dependency_list * - gather_inst_dependencies(const fs_visitor *shader, - const ordered_address *jps) - { - const struct intel_device_info *devinfo = shader->devinfo; - equivalence_relation eq(num_instructions(shader)); - scoreboard *sbs = propagate_block_scoreboards(shader, jps, eq); - const unsigned *ids = eq.flatten(); - dependency_list *deps = new dependency_list[num_instructions(shader)]; - unsigned ip = 0; - - foreach_block_and_inst(block, fs_inst, inst, shader->cfg) { - const bool exec_all = inst->force_writemask_all; - const tgl_pipe p = inferred_exec_pipe(devinfo, inst); - scoreboard &sb = sbs[block->num]; - - for (unsigned i = 0; i < inst->sources; i++) { - for (unsigned j = 0; j < regs_read(inst, i); j++) - add_dependency(ids, deps[ip], dependency_for_read( - sb.get(byte_offset(inst->src[i], REG_SIZE * j)))); - } - - if (inst->reads_accumulator_implicitly()) { - /* Wa_22012725308: - * - * "When the accumulator registers are used as source and/or - * destination, hardware does not ensure prevention of write - * after read hazard across execution pipes." - */ - const dependency dep = sb.get(brw_acc_reg(8)); - if (dep.ordered && !is_single_pipe(dep.jp, p)) - add_dependency(ids, deps[ip], dep); - } - - if (is_send(inst) && inst->base_mrf != -1) { - for (unsigned j = 0; j < inst->mlen; j++) - add_dependency(ids, deps[ip], dependency_for_read( - sb.get(brw_uvec_mrf(8, inst->base_mrf + j, 0)))); - } - - if (is_unordered(devinfo, inst) && !inst->eot) - add_dependency(ids, deps[ip], - dependency(TGL_SBID_SET, ip, exec_all)); - - if (!inst->no_dd_check) { - if (inst->dst.file != BAD_FILE && !inst->dst.is_null() && - !inst->dst.is_accumulator()) { - for (unsigned j = 0; j < regs_written(inst); j++) { - add_dependency(ids, deps[ip], dependency_for_write(devinfo, inst, - sb.get(byte_offset(inst->dst, REG_SIZE * j)))); - } - } - - if (inst->writes_accumulator_implicitly(devinfo) || - inst->dst.is_accumulator()) { - /* Wa_22012725308: - * - * "When the accumulator registers are used as source and/or - * destination, hardware does not ensure prevention of write - * after read hazard across execution pipes." - */ - const dependency dep = sb.get(brw_acc_reg(8)); - if (dep.ordered && !is_single_pipe(dep.jp, p)) - add_dependency(ids, deps[ip], dep); - } - - if (is_send(inst) && inst->base_mrf != -1) { - for (unsigned j = 0; j < inst->implied_mrf_writes(); j++) - add_dependency(ids, deps[ip], dependency_for_write(devinfo, inst, - sb.get(brw_uvec_mrf(8, inst->base_mrf + j, 0)))); - } - } - - update_inst_scoreboard(shader, jps, inst, ip, sb); - ip++; - } - - delete[] sbs; - delete[] ids; - - return deps; - } - - /** @} */ - - /** - * Allocate SBID tokens to track the execution of every out-of-order - * instruction of the shader. - */ - dependency_list * - allocate_inst_dependencies(const fs_visitor *shader, - const dependency_list *deps0) - { - /* XXX - Use bin-packing algorithm to assign hardware SBIDs optimally in - * shaders with a large number of SEND messages. - * - * XXX - Use 32 SBIDs on Xe2+ while in large GRF mode. - */ - const unsigned num_sbids = 16; - - /* Allocate an unordered dependency ID to hardware SBID translation - * table with as many entries as instructions there are in the shader, - * which is the maximum number of unordered IDs we can find in the - * program. - */ - unsigned *ids = new unsigned[num_instructions(shader)]; - for (unsigned ip = 0; ip < num_instructions(shader); ip++) - ids[ip] = ~0u; - - dependency_list *deps1 = new dependency_list[num_instructions(shader)]; - unsigned next_id = 0; - - for (unsigned ip = 0; ip < num_instructions(shader); ip++) { - for (unsigned i = 0; i < deps0[ip].size(); i++) { - const dependency &dep = deps0[ip][i]; - - if (dep.unordered && ids[dep.id] == ~0u) - ids[dep.id] = (next_id++) & (num_sbids - 1); - - add_dependency(ids, deps1[ip], dep); - } - } - - delete[] ids; - - return deps1; - } - - /** - * Emit dependency information provided by \p deps into the shader, - * inserting additional SYNC instructions for dependencies that can't be - * represented directly by annotating existing instructions. - */ - void - emit_inst_dependencies(fs_visitor *shader, - const ordered_address *jps, - const dependency_list *deps) - { - const struct intel_device_info *devinfo = shader->devinfo; - unsigned ip = 0; - - foreach_block_and_inst_safe(block, fs_inst, inst, shader->cfg) { - const bool exec_all = inst->force_writemask_all; - const bool ordered_mode = - baked_ordered_dependency_mode(devinfo, inst, deps[ip], jps[ip]); - const tgl_sbid_mode unordered_mode = - baked_unordered_dependency_mode(devinfo, inst, deps[ip], jps[ip]); - tgl_swsb swsb = !ordered_mode ? tgl_swsb() : - ordered_dependency_swsb(deps[ip], jps[ip], exec_all); - - for (unsigned i = 0; i < deps[ip].size(); i++) { - const dependency &dep = deps[ip][i]; - - if (dep.unordered) { - if (unordered_mode == dep.unordered && - exec_all >= dep.exec_all && !swsb.mode) { - /* Bake unordered dependency into the instruction's SWSB if - * possible, except in cases where the current instruction - * isn't marked NoMask but the dependency is, since that - * might lead to data coherency issues due to - * Wa_1407528679. - */ - swsb.sbid = dep.id; - swsb.mode = dep.unordered; - } else { - /* Emit dependency into the SWSB of an extra SYNC - * instruction. - */ - const fs_builder ibld = fs_builder(shader, block, inst) - .exec_all().group(1, 0); - fs_inst *sync = ibld.emit(BRW_OPCODE_SYNC, ibld.null_reg_ud(), - brw_imm_ud(TGL_SYNC_NOP)); - sync->sched.sbid = dep.id; - sync->sched.mode = dep.unordered; - assert(!(sync->sched.mode & TGL_SBID_SET)); - } - } - } - - for (unsigned i = 0; i < deps[ip].size(); i++) { - const dependency &dep = deps[ip][i]; - - if (dep.ordered && - find_ordered_dependency(deps[ip], jps[ip], true) && - (!ordered_mode || dep.exec_all > exec_all)) { - /* If the current instruction is not marked NoMask but an - * ordered dependency is, perform the synchronization as a - * separate NoMask SYNC instruction in order to avoid data - * coherency issues due to Wa_1407528679. The similar - * scenario with unordered dependencies should have been - * handled above. - */ - const fs_builder ibld = fs_builder(shader, block, inst) - .exec_all().group(1, 0); - fs_inst *sync = ibld.emit(BRW_OPCODE_SYNC, ibld.null_reg_ud(), - brw_imm_ud(TGL_SYNC_NOP)); - sync->sched = ordered_dependency_swsb(deps[ip], jps[ip], true); - break; - } - } - - /* Update the IR. */ - inst->sched = swsb; - inst->no_dd_check = inst->no_dd_clear = false; - ip++; - } - } -} - -bool -fs_visitor::lower_scoreboard() -{ - if (devinfo->ver >= 12) { - const ordered_address *jps = ordered_inst_addresses(this); - const dependency_list *deps0 = gather_inst_dependencies(this, jps); - const dependency_list *deps1 = allocate_inst_dependencies(this, deps0); - emit_inst_dependencies(this, jps, deps1); - delete[] deps1; - delete[] deps0; - delete[] jps; - } - - return true; -} diff --git a/src/intel/compiler/elk/brw_kernel.c b/src/intel/compiler/elk/brw_kernel.c deleted file mode 100644 index a85dc583a58..00000000000 --- a/src/intel/compiler/elk/brw_kernel.c +++ /dev/null @@ -1,790 +0,0 @@ -/* - * Copyright © 2020 Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_kernel.h" -#include "brw_nir.h" -#include "intel_nir.h" - -#include "intel_nir.h" -#include "nir_clc_helpers.h" -#include "compiler/nir/nir_builder.h" -#include "compiler/spirv/nir_spirv.h" -#include "dev/intel_debug.h" -#include "util/u_atomic.h" -#include "util/u_dynarray.h" - -static const nir_shader * -load_clc_shader(struct brw_compiler *compiler, struct disk_cache *disk_cache, - const nir_shader_compiler_options *nir_options, - const struct spirv_to_nir_options *spirv_options) -{ - if (compiler->clc_shader) - return compiler->clc_shader; - - nir_shader *nir = nir_load_libclc_shader(64, disk_cache, - spirv_options, nir_options, - disk_cache != NULL); - if (nir == NULL) - return NULL; - - const nir_shader *old_nir = - p_atomic_cmpxchg(&compiler->clc_shader, NULL, nir); - if (old_nir == NULL) { - /* We won the race */ - ralloc_steal(compiler, nir); - return nir; - } else { - /* Someone else built the shader first */ - ralloc_free(nir); - return old_nir; - } -} - -static nir_builder -builder_init_new_impl(nir_function *func) -{ - nir_function_impl *impl = nir_function_impl_create(func); - return nir_builder_at(nir_before_impl(impl)); -} - -static void -implement_atomic_builtin(nir_function *func, nir_atomic_op atomic_op, - enum glsl_base_type data_base_type, - nir_variable_mode mode) -{ - nir_builder b = builder_init_new_impl(func); - const struct glsl_type *data_type = glsl_scalar_type(data_base_type); - - unsigned p = 0; - - nir_deref_instr *ret = NULL; - ret = nir_build_deref_cast(&b, nir_load_param(&b, p++), - nir_var_function_temp, data_type, 0); - - nir_intrinsic_op op = nir_intrinsic_deref_atomic; - nir_intrinsic_instr *atomic = nir_intrinsic_instr_create(b.shader, op); - nir_intrinsic_set_atomic_op(atomic, atomic_op); - - for (unsigned i = 0; i < nir_intrinsic_infos[op].num_srcs; i++) { - nir_def *src = nir_load_param(&b, p++); - if (i == 0) { - /* The first source is our deref */ - assert(nir_intrinsic_infos[op].src_components[i] == -1); - src = &nir_build_deref_cast(&b, src, mode, data_type, 0)->def; - } - atomic->src[i] = nir_src_for_ssa(src); - } - - nir_def_init_for_type(&atomic->instr, &atomic->def, data_type); - - nir_builder_instr_insert(&b, &atomic->instr); - nir_store_deref(&b, ret, &atomic->def, ~0); -} - -static void -implement_sub_group_ballot_builtin(nir_function *func) -{ - nir_builder b = builder_init_new_impl(func); - nir_deref_instr *ret = - nir_build_deref_cast(&b, nir_load_param(&b, 0), - nir_var_function_temp, glsl_uint_type(), 0); - nir_def *cond = nir_load_param(&b, 1); - - nir_intrinsic_instr *ballot = - nir_intrinsic_instr_create(b.shader, nir_intrinsic_ballot); - ballot->src[0] = nir_src_for_ssa(cond); - ballot->num_components = 1; - nir_def_init(&ballot->instr, &ballot->def, 1, 32); - nir_builder_instr_insert(&b, &ballot->instr); - - nir_store_deref(&b, ret, &ballot->def, ~0); -} - -static bool -implement_intel_builtins(nir_shader *nir) -{ - bool progress = false; - - nir_foreach_function(func, nir) { - if (strcmp(func->name, "_Z10atomic_minPU3AS1Vff") == 0) { - /* float atom_min(__global float volatile *p, float val) */ - implement_atomic_builtin(func, nir_atomic_op_fmin, - GLSL_TYPE_FLOAT, nir_var_mem_global); - progress = true; - } else if (strcmp(func->name, "_Z10atomic_maxPU3AS1Vff") == 0) { - /* float atom_max(__global float volatile *p, float val) */ - implement_atomic_builtin(func, nir_atomic_op_fmax, - GLSL_TYPE_FLOAT, nir_var_mem_global); - progress = true; - } else if (strcmp(func->name, "_Z10atomic_minPU3AS3Vff") == 0) { - /* float atomic_min(__shared float volatile *, float) */ - implement_atomic_builtin(func, nir_atomic_op_fmin, - GLSL_TYPE_FLOAT, nir_var_mem_shared); - progress = true; - } else if (strcmp(func->name, "_Z10atomic_maxPU3AS3Vff") == 0) { - /* float atomic_max(__shared float volatile *, float) */ - implement_atomic_builtin(func, nir_atomic_op_fmax, - GLSL_TYPE_FLOAT, nir_var_mem_shared); - progress = true; - } else if (strcmp(func->name, "intel_sub_group_ballot") == 0) { - implement_sub_group_ballot_builtin(func); - progress = true; - } - } - - nir_shader_preserve_all_metadata(nir); - - return progress; -} - -static bool -lower_kernel_intrinsics(nir_shader *nir) -{ - nir_function_impl *impl = nir_shader_get_entrypoint(nir); - - bool progress = false; - - unsigned kernel_sysvals_start = 0; - unsigned kernel_arg_start = sizeof(struct brw_kernel_sysvals); - nir->num_uniforms += kernel_arg_start; - - nir_builder b = nir_builder_create(impl); - - nir_foreach_block(block, impl) { - nir_foreach_instr_safe(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - switch (intrin->intrinsic) { - case nir_intrinsic_load_kernel_input: { - b.cursor = nir_instr_remove(&intrin->instr); - - nir_intrinsic_instr *load = - nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform); - load->num_components = intrin->num_components; - load->src[0] = nir_src_for_ssa(nir_u2u32(&b, intrin->src[0].ssa)); - nir_intrinsic_set_base(load, kernel_arg_start); - nir_intrinsic_set_range(load, nir->num_uniforms); - nir_def_init(&load->instr, &load->def, - intrin->def.num_components, - intrin->def.bit_size); - nir_builder_instr_insert(&b, &load->instr); - - nir_def_rewrite_uses(&intrin->def, &load->def); - progress = true; - break; - } - - case nir_intrinsic_load_constant_base_ptr: { - b.cursor = nir_instr_remove(&intrin->instr); - nir_def *const_data_base_addr = nir_pack_64_2x32_split(&b, - nir_load_reloc_const_intel(&b, BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW), - nir_load_reloc_const_intel(&b, BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH)); - nir_def_rewrite_uses(&intrin->def, const_data_base_addr); - progress = true; - break; - } - - case nir_intrinsic_load_num_workgroups: { - b.cursor = nir_instr_remove(&intrin->instr); - - nir_intrinsic_instr *load = - nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform); - load->num_components = 3; - load->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0)); - nir_intrinsic_set_base(load, kernel_sysvals_start + - offsetof(struct brw_kernel_sysvals, num_work_groups)); - nir_intrinsic_set_range(load, 3 * 4); - nir_def_init(&load->instr, &load->def, 3, 32); - nir_builder_instr_insert(&b, &load->instr); - nir_def_rewrite_uses(&intrin->def, &load->def); - progress = true; - break; - } - - default: - break; - } - } - } - - if (progress) { - nir_metadata_preserve(impl, nir_metadata_block_index | - nir_metadata_dominance); - } else { - nir_metadata_preserve(impl, nir_metadata_all); - } - - return progress; -} - -bool -brw_kernel_from_spirv(struct brw_compiler *compiler, - struct disk_cache *disk_cache, - struct brw_kernel *kernel, - void *log_data, void *mem_ctx, - const uint32_t *spirv, size_t spirv_size, - const char *entrypoint_name, - char **error_str) -{ - const struct intel_device_info *devinfo = compiler->devinfo; - const nir_shader_compiler_options *nir_options = - compiler->nir_options[MESA_SHADER_KERNEL]; - - struct spirv_to_nir_options spirv_options = { - .environment = NIR_SPIRV_OPENCL, - .caps = { - .address = true, - .float16 = devinfo->ver >= 8, - .float64 = devinfo->ver >= 8, - .groups = true, - .image_write_without_format = true, - .int8 = devinfo->ver >= 8, - .int16 = devinfo->ver >= 8, - .int64 = devinfo->ver >= 8, - .int64_atomics = devinfo->ver >= 9, - .kernel = true, - .linkage = true, /* We receive linked kernel from clc */ - .float_controls = devinfo->ver >= 8, - .generic_pointers = true, - .storage_8bit = devinfo->ver >= 8, - .storage_16bit = devinfo->ver >= 8, - .subgroup_arithmetic = true, - .subgroup_basic = true, - .subgroup_ballot = true, - .subgroup_dispatch = true, - .subgroup_quad = true, - .subgroup_shuffle = true, - .subgroup_vote = true, - - .intel_subgroup_shuffle = true, - .intel_subgroup_buffer_block_io = true, - }, - .shared_addr_format = nir_address_format_62bit_generic, - .global_addr_format = nir_address_format_62bit_generic, - .temp_addr_format = nir_address_format_62bit_generic, - .constant_addr_format = nir_address_format_64bit_global, - }; - - spirv_options.clc_shader = load_clc_shader(compiler, disk_cache, - nir_options, &spirv_options); - if (spirv_options.clc_shader == NULL) { - fprintf(stderr, "ERROR: libclc shader missing." - " Consider installing the libclc package\n"); - abort(); - } - - assert(spirv_size % 4 == 0); - nir_shader *nir = - spirv_to_nir(spirv, spirv_size / 4, NULL, 0, MESA_SHADER_KERNEL, - entrypoint_name, &spirv_options, nir_options); - nir_validate_shader(nir, "after spirv_to_nir"); - nir_validate_ssa_dominance(nir, "after spirv_to_nir"); - ralloc_steal(mem_ctx, nir); - nir->info.name = ralloc_strdup(nir, entrypoint_name); - - if (INTEL_DEBUG(DEBUG_CS)) { - /* Re-index SSA defs so we print more sensible numbers. */ - nir_foreach_function_impl(impl, nir) { - nir_index_ssa_defs(impl); - } - - fprintf(stderr, "NIR (from SPIR-V) for kernel\n"); - nir_print_shader(nir, stderr); - } - - NIR_PASS_V(nir, implement_intel_builtins); - NIR_PASS_V(nir, nir_link_shader_functions, spirv_options.clc_shader); - - /* We have to lower away local constant initializers right before we - * inline functions. That way they get properly initialized at the top - * of the function and not at the top of its caller. - */ - NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp); - NIR_PASS_V(nir, nir_lower_returns); - NIR_PASS_V(nir, nir_inline_functions); - NIR_PASS_V(nir, nir_copy_prop); - NIR_PASS_V(nir, nir_opt_deref); - - /* Pick off the single entrypoint that we want */ - nir_remove_non_entrypoints(nir); - - /* Now that we've deleted all but the main function, we can go ahead and - * lower the rest of the constant initializers. We do this here so that - * nir_remove_dead_variables and split_per_member_structs below see the - * corresponding stores. - */ - NIR_PASS_V(nir, nir_lower_variable_initializers, ~0); - - /* LLVM loves take advantage of the fact that vec3s in OpenCL are 16B - * aligned and so it can just read/write them as vec4s. This results in a - * LOT of vec4->vec3 casts on loads and stores. One solution to this - * problem is to get rid of all vec3 variables. - */ - NIR_PASS_V(nir, nir_lower_vec3_to_vec4, - nir_var_shader_temp | nir_var_function_temp | - nir_var_mem_shared | nir_var_mem_global| - nir_var_mem_constant); - - /* We assign explicit types early so that the optimizer can take advantage - * of that information and hopefully get rid of some of our memcpys. - */ - NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, - nir_var_uniform | - nir_var_shader_temp | nir_var_function_temp | - nir_var_mem_shared | nir_var_mem_global, - glsl_get_cl_type_size_align); - - struct brw_nir_compiler_opts opts = {}; - brw_preprocess_nir(compiler, nir, &opts); - - int max_arg_idx = -1; - nir_foreach_uniform_variable(var, nir) { - assert(var->data.location < 256); - max_arg_idx = MAX2(max_arg_idx, var->data.location); - } - - kernel->args_size = nir->num_uniforms; - kernel->arg_count = max_arg_idx + 1; - - /* No bindings */ - struct brw_kernel_arg_desc *args = - rzalloc_array(mem_ctx, struct brw_kernel_arg_desc, kernel->arg_count); - kernel->args = args; - - nir_foreach_uniform_variable(var, nir) { - struct brw_kernel_arg_desc arg_desc = { - .offset = var->data.driver_location, - .size = glsl_get_explicit_size(var->type, false), - }; - assert(arg_desc.offset + arg_desc.size <= nir->num_uniforms); - - assert(var->data.location >= 0); - args[var->data.location] = arg_desc; - } - - NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_all, NULL); - - /* Lower again, this time after dead-variables to get more compact variable - * layouts. - */ - nir->global_mem_size = 0; - nir->scratch_size = 0; - nir->info.shared_size = 0; - NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, - nir_var_shader_temp | nir_var_function_temp | - nir_var_mem_shared | nir_var_mem_global | nir_var_mem_constant, - glsl_get_cl_type_size_align); - if (nir->constant_data_size > 0) { - assert(nir->constant_data == NULL); - nir->constant_data = rzalloc_size(nir, nir->constant_data_size); - nir_gather_explicit_io_initializers(nir, nir->constant_data, - nir->constant_data_size, - nir_var_mem_constant); - } - - if (INTEL_DEBUG(DEBUG_CS)) { - /* Re-index SSA defs so we print more sensible numbers. */ - nir_foreach_function_impl(impl, nir) { - nir_index_ssa_defs(impl); - } - - fprintf(stderr, "NIR (before I/O lowering) for kernel\n"); - nir_print_shader(nir, stderr); - } - - NIR_PASS_V(nir, nir_lower_memcpy); - - NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_constant, - nir_address_format_64bit_global); - - NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_uniform, - nir_address_format_32bit_offset_as_64bit); - - NIR_PASS_V(nir, nir_lower_explicit_io, - nir_var_shader_temp | nir_var_function_temp | - nir_var_mem_shared | nir_var_mem_global, - nir_address_format_62bit_generic); - - NIR_PASS_V(nir, nir_lower_convert_alu_types, NULL); - - NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics, devinfo, NULL); - NIR_PASS_V(nir, lower_kernel_intrinsics); - - struct brw_cs_prog_key key = { }; - - memset(&kernel->prog_data, 0, sizeof(kernel->prog_data)); - kernel->prog_data.base.nr_params = DIV_ROUND_UP(nir->num_uniforms, 4); - - struct brw_compile_cs_params params = { - .base = { - .nir = nir, - .stats = kernel->stats, - .log_data = log_data, - .mem_ctx = mem_ctx, - }, - .key = &key, - .prog_data = &kernel->prog_data, - }; - - kernel->code = brw_compile_cs(compiler, ¶ms); - - if (error_str) - *error_str = params.base.error_str; - - return kernel->code != NULL; -} - -static nir_def * -rebuild_value_from_store(struct util_dynarray *stores, - nir_def *value, unsigned read_offset) -{ - unsigned read_size = value->num_components * value->bit_size / 8; - - util_dynarray_foreach(stores, nir_intrinsic_instr *, _store) { - nir_intrinsic_instr *store = *_store; - - unsigned write_offset = nir_src_as_uint(store->src[1]); - unsigned write_size = nir_src_num_components(store->src[0]) * - nir_src_bit_size(store->src[0]) / 8; - if (write_offset <= read_offset && - (write_offset + write_size) >= (read_offset + read_size)) { - assert(nir_block_dominates(store->instr.block, value->parent_instr->block)); - assert(write_size == read_size); - return store->src[0].ssa; - } - } - unreachable("Matching scratch store not found"); -} - -/** - * Remove temporary variables stored to scratch to be then reloaded - * immediately. Remap the load to the store SSA value. - * - * This workaround is only meant to be applied to shaders in src/intel/shaders - * were we know there should be no issue. More complex cases might not work - * with this approach. - */ -static bool -nir_remove_llvm17_scratch(nir_shader *nir) -{ - struct util_dynarray scratch_stores; - void *mem_ctx = ralloc_context(NULL); - - util_dynarray_init(&scratch_stores, mem_ctx); - - nir_foreach_function_impl(func, nir) { - nir_foreach_block(block, func) { - nir_foreach_instr(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - - if (intrin->intrinsic != nir_intrinsic_store_scratch) - continue; - - nir_const_value *offset = nir_src_as_const_value(intrin->src[1]); - if (offset != NULL) { - util_dynarray_append(&scratch_stores, nir_intrinsic_instr *, intrin); - } - } - } - } - - bool progress = false; - if (util_dynarray_num_elements(&scratch_stores, nir_intrinsic_instr *) > 0) { - nir_foreach_function_impl(func, nir) { - nir_foreach_block(block, func) { - nir_foreach_instr_safe(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - - if (intrin->intrinsic != nir_intrinsic_load_scratch) - continue; - - nir_const_value *offset = nir_src_as_const_value(intrin->src[0]); - if (offset == NULL) - continue; - - nir_def_rewrite_uses(&intrin->def, - rebuild_value_from_store( - &scratch_stores, &intrin->def, - nir_src_as_uint(intrin->src[0]))); - nir_instr_remove(instr); - - progress = true; - } - } - } - } - - util_dynarray_foreach(&scratch_stores, nir_intrinsic_instr *, _store) { - nir_intrinsic_instr *store = *_store; - nir_instr_remove(&store->instr); - } - - /* Quick sanity check */ - assert(util_dynarray_num_elements(&scratch_stores, nir_intrinsic_instr *) == 0 || - progress); - - ralloc_free(mem_ctx); - - return progress; -} - -static void -cleanup_llvm17_scratch(nir_shader *nir) -{ - { - bool progress; - do { - progress = false; - NIR_PASS(progress, nir, nir_copy_prop); - NIR_PASS(progress, nir, nir_opt_dce); - NIR_PASS(progress, nir, nir_opt_constant_folding); - NIR_PASS(progress, nir, nir_opt_cse); - NIR_PASS(progress, nir, nir_opt_algebraic); - } while (progress); - } - - nir_remove_llvm17_scratch(nir); - - { - bool progress; - do { - progress = false; - NIR_PASS(progress, nir, nir_copy_prop); - NIR_PASS(progress, nir, nir_opt_dce); - NIR_PASS(progress, nir, nir_opt_constant_folding); - NIR_PASS(progress, nir, nir_opt_cse); - NIR_PASS(progress, nir, nir_opt_algebraic); - } while (progress); - } -} - -nir_shader * -brw_nir_from_spirv(void *mem_ctx, const uint32_t *spirv, size_t spirv_size, - bool llvm17_wa) -{ - struct spirv_to_nir_options spirv_options = { - .environment = NIR_SPIRV_OPENCL, - .caps = { - .address = true, - .groups = true, - .image_write_without_format = true, - .int8 = true, - .int16 = true, - .int64 = true, - .int64_atomics = true, - .kernel = true, - .linkage = true, /* We receive linked kernel from clc */ - .float_controls = true, - .generic_pointers = true, - .storage_8bit = true, - .storage_16bit = true, - .subgroup_arithmetic = true, - .subgroup_basic = true, - .subgroup_ballot = true, - .subgroup_dispatch = true, - .subgroup_quad = true, - .subgroup_shuffle = true, - .subgroup_vote = true, - - .intel_subgroup_shuffle = true, - .intel_subgroup_buffer_block_io = true, - }, - .shared_addr_format = nir_address_format_62bit_generic, - .global_addr_format = nir_address_format_62bit_generic, - .temp_addr_format = nir_address_format_62bit_generic, - .constant_addr_format = nir_address_format_64bit_global, - .create_library = true, - }; - - assert(spirv_size % 4 == 0); - nir_shader *nir = - spirv_to_nir(spirv, spirv_size / 4, NULL, 0, MESA_SHADER_KERNEL, - "library", &spirv_options, &brw_scalar_nir_options); - nir_validate_shader(nir, "after spirv_to_nir"); - nir_validate_ssa_dominance(nir, "after spirv_to_nir"); - ralloc_steal(mem_ctx, nir); - nir->info.name = ralloc_strdup(nir, "library"); - - if (INTEL_DEBUG(DEBUG_CS)) { - /* Re-index SSA defs so we print more sensible numbers. */ - nir_foreach_function_impl(impl, nir) { - nir_index_ssa_defs(impl); - } - - fprintf(stderr, "NIR (from SPIR-V) for kernel\n"); - nir_print_shader(nir, stderr); - } - - NIR_PASS_V(nir, implement_intel_builtins); - NIR_PASS_V(nir, nir_link_shader_functions, spirv_options.clc_shader); - - /* We have to lower away local constant initializers right before we - * inline functions. That way they get properly initialized at the top - * of the function and not at the top of its caller. - */ - NIR_PASS_V(nir, nir_lower_variable_initializers, ~(nir_var_shader_temp | - nir_var_function_temp)); - NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_uniform | nir_var_mem_ubo | - nir_var_mem_constant | nir_var_function_temp | nir_var_image, NULL); - { - bool progress; - do - { - progress = false; - NIR_PASS(progress, nir, nir_copy_prop); - NIR_PASS(progress, nir, nir_opt_copy_prop_vars); - NIR_PASS(progress, nir, nir_opt_deref); - NIR_PASS(progress, nir, nir_opt_dce); - NIR_PASS(progress, nir, nir_opt_undef); - NIR_PASS(progress, nir, nir_opt_constant_folding); - NIR_PASS(progress, nir, nir_opt_cse); - NIR_PASS(progress, nir, nir_lower_vars_to_ssa); - NIR_PASS(progress, nir, nir_opt_algebraic); - } while (progress); - } - - NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp); - NIR_PASS_V(nir, nir_lower_returns); - NIR_PASS_V(nir, nir_inline_functions); - - assert(nir->scratch_size == 0); - NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_function_temp, glsl_get_cl_type_size_align); - - { - bool progress; - do - { - progress = false; - NIR_PASS(progress, nir, nir_copy_prop); - NIR_PASS(progress, nir, nir_opt_copy_prop_vars); - NIR_PASS(progress, nir, nir_opt_deref); - NIR_PASS(progress, nir, nir_opt_dce); - NIR_PASS(progress, nir, nir_opt_undef); - NIR_PASS(progress, nir, nir_opt_constant_folding); - NIR_PASS(progress, nir, nir_opt_cse); - NIR_PASS(progress, nir, nir_split_var_copies); - NIR_PASS(progress, nir, nir_lower_var_copies); - NIR_PASS(progress, nir, nir_lower_vars_to_ssa); - NIR_PASS(progress, nir, nir_opt_algebraic); - NIR_PASS(progress, nir, nir_opt_if, nir_opt_if_optimize_phi_true_false); - NIR_PASS(progress, nir, nir_opt_dead_cf); - NIR_PASS(progress, nir, nir_opt_remove_phis); - NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true); - NIR_PASS(progress, nir, nir_lower_vec3_to_vec4, nir_var_mem_generic | nir_var_uniform); - NIR_PASS(progress, nir, nir_opt_memcpy); - } while (progress); - } - - NIR_PASS_V(nir, nir_scale_fdiv); - - NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_uniform | nir_var_mem_ubo | - nir_var_mem_constant | nir_var_function_temp | nir_var_image, NULL); - - - NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_mem_shared | nir_var_function_temp, NULL); - - nir->scratch_size = 0; - NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, - nir_var_mem_shared | nir_var_function_temp | nir_var_shader_temp | - nir_var_mem_global | nir_var_mem_constant, - glsl_get_cl_type_size_align); - - // Lower memcpy - needs to wait until types are sized - { - bool progress; - do { - progress = false; - NIR_PASS(progress, nir, nir_opt_memcpy); - NIR_PASS(progress, nir, nir_copy_prop); - NIR_PASS(progress, nir, nir_opt_copy_prop_vars); - NIR_PASS(progress, nir, nir_opt_deref); - NIR_PASS(progress, nir, nir_opt_dce); - NIR_PASS(progress, nir, nir_split_var_copies); - NIR_PASS(progress, nir, nir_lower_var_copies); - NIR_PASS(progress, nir, nir_lower_vars_to_ssa); - NIR_PASS(progress, nir, nir_opt_constant_folding); - NIR_PASS(progress, nir, nir_opt_cse); - } while (progress); - } - NIR_PASS_V(nir, nir_lower_memcpy); - - NIR_PASS_V(nir, nir_lower_explicit_io, - nir_var_mem_shared | nir_var_function_temp | nir_var_shader_temp | nir_var_uniform, - nir_address_format_32bit_offset_as_64bit); - - NIR_PASS_V(nir, nir_lower_system_values); - - /* Hopefully we can drop this once lower_vars_to_ssa has improved to not - * lower everything to scratch. - */ - if (llvm17_wa) - cleanup_llvm17_scratch(nir); - - /* Lower again, this time after dead-variables to get more compact variable - * layouts. - */ - nir->global_mem_size = 0; - nir->scratch_size = 0; - nir->info.shared_size = 0; - NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, - nir_var_mem_shared | nir_var_mem_global | nir_var_mem_constant, - glsl_get_cl_type_size_align); - if (nir->constant_data_size > 0) { - assert(nir->constant_data == NULL); - nir->constant_data = rzalloc_size(nir, nir->constant_data_size); - nir_gather_explicit_io_initializers(nir, nir->constant_data, - nir->constant_data_size, - nir_var_mem_constant); - } - - NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_constant, - nir_address_format_64bit_global); - - NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_uniform, - nir_address_format_32bit_offset_as_64bit); - - NIR_PASS_V(nir, nir_lower_explicit_io, - nir_var_shader_temp | nir_var_function_temp | - nir_var_mem_shared | nir_var_mem_global, - nir_address_format_62bit_generic); - - if (INTEL_DEBUG(DEBUG_CS)) { - /* Re-index SSA defs so we print more sensible numbers. */ - nir_foreach_function_impl(impl, nir) { - nir_index_ssa_defs(impl); - } - - fprintf(stderr, "NIR (before I/O lowering) for kernel\n"); - nir_print_shader(nir, stderr); - } - - return nir; -} diff --git a/src/intel/compiler/elk/brw_kernel.h b/src/intel/compiler/elk/brw_kernel.h deleted file mode 100644 index fb1289872d5..00000000000 --- a/src/intel/compiler/elk/brw_kernel.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright © 2020 Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef BRW_KERNEL_H -#define BRW_KERNEL_H - -#include "brw_compiler.h" - -struct disk_cache; - -#ifdef __cplusplus -extern "C" { -#endif - -/** Software interface for system values in kernels - * - * These are intended to go at the start of the kernel argument buffer. - */ -struct brw_kernel_sysvals { - uint32_t num_work_groups[3]; - uint32_t pad[5]; -}; - -struct brw_kernel_arg_desc { - uint16_t offset; - uint16_t size; -}; - -struct brw_kernel { - struct brw_cs_prog_data prog_data; - - struct brw_compile_stats stats[3]; - - uint16_t args_size; - uint16_t arg_count; - const struct brw_kernel_arg_desc *args; - - const void *code; -}; - -bool -brw_kernel_from_spirv(struct brw_compiler *compiler, - struct disk_cache *disk_cache, - struct brw_kernel *kernel, - void *log_data, void *mem_ctx, - const uint32_t *spirv, size_t spirv_size, - const char *entrypoint_name, - char **error_str); - -nir_shader * -brw_nir_from_spirv(void *mem_ctx, const uint32_t *spirv, size_t spirv_size, - bool llvm17_wa); - -#ifdef __cplusplus -} /* extern "C" */ -#endif - -#endif /* BRW_KERNEL_H */ diff --git a/src/intel/compiler/elk/brw_mesh.cpp b/src/intel/compiler/elk/brw_mesh.cpp deleted file mode 100644 index 66a02b2275e..00000000000 --- a/src/intel/compiler/elk/brw_mesh.cpp +++ /dev/null @@ -1,1606 +0,0 @@ -/* - * Copyright © 2021 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include -#include -#include "brw_compiler.h" -#include "brw_fs.h" -#include "brw_nir.h" -#include "brw_private.h" -#include "compiler/nir/nir_builder.h" -#include "dev/intel_debug.h" - -#include - -using namespace brw; - -static bool -brw_nir_lower_load_uniforms_filter(const nir_instr *instr, - UNUSED const void *data) -{ - if (instr->type != nir_instr_type_intrinsic) - return false; - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - return intrin->intrinsic == nir_intrinsic_load_uniform; -} - -static nir_def * -brw_nir_lower_load_uniforms_impl(nir_builder *b, nir_instr *instr, - UNUSED void *data) -{ - assert(instr->type == nir_instr_type_intrinsic); - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - assert(intrin->intrinsic == nir_intrinsic_load_uniform); - - /* Read the first few 32-bit scalars from InlineData. */ - if (nir_src_is_const(intrin->src[0]) && - intrin->def.bit_size == 32 && - intrin->def.num_components == 1) { - unsigned off = nir_intrinsic_base(intrin) + nir_src_as_uint(intrin->src[0]); - unsigned off_dw = off / 4; - if (off % 4 == 0 && off_dw < BRW_TASK_MESH_PUSH_CONSTANTS_SIZE_DW) { - off_dw += BRW_TASK_MESH_PUSH_CONSTANTS_START_DW; - return nir_load_mesh_inline_data_intel(b, 32, off_dw); - } - } - - return brw_nir_load_global_const(b, intrin, - nir_load_mesh_inline_data_intel(b, 64, 0), 0); -} - -static bool -brw_nir_lower_load_uniforms(nir_shader *nir) -{ - return nir_shader_lower_instructions(nir, brw_nir_lower_load_uniforms_filter, - brw_nir_lower_load_uniforms_impl, NULL); -} - -static inline int -type_size_scalar_dwords(const struct glsl_type *type, bool bindless) -{ - return glsl_count_dword_slots(type, bindless); -} - -/* TODO(mesh): Make this a common function. */ -static void -shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align) -{ - assert(glsl_type_is_vector_or_scalar(type)); - - uint32_t comp_size = glsl_type_is_boolean(type) - ? 4 : glsl_get_bit_size(type) / 8; - unsigned length = glsl_get_vector_elements(type); - *size = comp_size * length, - *align = comp_size * (length == 3 ? 4 : length); -} - -static bool -brw_nir_lower_launch_mesh_workgroups_instr(nir_builder *b, - nir_intrinsic_instr *intrin, - void *data) -{ - if (intrin->intrinsic != nir_intrinsic_launch_mesh_workgroups) - return false; - - b->cursor = nir_before_instr(&intrin->instr); - - nir_def *local_invocation_index = nir_load_local_invocation_index(b); - - /* Make sure that the mesh workgroup size is taken from the first invocation - * (nir_intrinsic_launch_mesh_workgroups requirement) - */ - nir_def *cmp = nir_ieq_imm(b, local_invocation_index, 0); - nir_if *if_stmt = nir_push_if(b, cmp); - { - /* TUE header contains 4 words: - * - * - Word 0 for Task Count. - * - * - Words 1-3 used for "Dispatch Dimensions" feature, to allow mapping a - * 3D dispatch into the 1D dispatch supported by HW. - */ - nir_def *x = nir_channel(b, intrin->src[0].ssa, 0); - nir_def *y = nir_channel(b, intrin->src[0].ssa, 1); - nir_def *z = nir_channel(b, intrin->src[0].ssa, 2); - nir_def *task_count = nir_imul(b, x, nir_imul(b, y, z)); - nir_def *tue_header = nir_vec4(b, task_count, x, y, z); - nir_store_task_payload(b, tue_header, nir_imm_int(b, 0)); - } - nir_pop_if(b, if_stmt); - - nir_instr_remove(&intrin->instr); - - return true; -} - -static bool -brw_nir_lower_launch_mesh_workgroups(nir_shader *nir) -{ - return nir_shader_intrinsics_pass(nir, - brw_nir_lower_launch_mesh_workgroups_instr, - nir_metadata_none, - NULL); -} - -static void -brw_nir_lower_tue_outputs(nir_shader *nir, brw_tue_map *map) -{ - memset(map, 0, sizeof(*map)); - - NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out, - type_size_scalar_dwords, nir_lower_io_lower_64bit_to_32); - - /* From bspec: "It is suggested that SW reserve the 16 bytes following the - * TUE Header, and therefore start the SW-defined data structure at 32B - * alignment. This allows the TUE Header to always be written as 32 bytes - * with 32B alignment, the most optimal write performance case." - */ - map->per_task_data_start_dw = 8; - - /* Lowering to explicit types will start offsets from task_payload_size, so - * set it to start after the header. - */ - nir->info.task_payload_size = map->per_task_data_start_dw * 4; - NIR_PASS(_, nir, nir_lower_vars_to_explicit_types, - nir_var_mem_task_payload, shared_type_info); - NIR_PASS(_, nir, nir_lower_explicit_io, - nir_var_mem_task_payload, nir_address_format_32bit_offset); - - map->size_dw = ALIGN(DIV_ROUND_UP(nir->info.task_payload_size, 4), 8); -} - -static void -brw_print_tue_map(FILE *fp, const struct brw_tue_map *map) -{ - fprintf(fp, "TUE (%d dwords)\n\n", map->size_dw); -} - -static bool -brw_nir_adjust_task_payload_offsets_instr(struct nir_builder *b, - nir_intrinsic_instr *intrin, - void *data) -{ - switch (intrin->intrinsic) { - case nir_intrinsic_store_task_payload: - case nir_intrinsic_load_task_payload: { - nir_src *offset_src = nir_get_io_offset_src(intrin); - - if (nir_src_is_const(*offset_src)) - assert(nir_src_as_uint(*offset_src) % 4 == 0); - - b->cursor = nir_before_instr(&intrin->instr); - - /* Regular I/O uses dwords while explicit I/O used for task payload uses - * bytes. Normalize it to dwords. - * - * TODO(mesh): Figure out how to handle 8-bit, 16-bit. - */ - - nir_def *offset = nir_ishr_imm(b, offset_src->ssa, 2); - nir_src_rewrite(offset_src, offset); - - unsigned base = nir_intrinsic_base(intrin); - assert(base % 4 == 0); - nir_intrinsic_set_base(intrin, base / 4); - - return true; - } - - default: - return false; - } -} - -static bool -brw_nir_adjust_task_payload_offsets(nir_shader *nir) -{ - return nir_shader_intrinsics_pass(nir, - brw_nir_adjust_task_payload_offsets_instr, - nir_metadata_block_index | - nir_metadata_dominance, - NULL); -} - -void -brw_nir_adjust_payload(nir_shader *shader) -{ - /* Adjustment of task payload offsets must be performed *after* last pass - * which interprets them as bytes, because it changes their unit. - */ - bool adjusted = false; - NIR_PASS(adjusted, shader, brw_nir_adjust_task_payload_offsets); - if (adjusted) /* clean up the mess created by offset adjustments */ - NIR_PASS(_, shader, nir_opt_constant_folding); -} - -static bool -brw_nir_align_launch_mesh_workgroups_instr(nir_builder *b, - nir_intrinsic_instr *intrin, - void *data) -{ - if (intrin->intrinsic != nir_intrinsic_launch_mesh_workgroups) - return false; - - /* nir_lower_task_shader uses "range" as task payload size. */ - unsigned range = nir_intrinsic_range(intrin); - /* This will avoid special case in nir_lower_task_shader dealing with - * not vec4-aligned payload when payload_in_shared workaround is enabled. - */ - nir_intrinsic_set_range(intrin, ALIGN(range, 16)); - - return true; -} - -static bool -brw_nir_align_launch_mesh_workgroups(nir_shader *nir) -{ - return nir_shader_intrinsics_pass(nir, - brw_nir_align_launch_mesh_workgroups_instr, - nir_metadata_block_index | - nir_metadata_dominance, - NULL); -} - -const unsigned * -brw_compile_task(const struct brw_compiler *compiler, - struct brw_compile_task_params *params) -{ - struct nir_shader *nir = params->base.nir; - const struct brw_task_prog_key *key = params->key; - struct brw_task_prog_data *prog_data = params->prog_data; - const bool debug_enabled = brw_should_print_shader(nir, DEBUG_TASK); - - brw_nir_lower_tue_outputs(nir, &prog_data->map); - - NIR_PASS(_, nir, brw_nir_align_launch_mesh_workgroups); - - nir_lower_task_shader_options lower_ts_opt = { - .payload_to_shared_for_atomics = true, - .payload_to_shared_for_small_types = true, - /* The actual payload data starts after the TUE header and padding, - * so skip those when copying. - */ - .payload_offset_in_bytes = prog_data->map.per_task_data_start_dw * 4, - }; - NIR_PASS(_, nir, nir_lower_task_shader, lower_ts_opt); - - NIR_PASS(_, nir, brw_nir_lower_launch_mesh_workgroups); - - prog_data->base.base.stage = MESA_SHADER_TASK; - prog_data->base.base.total_shared = nir->info.shared_size; - prog_data->base.base.total_scratch = 0; - - prog_data->base.local_size[0] = nir->info.workgroup_size[0]; - prog_data->base.local_size[1] = nir->info.workgroup_size[1]; - prog_data->base.local_size[2] = nir->info.workgroup_size[2]; - - prog_data->uses_drawid = - BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); - - brw_simd_selection_state simd_state{ - .devinfo = compiler->devinfo, - .prog_data = &prog_data->base, - .required_width = brw_required_dispatch_width(&nir->info), - }; - - std::unique_ptr v[3]; - - for (unsigned simd = 0; simd < 3; simd++) { - if (!brw_simd_should_compile(simd_state, simd)) - continue; - - const unsigned dispatch_width = 8 << simd; - - nir_shader *shader = nir_shader_clone(params->base.mem_ctx, nir); - brw_nir_apply_key(shader, compiler, &key->base, dispatch_width); - - NIR_PASS(_, shader, brw_nir_lower_load_uniforms); - NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width); - - brw_postprocess_nir(shader, compiler, debug_enabled, - key->base.robust_flags); - - v[simd] = std::make_unique(compiler, ¶ms->base, - &key->base, - &prog_data->base.base, - shader, dispatch_width, - params->base.stats != NULL, - debug_enabled); - - if (prog_data->base.prog_mask) { - unsigned first = ffs(prog_data->base.prog_mask) - 1; - v[simd]->import_uniforms(v[first].get()); - } - - const bool allow_spilling = !brw_simd_any_compiled(simd_state); - if (v[simd]->run_task(allow_spilling)) - brw_simd_mark_compiled(simd_state, simd, v[simd]->spilled_any_registers); - else - simd_state.error[simd] = ralloc_strdup(params->base.mem_ctx, v[simd]->fail_msg); - } - - int selected_simd = brw_simd_select(simd_state); - if (selected_simd < 0) { - params->base.error_str = - ralloc_asprintf(params->base.mem_ctx, - "Can't compile shader: " - "SIMD8 '%s', SIMD16 '%s' and SIMD32 '%s'.\n", - simd_state.error[0], simd_state.error[1], - simd_state.error[2]); - return NULL; - } - - fs_visitor *selected = v[selected_simd].get(); - prog_data->base.prog_mask = 1 << selected_simd; - - if (unlikely(debug_enabled)) { - fprintf(stderr, "Task Output "); - brw_print_tue_map(stderr, &prog_data->map); - } - - fs_generator g(compiler, ¶ms->base, &prog_data->base.base, - false, MESA_SHADER_TASK); - if (unlikely(debug_enabled)) { - g.enable_debug(ralloc_asprintf(params->base.mem_ctx, - "%s task shader %s", - nir->info.label ? nir->info.label - : "unnamed", - nir->info.name)); - } - - g.generate_code(selected->cfg, selected->dispatch_width, selected->shader_stats, - selected->performance_analysis.require(), params->base.stats); - g.add_const_data(nir->constant_data, nir->constant_data_size); - return g.get_assembly(); -} - -static void -brw_nir_lower_tue_inputs(nir_shader *nir, const brw_tue_map *map) -{ - if (!map) - return; - - nir->info.task_payload_size = map->per_task_data_start_dw * 4; - - bool progress = false; - - NIR_PASS(progress, nir, nir_lower_vars_to_explicit_types, - nir_var_mem_task_payload, shared_type_info); - - if (progress) { - /* The types for Task Output and Mesh Input should match, so their sizes - * should also match. - */ - assert(map->size_dw == ALIGN(DIV_ROUND_UP(nir->info.task_payload_size, 4), 8)); - } else { - /* Mesh doesn't read any input, to make it clearer set the - * task_payload_size to zero instead of keeping an incomplete size that - * just includes the header. - */ - nir->info.task_payload_size = 0; - } - - NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_task_payload, - nir_address_format_32bit_offset); -} - -/* Attribute types. Flat attributes have to be a separate class because - * flat and interpolated attributes can't share the same vec4 slot - * (see 3DSTATE_SBE.ConstantInterpolationEnable). - */ -enum { - PRIM, /* per primitive */ - VERT, /* per vertex interpolated */ - VERT_FLAT, /* per vertex flat */ -}; - -struct attr_desc { - int location; - const struct glsl_type *type; - unsigned dwords; - unsigned slots; -}; - -struct attr_type_info { - /* order of attributes, negative values are holes */ - std::list *order; - - /* attributes after which there's hole of size equal to array index */ - std::list holes[5]; -}; - -static void -brw_mue_assign_position(const struct attr_desc *attr, - struct brw_mue_map *map, - unsigned start_dw) -{ - bool is_array = glsl_type_is_array(attr->type); - int location = attr->location; - unsigned remaining = attr->dwords; - - for (unsigned slot = 0; slot < attr->slots; ++slot) { - map->start_dw[location + slot] = start_dw; - - unsigned sz; - - if (is_array) { - assert(attr->dwords % attr->slots == 0); - sz = attr->dwords / attr->slots; - } else { - sz = MIN2(remaining, 4); - } - - map->len_dw[location + slot] = sz; - start_dw += sz; - remaining -= sz; - } -} - -static nir_variable * -brw_nir_find_complete_variable_with_location(nir_shader *shader, - nir_variable_mode mode, - int location) -{ - nir_variable *best_var = NULL; - unsigned last_size = 0; - - nir_foreach_variable_with_modes(var, shader, mode) { - if (var->data.location != location) - continue; - - unsigned new_size = glsl_count_dword_slots(var->type, false); - if (new_size > last_size) { - best_var = var; - last_size = new_size; - } - } - - return best_var; -} - -static unsigned -brw_sum_size(const std::list &orders) -{ - unsigned sz = 0; - for (auto it = orders.cbegin(); it != orders.cend(); ++it) - sz += (*it).dwords; - return sz; -} - -/* Finds order of outputs which require minimum size, without splitting - * of URB read/write messages (which operate on vec4-aligned memory). - */ -static void -brw_compute_mue_layout(const struct brw_compiler *compiler, - std::list *orders, - uint64_t outputs_written, - struct nir_shader *nir, - bool *pack_prim_data_into_header, - bool *pack_vert_data_into_header) -{ - const struct shader_info *info = &nir->info; - - struct attr_type_info data[3]; - - if ((compiler->mesh.mue_header_packing & 1) == 0) - *pack_prim_data_into_header = false; - if ((compiler->mesh.mue_header_packing & 2) == 0) - *pack_vert_data_into_header = false; - - for (unsigned i = PRIM; i <= VERT_FLAT; ++i) - data[i].order = &orders[i]; - - /* If packing into header is enabled, add a hole of size 4 and add - * a virtual location to keep the algorithm happy (it expects holes - * to be preceded by some location). We'll remove those virtual - * locations at the end. - */ - const gl_varying_slot virtual_header_location = VARYING_SLOT_POS; - assert((outputs_written & BITFIELD64_BIT(virtual_header_location)) == 0); - - struct attr_desc d; - d.location = virtual_header_location; - d.type = NULL; - d.dwords = 0; - d.slots = 0; - - struct attr_desc h; - h.location = -1; - h.type = NULL; - h.dwords = 4; - h.slots = 0; - - if (*pack_prim_data_into_header) { - orders[PRIM].push_back(d); - orders[PRIM].push_back(h); - data[PRIM].holes[4].push_back(virtual_header_location); - } - - if (*pack_vert_data_into_header) { - orders[VERT].push_back(d); - orders[VERT].push_back(h); - data[VERT].holes[4].push_back(virtual_header_location); - } - - u_foreach_bit64(location, outputs_written) { - if ((BITFIELD64_BIT(location) & outputs_written) == 0) - continue; - - /* At this point there are both complete and split variables as - * outputs. We need the complete variable to compute the required - * size. - */ - nir_variable *var = - brw_nir_find_complete_variable_with_location(nir, - nir_var_shader_out, - location); - - d.location = location; - d.type = brw_nir_get_var_type(nir, var); - d.dwords = glsl_count_dword_slots(d.type, false); - d.slots = glsl_count_attribute_slots(d.type, false); - - struct attr_type_info *type_data; - - if (BITFIELD64_BIT(location) & info->per_primitive_outputs) - type_data = &data[PRIM]; - else if (var->data.interpolation == INTERP_MODE_FLAT) - type_data = &data[VERT_FLAT]; - else - type_data = &data[VERT]; - - std::list *order = type_data->order; - std::list *holes = type_data->holes; - - outputs_written &= ~BITFIELD64_RANGE(location, d.slots); - - /* special case to use hole of size 4 */ - if (d.dwords == 4 && !holes[4].empty()) { - holes[4].pop_back(); - - assert(order->front().location == virtual_header_location); - order->pop_front(); - - assert(order->front().location == -1); - assert(order->front().dwords == 4); - order->front() = d; - - continue; - } - - int mod = d.dwords % 4; - if (mod == 0) { - order->push_back(d); - continue; - } - - h.location = -1; - h.type = NULL; - h.dwords = 4 - mod; - h.slots = 0; - - if (!compiler->mesh.mue_compaction) { - order->push_back(d); - order->push_back(h); - continue; - } - - if (d.dwords > 4) { - order->push_back(d); - order->push_back(h); - holes[h.dwords].push_back(location); - continue; - } - - assert(d.dwords < 4); - - unsigned found = 0; - /* try to find the smallest hole big enough to hold this attribute */ - for (unsigned sz = d.dwords; sz <= 4; sz++){ - if (!holes[sz].empty()) { - found = sz; - break; - } - } - - /* append at the end if not found */ - if (found == 0) { - order->push_back(d); - order->push_back(h); - holes[h.dwords].push_back(location); - - continue; - } - - assert(found <= 4); - assert(!holes[found].empty()); - int after_loc = holes[found].back(); - holes[found].pop_back(); - - bool inserted_back = false; - - for (auto it = order->begin(); it != order->end(); ++it) { - if ((*it).location != after_loc) - continue; - - ++it; - /* must be a hole */ - assert((*it).location < 0); - /* and it must be big enough */ - assert(d.dwords <= (*it).dwords); - - if (d.dwords == (*it).dwords) { - /* exact size, just replace */ - *it = d; - } else { - /* inexact size, shrink hole */ - (*it).dwords -= d.dwords; - /* and insert new attribute before it */ - order->insert(it, d); - - /* Insert shrunk hole in a spot so that the order of attributes - * is preserved. - */ - std::list &hole_list = holes[(*it).dwords]; - std::list::iterator insert_before = hole_list.end(); - - for (auto it2 = hole_list.begin(); it2 != hole_list.end(); ++it2) { - if ((*it2) >= (int)location) { - insert_before = it2; - break; - } - } - - hole_list.insert(insert_before, location); - } - - inserted_back = true; - break; - } - - assert(inserted_back); - } - - if (*pack_prim_data_into_header) { - if (orders[PRIM].front().location == virtual_header_location) - orders[PRIM].pop_front(); - - if (!data[PRIM].holes[4].empty()) { - *pack_prim_data_into_header = false; - - assert(orders[PRIM].front().location == -1); - assert(orders[PRIM].front().dwords == 4); - orders[PRIM].pop_front(); - } - - if (*pack_prim_data_into_header) { - unsigned sz = brw_sum_size(orders[PRIM]); - - if (sz % 8 == 0 || sz % 8 > 4) - *pack_prim_data_into_header = false; - } - } - - if (*pack_vert_data_into_header) { - if (orders[VERT].front().location == virtual_header_location) - orders[VERT].pop_front(); - - if (!data[VERT].holes[4].empty()) { - *pack_vert_data_into_header = false; - - assert(orders[VERT].front().location == -1); - assert(orders[VERT].front().dwords == 4); - orders[VERT].pop_front(); - } - - if (*pack_vert_data_into_header) { - unsigned sz = brw_sum_size(orders[VERT]) + - brw_sum_size(orders[VERT_FLAT]); - - if (sz % 8 == 0 || sz % 8 > 4) - *pack_vert_data_into_header = false; - } - } - - - if (INTEL_DEBUG(DEBUG_MESH)) { - fprintf(stderr, "MUE attribute order:\n"); - for (unsigned i = PRIM; i <= VERT_FLAT; ++i) { - if (!orders[i].empty()) - fprintf(stderr, "%d: ", i); - for (auto it = orders[i].cbegin(); it != orders[i].cend(); ++it) { - fprintf(stderr, "%d(%d) ", (*it).location, (*it).dwords); - } - if (!orders[i].empty()) - fprintf(stderr, "\n"); - } - } -} - -/* Mesh URB Entry consists of an initial section - * - * - Primitive Count - * - Primitive Indices (from 0 to Max-1) - * - Padding to 32B if needed - * - * optionally followed by a section for per-primitive data, - * in which each primitive (from 0 to Max-1) gets - * - * - Primitive Header (e.g. ViewportIndex) - * - Primitive Custom Attributes - * - * then followed by a section for per-vertex data - * - * - Vertex Header (e.g. Position) - * - Vertex Custom Attributes - * - * Each per-element section has a pitch and a starting offset. All the - * individual attributes offsets in start_dw are considering the first entry - * of the section (i.e. where the Position for first vertex, or ViewportIndex - * for first primitive). Attributes for other elements are calculated using - * the pitch. - */ -static void -brw_compute_mue_map(const struct brw_compiler *compiler, - struct nir_shader *nir, struct brw_mue_map *map, - enum brw_mesh_index_format index_format, bool compact_mue) -{ - memset(map, 0, sizeof(*map)); - - memset(&map->start_dw[0], -1, sizeof(map->start_dw)); - memset(&map->len_dw[0], 0, sizeof(map->len_dw)); - - unsigned vertices_per_primitive = - mesa_vertices_per_prim(nir->info.mesh.primitive_type); - - map->max_primitives = nir->info.mesh.max_primitives_out; - map->max_vertices = nir->info.mesh.max_vertices_out; - - uint64_t outputs_written = nir->info.outputs_written; - - /* One dword for primitives count then K extra dwords for each primitive. */ - switch (index_format) { - case BRW_INDEX_FORMAT_U32: - map->per_primitive_indices_dw = vertices_per_primitive; - break; - case BRW_INDEX_FORMAT_U888X: - map->per_primitive_indices_dw = 1; - break; - default: - unreachable("invalid index format"); - } - - map->per_primitive_start_dw = ALIGN(map->per_primitive_indices_dw * - map->max_primitives + 1, 8); - - /* Assign initial section. */ - if (BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT) & outputs_written) { - map->start_dw[VARYING_SLOT_PRIMITIVE_COUNT] = 0; - map->len_dw[VARYING_SLOT_PRIMITIVE_COUNT] = 1; - outputs_written &= ~BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT); - } - if (BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES) & outputs_written) { - map->start_dw[VARYING_SLOT_PRIMITIVE_INDICES] = 1; - map->len_dw[VARYING_SLOT_PRIMITIVE_INDICES] = - map->per_primitive_indices_dw * map->max_primitives; - outputs_written &= ~BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES); - } - - const uint64_t per_primitive_header_bits = - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE) | - BITFIELD64_BIT(VARYING_SLOT_LAYER) | - BITFIELD64_BIT(VARYING_SLOT_VIEWPORT) | - BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE); - - const uint64_t per_vertex_header_bits = - BITFIELD64_BIT(VARYING_SLOT_PSIZ) | - BITFIELD64_BIT(VARYING_SLOT_POS) | - BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0) | - BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1); - - std::list orders[3]; - uint64_t regular_outputs = outputs_written & - ~(per_primitive_header_bits | per_vertex_header_bits); - - /* packing into prim header is possible only if prim header is present */ - map->user_data_in_primitive_header = compact_mue && - (outputs_written & per_primitive_header_bits) != 0; - - /* Packing into vert header is always possible, but we allow it only - * if full vec4 is available (so point size is not used) and there's - * nothing between it and normal vertex data (so no clip distances). - */ - map->user_data_in_vertex_header = compact_mue && - (outputs_written & per_vertex_header_bits) == - BITFIELD64_BIT(VARYING_SLOT_POS); - - if (outputs_written & per_primitive_header_bits) { - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE)) { - map->start_dw[VARYING_SLOT_PRIMITIVE_SHADING_RATE] = - map->per_primitive_start_dw + 0; - map->len_dw[VARYING_SLOT_PRIMITIVE_SHADING_RATE] = 1; - } - - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_LAYER)) { - map->start_dw[VARYING_SLOT_LAYER] = - map->per_primitive_start_dw + 1; /* RTAIndex */ - map->len_dw[VARYING_SLOT_LAYER] = 1; - } - - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_VIEWPORT)) { - map->start_dw[VARYING_SLOT_VIEWPORT] = - map->per_primitive_start_dw + 2; - map->len_dw[VARYING_SLOT_VIEWPORT] = 1; - } - - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE)) { - map->start_dw[VARYING_SLOT_CULL_PRIMITIVE] = - map->per_primitive_start_dw + 3; - map->len_dw[VARYING_SLOT_CULL_PRIMITIVE] = 1; - } - - map->per_primitive_header_size_dw = 8; - outputs_written &= ~per_primitive_header_bits; - } else { - map->per_primitive_header_size_dw = 0; - } - - map->per_primitive_data_size_dw = 0; - - /* For fast linked libraries, we can't pack the MUE, as the fragment shader - * will be compiled without access to the MUE map and won't be able to find - * out where everything is. - * Instead, keep doing things as we did before the packing, just laying out - * everything in varying order, which is how the FS will expect them. - */ - if (compact_mue) { - brw_compute_mue_layout(compiler, orders, regular_outputs, nir, - &map->user_data_in_primitive_header, - &map->user_data_in_vertex_header); - - unsigned start_dw = map->per_primitive_start_dw; - if (map->user_data_in_primitive_header) - start_dw += 4; /* first 4 dwords are used */ - else - start_dw += map->per_primitive_header_size_dw; - unsigned header_used_dw = 0; - - for (auto it = orders[PRIM].cbegin(); it != orders[PRIM].cend(); ++it) { - int location = (*it).location; - if (location < 0) { - start_dw += (*it).dwords; - if (map->user_data_in_primitive_header && header_used_dw < 4) - header_used_dw += (*it).dwords; - else - map->per_primitive_data_size_dw += (*it).dwords; - assert(header_used_dw <= 4); - continue; - } - - assert(map->start_dw[location] == -1); - - assert(location == VARYING_SLOT_PRIMITIVE_ID || - location >= VARYING_SLOT_VAR0); - - brw_mue_assign_position(&*it, map, start_dw); - - start_dw += (*it).dwords; - if (map->user_data_in_primitive_header && header_used_dw < 4) - header_used_dw += (*it).dwords; - else - map->per_primitive_data_size_dw += (*it).dwords; - assert(header_used_dw <= 4); - outputs_written &= ~BITFIELD64_RANGE(location, (*it).slots); - } - } else { - unsigned start_dw = map->per_primitive_start_dw + - map->per_primitive_header_size_dw; - - uint64_t per_prim_outputs = outputs_written & nir->info.per_primitive_outputs; - while (per_prim_outputs) { - uint64_t location = ffsll(per_prim_outputs) - 1; - - assert(map->start_dw[location] == -1); - assert(location == VARYING_SLOT_PRIMITIVE_ID || - location >= VARYING_SLOT_VAR0); - - nir_variable *var = - brw_nir_find_complete_variable_with_location(nir, - nir_var_shader_out, - location); - struct attr_desc d; - d.location = location; - d.type = brw_nir_get_var_type(nir, var); - d.dwords = glsl_count_dword_slots(d.type, false); - d.slots = glsl_count_attribute_slots(d.type, false); - - brw_mue_assign_position(&d, map, start_dw); - - map->per_primitive_data_size_dw += ALIGN(d.dwords, 4); - start_dw += ALIGN(d.dwords, 4); - - per_prim_outputs &= ~BITFIELD64_RANGE(location, d.slots); - } - } - - map->per_primitive_pitch_dw = ALIGN(map->per_primitive_header_size_dw + - map->per_primitive_data_size_dw, 8); - - map->per_vertex_start_dw = ALIGN(map->per_primitive_start_dw + - map->per_primitive_pitch_dw * - map->max_primitives, 8); - - /* TODO(mesh): Multiview. */ - unsigned fixed_header_size = 8; - map->per_vertex_header_size_dw = ALIGN(fixed_header_size + - nir->info.clip_distance_array_size + - nir->info.cull_distance_array_size, 8); - - if (outputs_written & per_vertex_header_bits) { - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) { - map->start_dw[VARYING_SLOT_PSIZ] = map->per_vertex_start_dw + 3; - map->len_dw[VARYING_SLOT_PSIZ] = 1; - } - - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_POS)) { - map->start_dw[VARYING_SLOT_POS] = map->per_vertex_start_dw + 4; - map->len_dw[VARYING_SLOT_POS] = 4; - } - - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0)) { - map->start_dw[VARYING_SLOT_CLIP_DIST0] = - map->per_vertex_start_dw + fixed_header_size + 0; - map->len_dw[VARYING_SLOT_CLIP_DIST0] = 4; - } - - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1)) { - map->start_dw[VARYING_SLOT_CLIP_DIST1] = - map->per_vertex_start_dw + fixed_header_size + 4; - map->len_dw[VARYING_SLOT_CLIP_DIST1] = 4; - } - - outputs_written &= ~per_vertex_header_bits; - } - - /* cull distances should be lowered earlier */ - assert(!(outputs_written & BITFIELD64_BIT(VARYING_SLOT_CULL_DIST0))); - assert(!(outputs_written & BITFIELD64_BIT(VARYING_SLOT_CULL_DIST1))); - - map->per_vertex_data_size_dw = 0; - - /* For fast linked libraries, we can't pack the MUE, as the fragment shader - * will be compiled without access to the MUE map and won't be able to find - * out where everything is. - * Instead, keep doing things as we did before the packing, just laying out - * everything in varying order, which is how the FS will expect them. - */ - if (compact_mue) { - unsigned start_dw = map->per_vertex_start_dw; - if (!map->user_data_in_vertex_header) - start_dw += map->per_vertex_header_size_dw; - - unsigned header_used_dw = 0; - for (unsigned type = VERT; type <= VERT_FLAT; ++type) { - for (auto it = orders[type].cbegin(); it != orders[type].cend(); ++it) { - int location = (*it).location; - if (location < 0) { - start_dw += (*it).dwords; - if (map->user_data_in_vertex_header && header_used_dw < 4) { - header_used_dw += (*it).dwords; - assert(header_used_dw <= 4); - if (header_used_dw == 4) - start_dw += 4; /* jump over gl_position */ - } else { - map->per_vertex_data_size_dw += (*it).dwords; - } - continue; - } - - assert(map->start_dw[location] == -1); - - assert(location >= VARYING_SLOT_VAR0); - - brw_mue_assign_position(&*it, map, start_dw); - - start_dw += (*it).dwords; - if (map->user_data_in_vertex_header && header_used_dw < 4) { - header_used_dw += (*it).dwords; - assert(header_used_dw <= 4); - if (header_used_dw == 4) - start_dw += 4; /* jump over gl_position */ - } else { - map->per_vertex_data_size_dw += (*it).dwords; - } - outputs_written &= ~BITFIELD64_RANGE(location, (*it).slots); - } - } - } else { - unsigned start_dw = map->per_vertex_start_dw + - map->per_vertex_header_size_dw; - - uint64_t per_vertex_outputs = outputs_written & ~nir->info.per_primitive_outputs; - while (per_vertex_outputs) { - uint64_t location = ffsll(per_vertex_outputs) - 1; - - assert(map->start_dw[location] == -1); - assert(location >= VARYING_SLOT_VAR0); - - nir_variable *var = - brw_nir_find_complete_variable_with_location(nir, - nir_var_shader_out, - location); - struct attr_desc d; - d.location = location; - d.type = brw_nir_get_var_type(nir, var); - d.dwords = glsl_count_dword_slots(d.type, false); - d.slots = glsl_count_attribute_slots(d.type, false); - - brw_mue_assign_position(&d, map, start_dw); - - map->per_vertex_data_size_dw += ALIGN(d.dwords, 4); - start_dw += ALIGN(d.dwords, 4); - - per_vertex_outputs &= ~BITFIELD64_RANGE(location, d.slots); - } - } - - map->per_vertex_pitch_dw = ALIGN(map->per_vertex_header_size_dw + - map->per_vertex_data_size_dw, 8); - - map->size_dw = - map->per_vertex_start_dw + map->per_vertex_pitch_dw * map->max_vertices; - - assert(map->size_dw % 8 == 0); -} - -static void -brw_print_mue_map(FILE *fp, const struct brw_mue_map *map, struct nir_shader *nir) -{ - fprintf(fp, "MUE map (%d dwords, %d primitives, %d vertices)\n", - map->size_dw, map->max_primitives, map->max_vertices); - fprintf(fp, " <%4d, %4d>: VARYING_SLOT_PRIMITIVE_COUNT\n", - map->start_dw[VARYING_SLOT_PRIMITIVE_COUNT], - map->start_dw[VARYING_SLOT_PRIMITIVE_COUNT] + - map->len_dw[VARYING_SLOT_PRIMITIVE_COUNT] - 1); - fprintf(fp, " <%4d, %4d>: VARYING_SLOT_PRIMITIVE_INDICES\n", - map->start_dw[VARYING_SLOT_PRIMITIVE_INDICES], - map->start_dw[VARYING_SLOT_PRIMITIVE_INDICES] + - map->len_dw[VARYING_SLOT_PRIMITIVE_INDICES] - 1); - - fprintf(fp, " ----- per primitive (start %d, header_size %d, data_size %d, pitch %d)\n", - map->per_primitive_start_dw, - map->per_primitive_header_size_dw, - map->per_primitive_data_size_dw, - map->per_primitive_pitch_dw); - - for (unsigned i = 0; i < VARYING_SLOT_MAX; i++) { - if (map->start_dw[i] < 0) - continue; - - const unsigned offset = map->start_dw[i]; - const unsigned len = map->len_dw[i]; - - if (offset < map->per_primitive_start_dw || - offset >= map->per_primitive_start_dw + map->per_primitive_pitch_dw) - continue; - - const char *name = - gl_varying_slot_name_for_stage((gl_varying_slot)i, - MESA_SHADER_MESH); - - fprintf(fp, " <%4d, %4d>: %s (%d)\n", offset, offset + len - 1, - name, i); - } - - fprintf(fp, " ----- per vertex (start %d, header_size %d, data_size %d, pitch %d)\n", - map->per_vertex_start_dw, - map->per_vertex_header_size_dw, - map->per_vertex_data_size_dw, - map->per_vertex_pitch_dw); - - for (unsigned i = 0; i < VARYING_SLOT_MAX; i++) { - if (map->start_dw[i] < 0) - continue; - - const unsigned offset = map->start_dw[i]; - const unsigned len = map->len_dw[i]; - - if (offset < map->per_vertex_start_dw || - offset >= map->per_vertex_start_dw + map->per_vertex_pitch_dw) - continue; - - nir_variable *var = - nir_find_variable_with_location(nir, nir_var_shader_out, i); - bool flat = var->data.interpolation == INTERP_MODE_FLAT; - - const char *name = - gl_varying_slot_name_for_stage((gl_varying_slot)i, - MESA_SHADER_MESH); - - fprintf(fp, " <%4d, %4d>: %s (%d)%s\n", offset, offset + len - 1, - name, i, flat ? " (flat)" : ""); - } - - fprintf(fp, "\n"); -} - -static void -brw_nir_lower_mue_outputs(nir_shader *nir, const struct brw_mue_map *map) -{ - nir_foreach_shader_out_variable(var, nir) { - int location = var->data.location; - assert(location >= 0); - assert(map->start_dw[location] != -1); - var->data.driver_location = map->start_dw[location]; - } - - NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out, - type_size_scalar_dwords, nir_lower_io_lower_64bit_to_32); -} - -static void -brw_nir_initialize_mue(nir_shader *nir, - const struct brw_mue_map *map, - unsigned dispatch_width) -{ - assert(map->per_primitive_header_size_dw > 0); - - nir_builder b; - nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir); - b = nir_builder_at(nir_before_impl(entrypoint)); - - nir_def *dw_off = nir_imm_int(&b, 0); - nir_def *zerovec = nir_imm_vec4(&b, 0, 0, 0, 0); - - /* TODO(mesh): can we write in bigger batches, generating fewer SENDs? */ - - assert(!nir->info.workgroup_size_variable); - const unsigned workgroup_size = nir->info.workgroup_size[0] * - nir->info.workgroup_size[1] * - nir->info.workgroup_size[2]; - - /* Invocations from a single workgroup will cooperate in zeroing MUE. */ - - /* How many prims each invocation needs to cover without checking its index? */ - unsigned prims_per_inv = map->max_primitives / workgroup_size; - - /* Zero first 4 dwords of MUE Primitive Header: - * Reserved, RTAIndex, ViewportIndex, CullPrimitiveMask. - */ - - nir_def *local_invocation_index = nir_load_local_invocation_index(&b); - - /* Zero primitive headers distanced by workgroup_size, starting from - * invocation index. - */ - for (unsigned prim_in_inv = 0; prim_in_inv < prims_per_inv; ++prim_in_inv) { - nir_def *prim = nir_iadd_imm(&b, local_invocation_index, - prim_in_inv * workgroup_size); - - nir_store_per_primitive_output(&b, zerovec, prim, dw_off, - .base = (int)map->per_primitive_start_dw, - .write_mask = WRITEMASK_XYZW, - .component = 0, - .src_type = nir_type_uint32); - } - - /* How many prims are left? */ - unsigned remaining = map->max_primitives % workgroup_size; - - if (remaining) { - /* Zero "remaining" primitive headers starting from the last one covered - * by the loop above + workgroup_size. - */ - nir_def *cmp = nir_ilt_imm(&b, local_invocation_index, remaining); - nir_if *if_stmt = nir_push_if(&b, cmp); - { - nir_def *prim = nir_iadd_imm(&b, local_invocation_index, - prims_per_inv * workgroup_size); - - nir_store_per_primitive_output(&b, zerovec, prim, dw_off, - .base = (int)map->per_primitive_start_dw, - .write_mask = WRITEMASK_XYZW, - .component = 0, - .src_type = nir_type_uint32); - } - nir_pop_if(&b, if_stmt); - } - - /* If there's more than one subgroup, then we need to wait for all of them - * to finish initialization before we can proceed. Otherwise some subgroups - * may start filling MUE before other finished initializing. - */ - if (workgroup_size > dispatch_width) { - nir_barrier(&b, SCOPE_WORKGROUP, SCOPE_WORKGROUP, - NIR_MEMORY_ACQ_REL, nir_var_shader_out); - } - - if (remaining) { - nir_metadata_preserve(entrypoint, nir_metadata_none); - } else { - nir_metadata_preserve(entrypoint, nir_metadata_block_index | - nir_metadata_dominance); - } -} - -static void -brw_nir_adjust_offset(nir_builder *b, nir_intrinsic_instr *intrin, uint32_t pitch) -{ - nir_src *index_src = nir_get_io_arrayed_index_src(intrin); - nir_src *offset_src = nir_get_io_offset_src(intrin); - - b->cursor = nir_before_instr(&intrin->instr); - nir_def *offset = - nir_iadd(b, - offset_src->ssa, - nir_imul_imm(b, index_src->ssa, pitch)); - nir_src_rewrite(offset_src, offset); -} - -static bool -brw_nir_adjust_offset_for_arrayed_indices_instr(nir_builder *b, - nir_intrinsic_instr *intrin, - void *data) -{ - const struct brw_mue_map *map = (const struct brw_mue_map *) data; - - /* Remap per_vertex and per_primitive offsets using the extra source and - * the pitch. - */ - switch (intrin->intrinsic) { - case nir_intrinsic_load_per_vertex_output: - case nir_intrinsic_store_per_vertex_output: - brw_nir_adjust_offset(b, intrin, map->per_vertex_pitch_dw); - - return true; - - case nir_intrinsic_load_per_primitive_output: - case nir_intrinsic_store_per_primitive_output: { - struct nir_io_semantics sem = nir_intrinsic_io_semantics(intrin); - uint32_t pitch; - if (sem.location == VARYING_SLOT_PRIMITIVE_INDICES) - pitch = map->per_primitive_indices_dw; - else - pitch = map->per_primitive_pitch_dw; - - brw_nir_adjust_offset(b, intrin, pitch); - - return true; - } - - default: - return false; - } -} - -static bool -brw_nir_adjust_offset_for_arrayed_indices(nir_shader *nir, const struct brw_mue_map *map) -{ - return nir_shader_intrinsics_pass(nir, - brw_nir_adjust_offset_for_arrayed_indices_instr, - nir_metadata_block_index | - nir_metadata_dominance, - (void *)map); -} - -struct index_packing_state { - unsigned vertices_per_primitive; - nir_variable *original_prim_indices; - nir_variable *packed_prim_indices; -}; - -static bool -brw_can_pack_primitive_indices(nir_shader *nir, struct index_packing_state *state) -{ - /* can single index fit into one byte of U888X format? */ - if (nir->info.mesh.max_vertices_out > 255) - return false; - - state->vertices_per_primitive = - mesa_vertices_per_prim(nir->info.mesh.primitive_type); - /* packing point indices doesn't help */ - if (state->vertices_per_primitive == 1) - return false; - - state->original_prim_indices = - nir_find_variable_with_location(nir, - nir_var_shader_out, - VARYING_SLOT_PRIMITIVE_INDICES); - /* no indices = no changes to the shader, but it's still worth it, - * because less URB space will be used - */ - if (!state->original_prim_indices) - return true; - - ASSERTED const struct glsl_type *type = state->original_prim_indices->type; - assert(glsl_type_is_array(type)); - assert(glsl_type_is_vector(glsl_without_array(type))); - assert(glsl_without_array(type)->vector_elements == state->vertices_per_primitive); - - nir_foreach_function_impl(impl, nir) { - nir_foreach_block(block, impl) { - nir_foreach_instr(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - - if (intrin->intrinsic != nir_intrinsic_store_deref) { - /* any unknown deref operation on primitive indices -> don't pack */ - unsigned num_srcs = nir_intrinsic_infos[intrin->intrinsic].num_srcs; - for (unsigned i = 0; i < num_srcs; i++) { - nir_deref_instr *deref = nir_src_as_deref(intrin->src[i]); - if (!deref) - continue; - nir_variable *var = nir_deref_instr_get_variable(deref); - - if (var == state->original_prim_indices) - return false; - } - - continue; - } - - nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]); - if (!deref) - continue; - - nir_variable *var = nir_deref_instr_get_variable(deref); - if (var != state->original_prim_indices) - continue; - - if (deref->deref_type != nir_deref_type_array) - return false; /* unknown chain of derefs */ - - nir_deref_instr *var_deref = nir_src_as_deref(deref->parent); - if (!var_deref || var_deref->deref_type != nir_deref_type_var) - return false; /* unknown chain of derefs */ - - assert (var_deref->var == state->original_prim_indices); - - unsigned write_mask = nir_intrinsic_write_mask(intrin); - - /* If only some components are written, then we can't easily pack. - * In theory we could, by loading current dword value, bitmasking - * one byte and storing back the whole dword, but it would be slow - * and could actually decrease performance. TODO: reevaluate this - * once there will be something hitting this. - */ - if (write_mask != BITFIELD_MASK(state->vertices_per_primitive)) - return false; - } - } - } - - return true; -} - -static bool -brw_pack_primitive_indices_instr(nir_builder *b, nir_intrinsic_instr *intrin, - void *data) -{ - if (intrin->intrinsic != nir_intrinsic_store_deref) - return false; - - nir_deref_instr *array_deref = nir_src_as_deref(intrin->src[0]); - if (!array_deref || array_deref->deref_type != nir_deref_type_array) - return false; - - nir_deref_instr *var_deref = nir_src_as_deref(array_deref->parent); - if (!var_deref || var_deref->deref_type != nir_deref_type_var) - return false; - - struct index_packing_state *state = - (struct index_packing_state *)data; - - nir_variable *var = var_deref->var; - - if (var != state->original_prim_indices) - return false; - - unsigned vertices_per_primitive = state->vertices_per_primitive; - - b->cursor = nir_before_instr(&intrin->instr); - - nir_deref_instr *new_var_deref = - nir_build_deref_var(b, state->packed_prim_indices); - nir_deref_instr *new_array_deref = - nir_build_deref_array(b, new_var_deref, array_deref->arr.index.ssa); - - nir_src *data_src = &intrin->src[1]; - nir_def *data_def = - data_src->ssa; - - nir_def *new_data = - nir_ior(b, nir_ishl_imm(b, nir_channel(b, data_def, 0), 0), - nir_ishl_imm(b, nir_channel(b, data_def, 1), 8)); - - if (vertices_per_primitive >= 3) { - new_data = - nir_ior(b, new_data, - nir_ishl_imm(b, nir_channel(b, data_def, 2), 16)); - } - - nir_build_store_deref(b, &new_array_deref->def, new_data); - - nir_instr_remove(&intrin->instr); - - return true; -} - -static bool -brw_pack_primitive_indices(nir_shader *nir, void *data) -{ - struct index_packing_state *state = (struct index_packing_state *)data; - - const struct glsl_type *new_type = - glsl_array_type(glsl_uint_type(), - nir->info.mesh.max_primitives_out, - 0); - - state->packed_prim_indices = - nir_variable_create(nir, nir_var_shader_out, - new_type, "gl_PrimitiveIndicesPacked"); - state->packed_prim_indices->data.location = VARYING_SLOT_PRIMITIVE_INDICES; - state->packed_prim_indices->data.interpolation = INTERP_MODE_NONE; - state->packed_prim_indices->data.per_primitive = 1; - - return nir_shader_intrinsics_pass(nir, brw_pack_primitive_indices_instr, - nir_metadata_block_index | - nir_metadata_dominance, - data); -} - -const unsigned * -brw_compile_mesh(const struct brw_compiler *compiler, - struct brw_compile_mesh_params *params) -{ - struct nir_shader *nir = params->base.nir; - const struct brw_mesh_prog_key *key = params->key; - struct brw_mesh_prog_data *prog_data = params->prog_data; - const bool debug_enabled = brw_should_print_shader(nir, DEBUG_MESH); - - prog_data->base.base.stage = MESA_SHADER_MESH; - prog_data->base.base.total_shared = nir->info.shared_size; - prog_data->base.base.total_scratch = 0; - - prog_data->base.local_size[0] = nir->info.workgroup_size[0]; - prog_data->base.local_size[1] = nir->info.workgroup_size[1]; - prog_data->base.local_size[2] = nir->info.workgroup_size[2]; - - prog_data->clip_distance_mask = (1 << nir->info.clip_distance_array_size) - 1; - prog_data->cull_distance_mask = - ((1 << nir->info.cull_distance_array_size) - 1) << - nir->info.clip_distance_array_size; - prog_data->primitive_type = nir->info.mesh.primitive_type; - - struct index_packing_state index_packing_state = {}; - if (brw_can_pack_primitive_indices(nir, &index_packing_state)) { - if (index_packing_state.original_prim_indices) - NIR_PASS(_, nir, brw_pack_primitive_indices, &index_packing_state); - prog_data->index_format = BRW_INDEX_FORMAT_U888X; - } else { - prog_data->index_format = BRW_INDEX_FORMAT_U32; - } - - prog_data->uses_drawid = - BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); - - brw_nir_lower_tue_inputs(nir, params->tue_map); - - brw_compute_mue_map(compiler, nir, &prog_data->map, - prog_data->index_format, key->compact_mue); - brw_nir_lower_mue_outputs(nir, &prog_data->map); - - brw_simd_selection_state simd_state{ - .devinfo = compiler->devinfo, - .prog_data = &prog_data->base, - .required_width = brw_required_dispatch_width(&nir->info), - }; - - std::unique_ptr v[3]; - - for (int simd = 0; simd < 3; simd++) { - if (!brw_simd_should_compile(simd_state, simd)) - continue; - - const unsigned dispatch_width = 8 << simd; - - nir_shader *shader = nir_shader_clone(params->base.mem_ctx, nir); - - /* - * When Primitive Header is enabled, we may not generates writes to all - * fields, so let's initialize everything. - */ - if (prog_data->map.per_primitive_header_size_dw > 0) - NIR_PASS_V(shader, brw_nir_initialize_mue, &prog_data->map, dispatch_width); - - brw_nir_apply_key(shader, compiler, &key->base, dispatch_width); - - NIR_PASS(_, shader, brw_nir_adjust_offset_for_arrayed_indices, &prog_data->map); - /* Load uniforms can do a better job for constants, so fold before it. */ - NIR_PASS(_, shader, nir_opt_constant_folding); - NIR_PASS(_, shader, brw_nir_lower_load_uniforms); - - NIR_PASS(_, shader, brw_nir_lower_simd, dispatch_width); - - brw_postprocess_nir(shader, compiler, debug_enabled, - key->base.robust_flags); - - v[simd] = std::make_unique(compiler, ¶ms->base, - &key->base, - &prog_data->base.base, - shader, dispatch_width, - params->base.stats != NULL, - debug_enabled); - - if (prog_data->base.prog_mask) { - unsigned first = ffs(prog_data->base.prog_mask) - 1; - v[simd]->import_uniforms(v[first].get()); - } - - const bool allow_spilling = !brw_simd_any_compiled(simd_state); - if (v[simd]->run_mesh(allow_spilling)) - brw_simd_mark_compiled(simd_state, simd, v[simd]->spilled_any_registers); - else - simd_state.error[simd] = ralloc_strdup(params->base.mem_ctx, v[simd]->fail_msg); - } - - int selected_simd = brw_simd_select(simd_state); - if (selected_simd < 0) { - params->base.error_str = - ralloc_asprintf(params->base.mem_ctx, - "Can't compile shader: " - "SIMD8 '%s', SIMD16 '%s' and SIMD32 '%s'.\n", - simd_state.error[0], simd_state.error[1], - simd_state.error[2]); - return NULL; - } - - fs_visitor *selected = v[selected_simd].get(); - prog_data->base.prog_mask = 1 << selected_simd; - - if (unlikely(debug_enabled)) { - if (params->tue_map) { - fprintf(stderr, "Mesh Input "); - brw_print_tue_map(stderr, params->tue_map); - } - fprintf(stderr, "Mesh Output "); - brw_print_mue_map(stderr, &prog_data->map, nir); - } - - fs_generator g(compiler, ¶ms->base, &prog_data->base.base, - false, MESA_SHADER_MESH); - if (unlikely(debug_enabled)) { - g.enable_debug(ralloc_asprintf(params->base.mem_ctx, - "%s mesh shader %s", - nir->info.label ? nir->info.label - : "unnamed", - nir->info.name)); - } - - g.generate_code(selected->cfg, selected->dispatch_width, selected->shader_stats, - selected->performance_analysis.require(), params->base.stats); - g.add_const_data(nir->constant_data, nir->constant_data_size); - return g.get_assembly(); -} diff --git a/src/intel/compiler/elk/brw_nir.c b/src/intel/compiler/elk/brw_nir.c index 203113ed3ec..ff2bbbc239a 100644 --- a/src/intel/compiler/elk/brw_nir.c +++ b/src/intel/compiler/elk/brw_nir.c @@ -23,7 +23,6 @@ #include "intel_nir.h" #include "brw_nir.h" -#include "brw_nir_rt.h" #include "brw_shader.h" #include "dev/intel_debug.h" #include "compiler/glsl_types.h" @@ -1770,15 +1769,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, OPT(nir_opt_dce); - /* The mesh stages require this pass to be called at the last minute, - * but if anything is done by it, it will also constant fold, and that - * undoes the work done by nir_trivialize_registers, so call it right - * before that one instead. - */ - if (nir->info.stage == MESA_SHADER_MESH || - nir->info.stage == MESA_SHADER_TASK) - brw_nir_adjust_payload(nir); - nir_trivialize_registers(nir); /* This is the last pass we run before we start emitting stuff. It diff --git a/src/intel/compiler/elk/brw_nir_lower_cooperative_matrix.c b/src/intel/compiler/elk/brw_nir_lower_cooperative_matrix.c deleted file mode 100644 index 8ed937baaed..00000000000 --- a/src/intel/compiler/elk/brw_nir_lower_cooperative_matrix.c +++ /dev/null @@ -1,818 +0,0 @@ -/* - * Copyright 2023 Intel Corporation - * SPDX-License-Identifier: MIT - */ - -/** - * \file brw_nir_lower_cooperative_matrix.c - * Lower cooperative matrix to subgroup operations. - * - * All supported matrix types are assumed to have either 8 rows or 8 - * columns. The other dimension of the matrix is typically 8 times the number - * of data elements that can be stored in a 32-bit dword. Matrix data is - * indexed by a combination of an array element and a subgroup invocation ID. - * - * Two layouts for matrix data are used. In the first layout, - * subgroupShuffle(slice[N], ...) accesses row N of the matrix. This will be - * called row-major hereafter. In the other layout, - * subgroupShuffle(slice[...], M) accesses column M of the matrix. This will - * be called column-major hereafter. In cases where a single 32-bit value is - * stored in each entry, these layouts are identical. - * - * The subtle difference arises when multiple values are packed into a single - * 32-bit dword. If two 16-bit values are packed in a single 32-bit value in - * column-major, subgroupShuffle(slice[0], 1) holds matrix entries m[1][1] and - * m[2][1] (in m[row][column] notation). In row-major, that same shuffle holds - * m[0][2] and m[0][3]. - * - * There is an alternate way to think about the matrix layouts. Every matrix - * size supported by the Intel driver is either Sx8 (e.g., 16x8 for float16 B - * matrix) or Sx8T (e.g., 8x32 for int8 A matrix). The A matrix and B matrix - * layouts are such that a single 8 dword register hold an entire row of the - * matrix. - * - * Consider a matrix stored starting in register g32. In an A matrix, the - * packed dwords of g32 contain only the data for a single row of the - * matrix. g32 is row 0, g33 is row 1, etc. In a B matrix, the packed dwords - * of g(32+N).X contain only the data for a single column of the - * matrix. g[32:40].0 is column 0, g[32:40].1 is column 1, etc. - * - * This leads to some shenanigans in \c lower_cmat_load_store. - * - * In the common case, A, C, and result matrices are stored row major while B - * matrices are stored column major. This arrangement facilitates efficient - * dot product operations using DPAS or DP4A instructions. - * - * Future optimizations are possible when row and column major are - * flipped. That is, efficient dot products are also possible when A, C, and - * result matrices are column major while B is row major. - */ - -#include "brw_nir.h" - -struct lower_cmat_state { - nir_shader *shader; - - struct hash_table *slice_coop_types; - - struct hash_table *vars_to_slice; - - unsigned subgroup_size; -}; - -static void -print_coop_types(struct lower_cmat_state *state) -{ - fprintf(stderr, "--- Slices to Cooperative Matrix type table\n"); - hash_table_foreach(state->slice_coop_types, e) { - nir_variable *var = (void *)e->key; - const struct glsl_type *t = e->data; - fprintf(stderr, "%p: %s -> %s\n", var, var->name, glsl_get_type_name(t)); - } - fprintf(stderr, "\n\n"); -} - -static const struct glsl_type * -get_coop_type_for_slice(struct lower_cmat_state *state, nir_deref_instr *deref) -{ - nir_variable *var = nir_deref_instr_get_variable(deref); - struct hash_entry *entry = _mesa_hash_table_search(state->slice_coop_types, var); - - assert(entry != NULL); - - return entry->data; -} - -static bool -lower_cmat_filter(const nir_instr *instr, const void *_state) -{ - if (instr->type == nir_instr_type_deref) { - nir_deref_instr *deref = nir_instr_as_deref(instr); - return glsl_type_is_cmat(deref->type); - } - - if (instr->type != nir_instr_type_intrinsic) - return false; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - switch (intrin->intrinsic) { - case nir_intrinsic_cmat_construct: - case nir_intrinsic_cmat_load: - case nir_intrinsic_cmat_store: - case nir_intrinsic_cmat_length: - case nir_intrinsic_cmat_muladd: - case nir_intrinsic_cmat_unary_op: - case nir_intrinsic_cmat_binary_op: - case nir_intrinsic_cmat_scalar_op: - case nir_intrinsic_cmat_bitcast: - case nir_intrinsic_cmat_insert: - case nir_intrinsic_cmat_extract: - case nir_intrinsic_cmat_copy: - return true; - - default: - return false; - } -} - -/** - * Get number of matrix elements packed in each component of the slice. - */ -static unsigned -get_packing_factor(const struct glsl_cmat_description desc, - const struct glsl_type *slice_type) -{ - const struct glsl_type *slice_element_type = glsl_without_array(slice_type); - - assert(!glsl_type_is_cmat(slice_type)); - - assert(glsl_get_bit_size(slice_element_type) >= glsl_base_type_get_bit_size(desc.element_type)); - assert(glsl_get_bit_size(slice_element_type) % glsl_base_type_get_bit_size(desc.element_type) == 0); - - return glsl_get_bit_size(slice_element_type) / glsl_base_type_get_bit_size(desc.element_type); -} - -static const struct glsl_type * -get_slice_type_from_desc(const struct lower_cmat_state *state, - const struct glsl_cmat_description desc) -{ - enum glsl_base_type base_type; - - /* Number of matrix elements stored by each subgroup invocation. If the - * data is packed, the slice size will be less than this. - */ - const unsigned elements_per_invocation = - (desc.rows * desc.cols) / state->subgroup_size; - - assert(elements_per_invocation > 0); - - const unsigned element_bits = 32; - const unsigned bits = glsl_base_type_get_bit_size(desc.element_type); - unsigned packing_factor = MIN2(elements_per_invocation, - element_bits / bits); - - /* Adjust the packing factor so that each row of the matrix fills and - * entire GRF. - * - * The in-register layout of B matrices is different, so those are handled - * more like column major (for row major matrices). See the file comment - * for more details. - */ - const unsigned actual_cols = desc.use != GLSL_CMAT_USE_B ? desc.cols : desc.rows; - while ((actual_cols / packing_factor) < 8) { - assert(packing_factor > 1); - packing_factor /= 2; - } - - switch (desc.element_type) { - case GLSL_TYPE_FLOAT: - base_type = GLSL_TYPE_FLOAT; - break; - case GLSL_TYPE_UINT: - case GLSL_TYPE_FLOAT16: - case GLSL_TYPE_UINT8: - case GLSL_TYPE_UINT16: - base_type = glsl_get_base_type(glsl_uintN_t_type(packing_factor * bits)); - break; - case GLSL_TYPE_INT: - case GLSL_TYPE_INT8: - case GLSL_TYPE_INT16: - base_type = glsl_get_base_type(glsl_intN_t_type(packing_factor * bits)); - break; - default: - unreachable("Invalid cooperative matrix element type."); - } - - unsigned len = elements_per_invocation / packing_factor; - - /* Supported matrix sizes are designed to fill either 4 or 8 SIMD8 - * registers. That means: - * - * 4 regsiters 8 registers - * SIMD32 len = 1 len = 2 - * SIMD16 len = 2 len = 4 - * SIMD8 len = 4 len = 8 - * - * If configurations are added that result in other values of len, at the - * very least this assertion will need to be updated. The only value of len - * that makes sense to add would be 16, and that would be a lot of - * registers. - */ - assert(len == 1 || len == 2 || len == 4 || len == 8); - - const struct glsl_type *slice_type = glsl_vector_type(base_type, len); - - assert(packing_factor == get_packing_factor(desc, slice_type)); - - return slice_type; -} - -static const struct glsl_type * -get_slice_type(const struct lower_cmat_state *state, - const struct glsl_type *type) -{ - if (glsl_type_is_array(type)) { - const struct glsl_type *slice_type = - get_slice_type(state, glsl_get_array_element(type)); - - return glsl_array_type(slice_type, glsl_array_size(type), 0); - } - - assert(glsl_type_is_cmat(type)); - - return get_slice_type_from_desc(state, - *glsl_get_cmat_description(type)); -} - -static nir_deref_instr * -create_local_slice(struct lower_cmat_state *state, nir_builder *b, - const struct glsl_type *mat_type, const char *name) -{ - const struct glsl_type *slice_type = get_slice_type(state, mat_type); - nir_variable *slice_var = nir_local_variable_create(b->impl, slice_type, name); - _mesa_hash_table_insert(state->slice_coop_types, slice_var, (void *)mat_type); - return nir_build_deref_var(b, slice_var); -} - -static void -lower_cmat_load_store(nir_builder *b, nir_intrinsic_instr *intrin, - struct lower_cmat_state *state) -{ - const bool load = intrin->intrinsic == nir_intrinsic_cmat_load; - const unsigned mat_src = load ? 0 : 1; - const unsigned ptr_src = load ? 1 : 0; - - nir_deref_instr *slice = nir_src_as_deref(intrin->src[mat_src]); - const struct glsl_type *mat_type = get_coop_type_for_slice(state, slice); - const struct glsl_cmat_description *desc = glsl_get_cmat_description(mat_type); - - nir_def *results[NIR_MAX_VEC_COMPONENTS]; - const unsigned num_components = glsl_get_vector_elements(slice->type); - const unsigned packing_factor = get_packing_factor(*desc, slice->type); - - nir_deref_instr *pointer = nir_src_as_deref(intrin->src[ptr_src]); - - if ((nir_intrinsic_matrix_layout(intrin) == GLSL_MATRIX_LAYOUT_ROW_MAJOR) == - (desc->use != GLSL_CMAT_USE_B)) { - nir_def *stride = nir_udiv_imm(b, intrin->src[2].ssa, packing_factor); - - const struct glsl_type *element_type = - glsl_scalar_type(glsl_get_base_type(slice->type)); - - pointer = nir_build_deref_cast(b, &pointer->def, pointer->modes, - element_type, - glsl_get_bit_size(element_type) / 8); - - nir_def *invocation = nir_load_subgroup_invocation(b); - nir_def *base_offset; - nir_def *step; - - if (desc->use != GLSL_CMAT_USE_B) { - base_offset = nir_iadd(b, - nir_imul(b, - nir_udiv_imm(b, invocation, 8), - stride), - nir_umod_imm(b, invocation, 8)); - - step = nir_imul_imm(b, stride, state->subgroup_size / 8); - } else { - base_offset = nir_iadd(b, - nir_imul(b, - nir_umod_imm(b, invocation, 8), - stride), - nir_udiv_imm(b, invocation, 8)); - - step = nir_imm_int(b, state->subgroup_size / 8); - } - - for (unsigned i = 0; i < num_components; i++) { - nir_def *offset = nir_imul_imm(b, step, i); - - nir_deref_instr *memory_deref = - nir_build_deref_ptr_as_array(b, pointer, - nir_i2iN(b, - nir_iadd(b, - base_offset, - offset), - pointer->def.bit_size)); - - if (load) { - results[i] = nir_load_deref(b, memory_deref); - } else { - nir_def *src = nir_channel(b, nir_load_deref(b, slice), i); - nir_store_deref(b, memory_deref, src, 0x1); - } - } - } else { - nir_def *stride = intrin->src[2].ssa; - - const struct glsl_type *element_type = glsl_scalar_type(desc->element_type); - const unsigned element_bits = glsl_base_type_get_bit_size(desc->element_type); - const unsigned element_stride = element_bits / 8; - - pointer = nir_build_deref_cast(b, &pointer->def, pointer->modes, element_type, - element_stride); - - nir_def *invocation_div_8 = nir_udiv_imm(b, nir_load_subgroup_invocation(b), 8); - nir_def *invocation_mod_8 = nir_umod_imm(b, nir_load_subgroup_invocation(b), 8); - - nir_def *packed_stride = nir_imul_imm(b, stride, packing_factor); - - for (unsigned i = 0; i < num_components; i++) { - const unsigned i_offset = i * (state->subgroup_size / 8); - nir_def *v[4]; - - for (unsigned j = 0; j < packing_factor; j++) { - nir_def *j_offset = nir_imul_imm(b, stride, j); - nir_def *offset; - - if (desc->use != GLSL_CMAT_USE_B) { - offset = nir_iadd(b, - nir_iadd(b, - nir_imul(b, - invocation_mod_8, - packed_stride), - invocation_div_8), - nir_iadd_imm(b, j_offset, i_offset)); - } else { - offset = nir_iadd(b, - nir_iadd(b, - nir_imul(b, - invocation_div_8, - packed_stride), - invocation_mod_8), - nir_iadd(b, - nir_imul_imm(b, - packed_stride, - i_offset), - j_offset)); - } - - nir_deref_instr *memory_deref = - nir_build_deref_ptr_as_array(b, pointer, - nir_i2iN(b, - offset, - pointer->def.bit_size)); - - if (load) { - v[j] = nir_load_deref(b, memory_deref); - } else { - nir_def *src = nir_channel(b, nir_load_deref(b, slice), i); - - nir_def *v = - nir_channel(b, nir_unpack_bits(b, src, element_bits), j); - - nir_store_deref(b, memory_deref, v, 0x1); - } - } - - if (load) { - results[i] = nir_pack_bits(b, nir_vec(b, v, packing_factor), - packing_factor * element_bits); - } - } - } - - if (load) - nir_store_deref(b, slice, nir_vec(b, results, num_components), - nir_component_mask(num_components)); -} - -static void -lower_cmat_unary_op(nir_builder *b, nir_intrinsic_instr *intrin, - struct lower_cmat_state *state) -{ - nir_deref_instr *dst_slice = nir_src_as_deref(intrin->src[0]); - nir_deref_instr *src_slice = nir_src_as_deref(intrin->src[1]); - nir_def *results[NIR_MAX_VEC_COMPONENTS]; - const unsigned num_components = glsl_get_vector_elements(dst_slice->type); - - const struct glsl_type *dst_mat_type = - get_coop_type_for_slice(state, dst_slice); - const struct glsl_type *src_mat_type = - get_coop_type_for_slice(state, src_slice); - - const struct glsl_cmat_description dst_desc = - *glsl_get_cmat_description(dst_mat_type); - - const struct glsl_cmat_description src_desc = - *glsl_get_cmat_description(src_mat_type); - - const unsigned dst_bits = glsl_base_type_bit_size(dst_desc.element_type); - const unsigned src_bits = glsl_base_type_bit_size(src_desc.element_type); - - /* The type of the returned slice may be different from the type of the - * input slice. - */ - const unsigned dst_packing_factor = - get_packing_factor(dst_desc, dst_slice->type); - - const unsigned src_packing_factor = - get_packing_factor(src_desc, src_slice->type); - - const nir_op op = nir_intrinsic_alu_op(intrin); - - /* There are three possible cases: - * - * 1. dst_packing_factor == src_packing_factor. This is the common case, - * and handling it is straightforward. - * - * 2. dst_packing_factor > src_packing_factor. This occurs when converting a - * float32_t matrix slice to a packed float16_t slice. Loop over the size - * of the destination slice, but read multiple entries from the source - * slice on each iteration. - * - * 3. dst_packing_factor < src_packing_factor. This occurs when converting a - * packed int8_t matrix slice to an int32_t slice. Loop over the size of - * the source slice, but write multiple entries to the destination slice - * on each iteration. - * - * Handle all cases by iterating over the total (non-packed) number of - * elements in the slice. When dst_packing_factor values have been - * calculated, store them. - */ - assert((dst_packing_factor * glsl_get_vector_elements(dst_slice->type)) == - (src_packing_factor * glsl_get_vector_elements(src_slice->type))); - - /* Stores at most dst_packing_factor partial results. */ - nir_def *v[4]; - assert(dst_packing_factor <= 4); - - for (unsigned i = 0; i < num_components * dst_packing_factor; i++) { - const unsigned dst_chan_index = i % dst_packing_factor; - const unsigned src_chan_index = i % src_packing_factor; - const unsigned dst_index = i / dst_packing_factor; - const unsigned src_index = i / src_packing_factor; - - nir_def *src = - nir_channel(b, - nir_unpack_bits(b, - nir_channel(b, - nir_load_deref(b, src_slice), - src_index), - src_bits), - src_chan_index); - - v[dst_chan_index] = nir_build_alu1(b, op, src); - - if (dst_chan_index == (dst_packing_factor - 1)) { - results[dst_index] = - nir_pack_bits(b, nir_vec(b, v, dst_packing_factor), - dst_packing_factor * dst_bits); - } - } - - nir_store_deref(b, dst_slice, nir_vec(b, results, num_components), - nir_component_mask(num_components)); -} - -static void -lower_cmat_binary_op(nir_builder *b, nir_intrinsic_instr *intrin, - struct lower_cmat_state *state) -{ - nir_deref_instr *dst_slice = nir_src_as_deref(intrin->src[0]); - nir_deref_instr *src_a_slice = nir_src_as_deref(intrin->src[1]); - nir_deref_instr *src_b_slice = nir_src_as_deref(intrin->src[2]); - - nir_def *src_a = nir_load_deref(b, src_a_slice); - nir_def *src_b = nir_load_deref(b, src_b_slice); - nir_def *results[NIR_MAX_VEC_COMPONENTS]; - const unsigned num_components = glsl_get_vector_elements(dst_slice->type); - - const struct glsl_type *dst_mat_type = get_coop_type_for_slice(state, dst_slice); - ASSERTED const struct glsl_type *src_a_mat_type = get_coop_type_for_slice(state, src_a_slice); - ASSERTED const struct glsl_type *src_b_mat_type = get_coop_type_for_slice(state, src_b_slice); - - const struct glsl_cmat_description desc = - *glsl_get_cmat_description(dst_mat_type); - - assert(dst_mat_type == src_a_mat_type); - assert(dst_mat_type == src_b_mat_type); - - const unsigned bits = glsl_base_type_bit_size(desc.element_type); - const unsigned packing_factor = get_packing_factor(desc, dst_slice->type); - - for (unsigned i = 0; i < num_components; i++) { - nir_def *val_a = nir_channel(b, src_a, i); - nir_def *val_b = nir_channel(b, src_b, i); - - results[i] = - nir_pack_bits(b, nir_build_alu2(b, nir_intrinsic_alu_op(intrin), - nir_unpack_bits(b, val_a, bits), - nir_unpack_bits(b, val_b, bits)), - packing_factor * bits); - } - - nir_store_deref(b, dst_slice, nir_vec(b, results, num_components), - nir_component_mask(num_components)); -} - -static void -lower_cmat_scalar_op(nir_builder *b, nir_intrinsic_instr *intrin, - struct lower_cmat_state *state) -{ - nir_deref_instr *dst_slice = nir_src_as_deref(intrin->src[0]); - nir_deref_instr *src_slice = nir_src_as_deref(intrin->src[1]); - nir_def *scalar = intrin->src[2].ssa; - - nir_def *src = nir_load_deref(b, src_slice); - nir_def *results[NIR_MAX_VEC_COMPONENTS]; - const unsigned num_components = glsl_get_vector_elements(dst_slice->type); - - ASSERTED const struct glsl_type *dst_mat_type = get_coop_type_for_slice(state, dst_slice); - ASSERTED const struct glsl_type *src_mat_type = get_coop_type_for_slice(state, src_slice); - assert(dst_mat_type == src_mat_type); - - const struct glsl_cmat_description desc = - *glsl_get_cmat_description(dst_mat_type); - - const unsigned bits = glsl_base_type_bit_size(desc.element_type); - const unsigned packing_factor = get_packing_factor(desc, dst_slice->type); - - for (unsigned i = 0; i < num_components; i++) { - nir_def *val = nir_channel(b, src, i); - - results[i] = - nir_pack_bits(b, nir_build_alu2(b, nir_intrinsic_alu_op(intrin), - nir_unpack_bits(b, val, bits), - scalar), - packing_factor * bits); - } - - nir_store_deref(b, dst_slice, nir_vec(b, results, num_components), - nir_component_mask(num_components)); -} - -static nir_deref_instr * -lower_cmat_deref(nir_builder *b, nir_deref_instr *deref, - struct lower_cmat_state *state) -{ - nir_deref_instr *parent = nir_deref_instr_parent(deref); - if (parent) { - assert(deref->deref_type == nir_deref_type_array); - parent = lower_cmat_deref(b, parent, state); - return nir_build_deref_array(b, parent, deref->arr.index.ssa); - } else { - assert(deref->deref_type == nir_deref_type_var); - assert(deref->var); - assert(glsl_type_is_cmat(glsl_without_array(deref->var->type))); - - struct hash_entry *entry = _mesa_hash_table_search(state->vars_to_slice, deref->var); - assert(entry); - return nir_build_deref_var(b, (nir_variable *)entry->data); - } -} - -static nir_def * -lower_cmat_instr(nir_builder *b, nir_instr *instr, void *_state) -{ - struct lower_cmat_state *state = _state; - - if (instr->type == nir_instr_type_deref) { - nir_deref_instr *deref = lower_cmat_deref(b, nir_instr_as_deref(instr), state); - return &deref->def; - } - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - switch (intrin->intrinsic) { - case nir_intrinsic_cmat_load: - case nir_intrinsic_cmat_store: - lower_cmat_load_store(b, intrin, state); - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - - case nir_intrinsic_cmat_construct: { - nir_deref_instr *slice = nir_src_as_deref(intrin->src[0]); - nir_def *src = intrin->src[1].ssa; - - const struct glsl_type *mat_type = get_coop_type_for_slice(state, slice); - const struct glsl_cmat_description desc = - *glsl_get_cmat_description(mat_type); - const unsigned packing_factor = get_packing_factor(desc, slice->type); - - if (packing_factor > 1) { - src = nir_pack_bits(b, nir_replicate(b, src, packing_factor), - packing_factor * glsl_base_type_get_bit_size(desc.element_type)); - } - - const unsigned num_components = glsl_get_vector_elements(slice->type); - - nir_store_deref(b, slice, nir_replicate(b, src, num_components), - nir_component_mask(num_components)); - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - } - - case nir_intrinsic_cmat_unary_op: - lower_cmat_unary_op(b, intrin, state); - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - - case nir_intrinsic_cmat_binary_op: - lower_cmat_binary_op(b, intrin, state); - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - - case nir_intrinsic_cmat_scalar_op: - lower_cmat_scalar_op(b, intrin, state); - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - - case nir_intrinsic_cmat_length: { - const struct glsl_cmat_description desc = nir_intrinsic_cmat_desc(intrin); - const struct glsl_type *mat_type = glsl_cmat_type(&desc); - const struct glsl_type *slice_type = get_slice_type(state, mat_type); - return nir_imm_intN_t(b, (get_packing_factor(desc, slice_type) * - glsl_get_vector_elements(slice_type)), 32); - } - - case nir_intrinsic_cmat_muladd: { - nir_deref_instr *dst_slice = nir_src_as_deref(intrin->src[0]); - nir_deref_instr *A_slice = nir_src_as_deref(intrin->src[1]); - nir_deref_instr *B_slice = nir_src_as_deref(intrin->src[2]); - nir_deref_instr *accum_slice = nir_src_as_deref(intrin->src[3]); - - const struct glsl_type *dst_mat_type = get_coop_type_for_slice(state, dst_slice); - const struct glsl_cmat_description dst_desc = *glsl_get_cmat_description(dst_mat_type); - - const struct glsl_type *src_mat_type = get_coop_type_for_slice(state, A_slice); - const struct glsl_cmat_description src_desc = *glsl_get_cmat_description(src_mat_type); - - const unsigned packing_factor = get_packing_factor(dst_desc, dst_slice->type); - const unsigned num_components = glsl_get_vector_elements(dst_slice->type); - - nir_def *result = - nir_dpas_intel(b, - packing_factor * glsl_base_type_get_bit_size(dst_desc.element_type), - nir_load_deref(b, A_slice), - nir_load_deref(b, B_slice), - nir_load_deref(b, accum_slice), - .dest_type = nir_get_nir_type_for_glsl_base_type(dst_desc.element_type), - .src_type = nir_get_nir_type_for_glsl_base_type(src_desc.element_type), - .saturate = nir_intrinsic_saturate(intrin), - .cmat_signed_mask = nir_intrinsic_cmat_signed_mask(intrin), - .systolic_depth = 8, - .repeat_count = 8); - - nir_store_deref(b, dst_slice, result, - nir_component_mask(num_components)); - - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - } - - case nir_intrinsic_cmat_bitcast: { - nir_deref_instr *dst_slice = nir_src_as_deref(intrin->src[0]); - nir_deref_instr *src_slice = nir_src_as_deref(intrin->src[1]); - - const unsigned num_components = glsl_get_vector_elements(dst_slice->type); - - assert(glsl_get_vector_elements(src_slice->type) == num_components); - - nir_store_deref(b, dst_slice, nir_load_deref(b, src_slice), - nir_component_mask(num_components)); - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - } - - case nir_intrinsic_cmat_copy: - nir_copy_deref(b, - nir_src_as_deref(intrin->src[0]), - nir_src_as_deref(intrin->src[1])); - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - - case nir_intrinsic_cmat_insert: { - nir_deref_instr *dst_slice = nir_src_as_deref(intrin->src[0]); - nir_def *scalar = intrin->src[1].ssa; - nir_deref_instr *src_slice = nir_src_as_deref(intrin->src[2]); - const nir_src dst_index = intrin->src[3]; - - const struct glsl_type *dst_mat_type = get_coop_type_for_slice(state, dst_slice); - ASSERTED const struct glsl_type *src_mat_type = get_coop_type_for_slice(state, src_slice); - assert(dst_mat_type == src_mat_type); - - const struct glsl_cmat_description desc = - *glsl_get_cmat_description(dst_mat_type); - - const unsigned bits = glsl_base_type_bit_size(desc.element_type); - const unsigned packing_factor = get_packing_factor(desc, dst_slice->type); - const unsigned num_components = glsl_get_vector_elements(dst_slice->type); - - nir_def *slice_index = nir_udiv_imm(b, dst_index.ssa, packing_factor); - nir_def *vector_index = nir_umod_imm(b, dst_index.ssa, packing_factor); - nir_def *results[NIR_MAX_VEC_COMPONENTS]; - - const int slice_constant_index = nir_src_is_const(dst_index) - ? nir_src_as_uint(dst_index) / packing_factor - : -1; - - for (unsigned i = 0; i < num_components; i++) { - nir_def *val = nir_channel(b, nir_load_deref(b, src_slice), i); - nir_def *insert; - - if (slice_constant_index < 0 || slice_constant_index == i) { - if (packing_factor == 1) { - insert = scalar; - } else { - nir_def *unpacked = nir_unpack_bits(b, val, bits); - nir_def *v = nir_vector_insert(b, unpacked, scalar, vector_index); - - insert = nir_pack_bits(b, v, bits * packing_factor); - } - } else { - insert = val; - } - - results[i] = slice_constant_index < 0 - ? nir_bcsel(b, nir_ieq_imm(b, slice_index, i), insert, val) - : insert; - } - - nir_store_deref(b, dst_slice, nir_vec(b, results, num_components), - nir_component_mask(num_components)); - - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - } - - case nir_intrinsic_cmat_extract: { - nir_deref_instr *slice = nir_src_as_deref(intrin->src[0]); - const struct glsl_type *mat_type = get_coop_type_for_slice(state, slice); - nir_def *index = intrin->src[1].ssa; - - const struct glsl_cmat_description desc = - *glsl_get_cmat_description(mat_type); - - const unsigned bits = glsl_base_type_bit_size(desc.element_type); - const unsigned packing_factor = get_packing_factor(desc, slice->type); - - nir_def *src = - nir_vector_extract(b, nir_load_deref(b, slice), - nir_udiv_imm(b, index, packing_factor)); - - if (packing_factor == 1) { - return src; - } else { - return nir_vector_extract(b, - nir_unpack_bits(b, src, bits), - nir_umod_imm(b, index, packing_factor)); - } - - return NIR_LOWER_INSTR_PROGRESS_REPLACE; - } - - default: - unreachable("invalid cooperative matrix intrinsic"); - } -} - -static void -create_slice_var(struct lower_cmat_state *state, nir_variable *var, - nir_function_impl *impl) -{ - // TODO: without array - const struct glsl_type *mat_type = glsl_without_array(var->type); - - assert(glsl_type_is_cmat(mat_type)); - assert((!impl && var->data.mode == nir_var_shader_temp) || - ( impl && var->data.mode == nir_var_function_temp)); - - const struct glsl_type *slice_type = get_slice_type(state, var->type); - const char *slice_name = ralloc_asprintf(state->shader, "%s_slice", var->name); - nir_variable *slice_var = impl ? - nir_local_variable_create(impl, slice_type, slice_name) : - nir_variable_create(state->shader, var->data.mode, slice_type, slice_name); - - _mesa_hash_table_insert(state->vars_to_slice, var, slice_var); - _mesa_hash_table_insert(state->slice_coop_types, slice_var, (void *)mat_type); -} - -bool -brw_nir_lower_cmat(nir_shader *shader, unsigned subgroup_size) -{ - void *temp_ctx = ralloc_context(NULL); - - struct lower_cmat_state state = { - .shader = shader, - .slice_coop_types = _mesa_pointer_hash_table_create(temp_ctx), - .vars_to_slice = _mesa_pointer_hash_table_create(temp_ctx), - .subgroup_size = subgroup_size, - }; - - /* Create a slice array for each variable and add a map from the original - * variable back to it, so it can be reached during lowering. - * - * TODO: Cooperative matrix inside struct? - */ - nir_foreach_variable_in_shader(var, shader) { - if (glsl_type_is_cmat(glsl_without_array(var->type))) - create_slice_var(&state, var, NULL); - } - nir_foreach_function(func, shader) { - nir_foreach_function_temp_variable(var, func->impl) { - if (glsl_type_is_cmat(glsl_without_array(var->type))) - create_slice_var(&state, var, func->impl); - } - } - - bool progress = nir_shader_lower_instructions(shader, - lower_cmat_filter, - lower_cmat_instr, - &state); - - ralloc_free(temp_ctx); - - return progress; -} diff --git a/src/intel/compiler/elk/brw_nir_lower_intersection_shader.c b/src/intel/compiler/elk/brw_nir_lower_intersection_shader.c deleted file mode 100644 index b26339bdac1..00000000000 --- a/src/intel/compiler/elk/brw_nir_lower_intersection_shader.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2020 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_nir_rt.h" -#include "brw_nir_rt_builder.h" - -static nir_function_impl * -lower_any_hit_for_intersection(nir_shader *any_hit) -{ - nir_function_impl *impl = nir_shader_get_entrypoint(any_hit); - - /* Any-hit shaders need three parameters */ - assert(impl->function->num_params == 0); - nir_parameter params[] = { - { - /* A pointer to a boolean value for whether or not the hit was - * accepted. - */ - .num_components = 1, - .bit_size = 32, - }, - { - /* The hit T value */ - .num_components = 1, - .bit_size = 32, - }, - { - /* The hit kind */ - .num_components = 1, - .bit_size = 32, - }, - }; - impl->function->num_params = ARRAY_SIZE(params); - impl->function->params = - ralloc_array(any_hit, nir_parameter, ARRAY_SIZE(params)); - memcpy(impl->function->params, params, sizeof(params)); - - nir_builder build = nir_builder_at(nir_before_impl(impl)); - nir_builder *b = &build; - - nir_def *commit_ptr = nir_load_param(b, 0); - nir_def *hit_t = nir_load_param(b, 1); - nir_def *hit_kind = nir_load_param(b, 2); - - nir_deref_instr *commit = - nir_build_deref_cast(b, commit_ptr, nir_var_function_temp, - glsl_bool_type(), 0); - - nir_foreach_block_safe(block, impl) { - nir_foreach_instr_safe(instr, block) { - switch (instr->type) { - case nir_instr_type_intrinsic: { - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - switch (intrin->intrinsic) { - case nir_intrinsic_ignore_ray_intersection: - b->cursor = nir_instr_remove(&intrin->instr); - /* We put the newly emitted code inside a dummy if because it's - * going to contain a jump instruction and we don't want to - * deal with that mess here. It'll get dealt with by our - * control-flow optimization passes. - */ - nir_store_deref(b, commit, nir_imm_false(b), 0x1); - nir_push_if(b, nir_imm_true(b)); - nir_jump(b, nir_jump_return); - nir_pop_if(b, NULL); - break; - - case nir_intrinsic_terminate_ray: - /* The "normal" handling of terminateRay works fine in - * intersection shaders. - */ - break; - - case nir_intrinsic_load_ray_t_max: - nir_def_rewrite_uses(&intrin->def, - hit_t); - nir_instr_remove(&intrin->instr); - break; - - case nir_intrinsic_load_ray_hit_kind: - nir_def_rewrite_uses(&intrin->def, - hit_kind); - nir_instr_remove(&intrin->instr); - break; - - default: - break; - } - break; - } - - case nir_instr_type_jump: { - /* Stomp any halts to returns since they only return from the - * any-hit shader and not necessarily from the intersection - * shader. This is safe to do because we've already asserted - * that we only have the one function. - */ - nir_jump_instr *jump = nir_instr_as_jump(instr); - if (jump->type == nir_jump_halt) - jump->type = nir_jump_return; - break; - } - - default: - break; - } - } - } - - nir_validate_shader(any_hit, "after initial any-hit lowering"); - - nir_lower_returns_impl(impl); - - nir_validate_shader(any_hit, "after lowering returns"); - - return impl; -} - -void -brw_nir_lower_intersection_shader(nir_shader *intersection, - const nir_shader *any_hit, - const struct intel_device_info *devinfo) -{ - void *dead_ctx = ralloc_context(intersection); - - nir_function_impl *any_hit_impl = NULL; - struct hash_table *any_hit_var_remap = NULL; - if (any_hit) { - nir_shader *any_hit_tmp = nir_shader_clone(dead_ctx, any_hit); - NIR_PASS_V(any_hit_tmp, nir_opt_dce); - any_hit_impl = lower_any_hit_for_intersection(any_hit_tmp); - any_hit_var_remap = _mesa_pointer_hash_table_create(dead_ctx); - } - - nir_function_impl *impl = nir_shader_get_entrypoint(intersection); - - nir_builder build = nir_builder_at(nir_before_impl(impl)); - nir_builder *b = &build; - - nir_def *t_addr = brw_nir_rt_mem_hit_addr(b, false /* committed */); - nir_variable *commit = - nir_local_variable_create(impl, glsl_bool_type(), "ray_commit"); - nir_store_var(b, commit, nir_imm_false(b), 0x1); - - assert(impl->end_block->predecessors->entries == 1); - set_foreach(impl->end_block->predecessors, block_entry) { - struct nir_block *block = (void *)block_entry->key; - b->cursor = nir_after_block_before_jump(block); - nir_push_if(b, nir_load_var(b, commit)); - { - /* Set the "valid" bit in mem_hit */ - nir_def *ray_addr = brw_nir_rt_mem_hit_addr(b, false /* committed */); - nir_def *flags_dw_addr = nir_iadd_imm(b, ray_addr, 12); - nir_store_global(b, flags_dw_addr, 4, - nir_ior(b, nir_load_global(b, flags_dw_addr, 4, 1, 32), - nir_imm_int(b, 1 << 16)), 0x1 /* write_mask */); - - nir_accept_ray_intersection(b); - } - nir_push_else(b, NULL); - { - nir_ignore_ray_intersection(b); - } - nir_pop_if(b, NULL); - break; - } - - nir_foreach_block_safe(block, impl) { - nir_foreach_instr_safe(instr, block) { - switch (instr->type) { - case nir_instr_type_intrinsic: { - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - switch (intrin->intrinsic) { - case nir_intrinsic_report_ray_intersection: { - b->cursor = nir_instr_remove(&intrin->instr); - nir_def *hit_t = intrin->src[0].ssa; - nir_def *hit_kind = intrin->src[1].ssa; - nir_def *min_t = nir_load_ray_t_min(b); - - struct brw_nir_rt_mem_ray_defs ray_def; - brw_nir_rt_load_mem_ray(b, &ray_def, BRW_RT_BVH_LEVEL_WORLD); - - struct brw_nir_rt_mem_hit_defs hit_in = {}; - brw_nir_rt_load_mem_hit(b, &hit_in, false); - - nir_def *max_t = ray_def.t_far; - - /* bool commit_tmp = false; */ - nir_variable *commit_tmp = - nir_local_variable_create(impl, glsl_bool_type(), - "commit_tmp"); - nir_store_var(b, commit_tmp, nir_imm_false(b), 0x1); - - nir_push_if(b, nir_iand(b, nir_fge(b, hit_t, min_t), - nir_fge(b, max_t, hit_t))); - { - /* Any-hit defaults to commit */ - nir_store_var(b, commit_tmp, nir_imm_true(b), 0x1); - - if (any_hit_impl != NULL) { - nir_push_if(b, nir_inot(b, nir_load_leaf_opaque_intel(b))); - { - nir_def *params[] = { - &nir_build_deref_var(b, commit_tmp)->def, - hit_t, - hit_kind, - }; - nir_inline_function_impl(b, any_hit_impl, params, - any_hit_var_remap); - } - nir_pop_if(b, NULL); - } - - nir_push_if(b, nir_load_var(b, commit_tmp)); - { - nir_store_var(b, commit, nir_imm_true(b), 0x1); - - nir_def *ray_addr = - brw_nir_rt_mem_ray_addr(b, brw_nir_rt_stack_addr(b), BRW_RT_BVH_LEVEL_WORLD); - - nir_store_global(b, nir_iadd_imm(b, ray_addr, 16 + 12), 4, hit_t, 0x1); - nir_store_global(b, t_addr, 4, - nir_vec2(b, nir_fmin(b, hit_t, hit_in.t), hit_kind), - 0x3); - } - nir_pop_if(b, NULL); - } - nir_pop_if(b, NULL); - - nir_def *accepted = nir_load_var(b, commit_tmp); - nir_def_rewrite_uses(&intrin->def, - accepted); - break; - } - - default: - break; - } - break; - } - - default: - break; - } - } - } - nir_metadata_preserve(impl, nir_metadata_none); - - /* We did some inlining; have to re-index SSA defs */ - nir_index_ssa_defs(impl); - - ralloc_free(dead_ctx); -} diff --git a/src/intel/compiler/elk/brw_nir_lower_ray_queries.c b/src/intel/compiler/elk/brw_nir_lower_ray_queries.c deleted file mode 100644 index bcade17e803..00000000000 --- a/src/intel/compiler/elk/brw_nir_lower_ray_queries.c +++ /dev/null @@ -1,567 +0,0 @@ -/* - * Copyright (c) 2021 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_nir_rt.h" -#include "brw_nir_rt_builder.h" - -#include "nir_deref.h" - -#include "util/macros.h" - -struct lowering_state { - const struct intel_device_info *devinfo; - - nir_function_impl *impl; - - struct hash_table *queries; - uint32_t n_queries; - - struct brw_nir_rt_globals_defs globals; - nir_def *rq_globals; -}; - -struct brw_ray_query { - nir_variable *opaque_var; - nir_variable *internal_var; - uint32_t id; -}; - -#define SIZEOF_QUERY_STATE (sizeof(uint32_t)) - -static bool -need_spill_fill(struct lowering_state *state) -{ - return state->n_queries > 1; -} - -/** - * This pass converts opaque RayQuery structures from SPIRV into a vec3 where - * the first 2 elements store a global address for the query and the third - * element is an incremented counter on the number of executed - * nir_intrinsic_rq_proceed. - */ - -static void -register_opaque_var(nir_variable *opaque_var, struct lowering_state *state) -{ - struct hash_entry *entry = _mesa_hash_table_search(state->queries, opaque_var); - assert(entry == NULL); - - struct brw_ray_query *rq = rzalloc(state->queries, struct brw_ray_query); - rq->opaque_var = opaque_var; - rq->id = state->n_queries; - - unsigned aoa_size = glsl_get_aoa_size(opaque_var->type); - state->n_queries += MAX2(1, aoa_size); - - _mesa_hash_table_insert(state->queries, opaque_var, rq); -} - -static void -create_internal_var(struct brw_ray_query *rq, struct lowering_state *state) -{ - const struct glsl_type *opaque_type = rq->opaque_var->type; - const struct glsl_type *internal_type = glsl_uint16_t_type(); - - while (glsl_type_is_array(opaque_type)) { - assert(!glsl_type_is_unsized_array(opaque_type)); - internal_type = glsl_array_type(internal_type, - glsl_array_size(opaque_type), - 0); - opaque_type = glsl_get_array_element(opaque_type); - } - - rq->internal_var = nir_local_variable_create(state->impl, - internal_type, - NULL); -} - - - -static nir_def * -get_ray_query_shadow_addr(nir_builder *b, - nir_deref_instr *deref, - struct lowering_state *state, - nir_deref_instr **out_state_deref) -{ - nir_deref_path path; - nir_deref_path_init(&path, deref, NULL); - assert(path.path[0]->deref_type == nir_deref_type_var); - - nir_variable *opaque_var = nir_deref_instr_get_variable(path.path[0]); - struct hash_entry *entry = _mesa_hash_table_search(state->queries, opaque_var); - assert(entry); - - struct brw_ray_query *rq = entry->data; - - /* Base address in the shadow memory of the variable associated with this - * ray query variable. - */ - nir_def *base_addr = - nir_iadd_imm(b, state->globals.resume_sbt_addr, - brw_rt_ray_queries_shadow_stack_size(state->devinfo) * rq->id); - - bool spill_fill = need_spill_fill(state); - *out_state_deref = nir_build_deref_var(b, rq->internal_var); - - if (!spill_fill) - return NULL; - - /* Just emit code and let constant-folding go to town */ - nir_deref_instr **p = &path.path[1]; - for (; *p; p++) { - if ((*p)->deref_type == nir_deref_type_array) { - nir_def *index = (*p)->arr.index.ssa; - - /**/ - *out_state_deref = nir_build_deref_array(b, *out_state_deref, index); - - /**/ - uint64_t size = MAX2(1, glsl_get_aoa_size((*p)->type)) * - brw_rt_ray_queries_shadow_stack_size(state->devinfo); - - nir_def *mul = nir_amul_imm(b, nir_i2i64(b, index), size); - - base_addr = nir_iadd(b, base_addr, mul); - } else { - unreachable("Unsupported deref type"); - } - } - - nir_deref_path_finish(&path); - - /* Add the lane offset to the shadow memory address */ - nir_def *lane_offset = - nir_imul_imm( - b, - nir_iadd( - b, - nir_imul( - b, - brw_load_btd_dss_id(b), - brw_nir_rt_load_num_simd_lanes_per_dss(b, state->devinfo)), - brw_nir_rt_sync_stack_id(b)), - BRW_RT_SIZEOF_SHADOW_RAY_QUERY); - - return nir_iadd(b, base_addr, nir_i2i64(b, lane_offset)); -} - -static void -update_trace_ctrl_level(nir_builder *b, - nir_deref_instr *state_deref, - nir_def **out_old_ctrl, - nir_def **out_old_level, - nir_def *new_ctrl, - nir_def *new_level) -{ - nir_def *old_value = nir_load_deref(b, state_deref); - nir_def *old_ctrl = nir_ishr_imm(b, old_value, 2); - nir_def *old_level = nir_iand_imm(b, old_value, 0x3); - - if (out_old_ctrl) - *out_old_ctrl = old_ctrl; - if (out_old_level) - *out_old_level = old_level; - - if (new_ctrl) - new_ctrl = nir_i2i16(b, new_ctrl); - if (new_level) - new_level = nir_i2i16(b, new_level); - - if (new_ctrl || new_level) { - if (!new_ctrl) - new_ctrl = old_ctrl; - if (!new_level) - new_level = old_level; - - nir_def *new_value = nir_ior(b, nir_ishl_imm(b, new_ctrl, 2), new_level); - nir_store_deref(b, state_deref, new_value, 0x1); - } -} - -static void -fill_query(nir_builder *b, - nir_def *hw_stack_addr, - nir_def *shadow_stack_addr, - nir_def *ctrl) -{ - brw_nir_memcpy_global(b, hw_stack_addr, 64, shadow_stack_addr, 64, - BRW_RT_SIZEOF_RAY_QUERY); -} - -static void -spill_query(nir_builder *b, - nir_def *hw_stack_addr, - nir_def *shadow_stack_addr) -{ - brw_nir_memcpy_global(b, shadow_stack_addr, 64, hw_stack_addr, 64, - BRW_RT_SIZEOF_RAY_QUERY); -} - - -static void -lower_ray_query_intrinsic(nir_builder *b, - nir_intrinsic_instr *intrin, - struct lowering_state *state) -{ - nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]); - - b->cursor = nir_instr_remove(&intrin->instr); - - nir_deref_instr *ctrl_level_deref; - nir_def *shadow_stack_addr = - get_ray_query_shadow_addr(b, deref, state, &ctrl_level_deref); - nir_def *hw_stack_addr = - brw_nir_rt_sync_stack_addr(b, state->globals.base_mem_addr, state->devinfo); - nir_def *stack_addr = shadow_stack_addr ? shadow_stack_addr : hw_stack_addr; - - switch (intrin->intrinsic) { - case nir_intrinsic_rq_initialize: { - nir_def *as_addr = intrin->src[1].ssa; - nir_def *ray_flags = intrin->src[2].ssa; - /* From the SPIR-V spec: - * - * "Only the 8 least-significant bits of Cull Mask are used by - * this instruction - other bits are ignored. - * - * Only the 16 least-significant bits of Miss Index are used by - * this instruction - other bits are ignored." - */ - nir_def *cull_mask = nir_iand_imm(b, intrin->src[3].ssa, 0xff); - nir_def *ray_orig = intrin->src[4].ssa; - nir_def *ray_t_min = intrin->src[5].ssa; - nir_def *ray_dir = intrin->src[6].ssa; - nir_def *ray_t_max = intrin->src[7].ssa; - - nir_def *root_node_ptr = - brw_nir_rt_acceleration_structure_to_root_node(b, as_addr); - - struct brw_nir_rt_mem_ray_defs ray_defs = { - .root_node_ptr = root_node_ptr, - .ray_flags = nir_u2u16(b, ray_flags), - .ray_mask = cull_mask, - .orig = ray_orig, - .t_near = ray_t_min, - .dir = ray_dir, - .t_far = ray_t_max, - }; - - nir_def *ray_addr = - brw_nir_rt_mem_ray_addr(b, stack_addr, BRW_RT_BVH_LEVEL_WORLD); - - brw_nir_rt_query_mark_init(b, stack_addr); - brw_nir_rt_store_mem_ray_query_at_addr(b, ray_addr, &ray_defs); - - update_trace_ctrl_level(b, ctrl_level_deref, - NULL, NULL, - nir_imm_int(b, GEN_RT_TRACE_RAY_INITAL), - nir_imm_int(b, BRW_RT_BVH_LEVEL_WORLD)); - break; - } - - case nir_intrinsic_rq_proceed: { - nir_def *not_done = - nir_inot(b, brw_nir_rt_query_done(b, stack_addr)); - nir_def *not_done_then, *not_done_else; - - nir_push_if(b, not_done); - { - nir_def *ctrl, *level; - update_trace_ctrl_level(b, ctrl_level_deref, - &ctrl, &level, - NULL, - NULL); - - /* Mark the query as done because handing it over to the HW for - * processing. If the HW make any progress, it will write back some - * data and as a side effect, clear the "done" bit. If no progress is - * made, HW does not write anything back and we can use this bit to - * detect that. - */ - brw_nir_rt_query_mark_done(b, stack_addr); - - if (shadow_stack_addr) - fill_query(b, hw_stack_addr, shadow_stack_addr, ctrl); - - nir_trace_ray_intel(b, state->rq_globals, level, ctrl, .synchronous = true); - - struct brw_nir_rt_mem_hit_defs hit_in = {}; - brw_nir_rt_load_mem_hit_from_addr(b, &hit_in, hw_stack_addr, false); - - if (shadow_stack_addr) - spill_query(b, hw_stack_addr, shadow_stack_addr); - - update_trace_ctrl_level(b, ctrl_level_deref, - NULL, NULL, - nir_imm_int(b, GEN_RT_TRACE_RAY_CONTINUE), - hit_in.bvh_level); - - not_done_then = nir_inot(b, hit_in.done); - } - nir_push_else(b, NULL); - { - not_done_else = nir_imm_false(b); - } - nir_pop_if(b, NULL); - not_done = nir_if_phi(b, not_done_then, not_done_else); - nir_def_rewrite_uses(&intrin->def, not_done); - break; - } - - case nir_intrinsic_rq_confirm_intersection: { - brw_nir_memcpy_global(b, - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, true), 16, - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, false), 16, - BRW_RT_SIZEOF_HIT_INFO); - update_trace_ctrl_level(b, ctrl_level_deref, - NULL, NULL, - nir_imm_int(b, GEN_RT_TRACE_RAY_COMMIT), - nir_imm_int(b, BRW_RT_BVH_LEVEL_OBJECT)); - break; - } - - case nir_intrinsic_rq_generate_intersection: { - brw_nir_rt_generate_hit_addr(b, stack_addr, intrin->src[1].ssa); - update_trace_ctrl_level(b, ctrl_level_deref, - NULL, NULL, - nir_imm_int(b, GEN_RT_TRACE_RAY_COMMIT), - nir_imm_int(b, BRW_RT_BVH_LEVEL_OBJECT)); - break; - } - - case nir_intrinsic_rq_terminate: { - brw_nir_rt_query_mark_done(b, stack_addr); - break; - } - - case nir_intrinsic_rq_load: { - const bool committed = nir_intrinsic_committed(intrin); - - struct brw_nir_rt_mem_ray_defs world_ray_in = {}; - struct brw_nir_rt_mem_ray_defs object_ray_in = {}; - struct brw_nir_rt_mem_hit_defs hit_in = {}; - brw_nir_rt_load_mem_ray_from_addr(b, &world_ray_in, stack_addr, - BRW_RT_BVH_LEVEL_WORLD); - brw_nir_rt_load_mem_ray_from_addr(b, &object_ray_in, stack_addr, - BRW_RT_BVH_LEVEL_OBJECT); - brw_nir_rt_load_mem_hit_from_addr(b, &hit_in, stack_addr, committed); - - nir_def *sysval = NULL; - switch (nir_intrinsic_ray_query_value(intrin)) { - case nir_ray_query_value_intersection_type: - if (committed) { - /* Values we want to generate : - * - * RayQueryCommittedIntersectionNoneEXT = 0U <= hit_in.valid == false - * RayQueryCommittedIntersectionTriangleEXT = 1U <= hit_in.leaf_type == BRW_RT_BVH_NODE_TYPE_QUAD (4) - * RayQueryCommittedIntersectionGeneratedEXT = 2U <= hit_in.leaf_type == BRW_RT_BVH_NODE_TYPE_PROCEDURAL (3) - */ - sysval = - nir_bcsel(b, nir_ieq_imm(b, hit_in.leaf_type, 4), - nir_imm_int(b, 1), nir_imm_int(b, 2)); - sysval = - nir_bcsel(b, hit_in.valid, - sysval, nir_imm_int(b, 0)); - } else { - /* 0 -> triangle, 1 -> AABB */ - sysval = - nir_b2i32(b, - nir_ieq_imm(b, hit_in.leaf_type, - BRW_RT_BVH_NODE_TYPE_PROCEDURAL)); - } - break; - - case nir_ray_query_value_intersection_t: - sysval = hit_in.t; - break; - - case nir_ray_query_value_intersection_instance_custom_index: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.instance_id; - break; - } - - case nir_ray_query_value_intersection_instance_id: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.instance_index; - break; - } - - case nir_ray_query_value_intersection_instance_sbt_index: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.contribution_to_hit_group_index; - break; - } - - case nir_ray_query_value_intersection_geometry_index: { - nir_def *geometry_index_dw = - nir_load_global(b, nir_iadd_imm(b, hit_in.prim_leaf_ptr, 4), 4, - 1, 32); - sysval = nir_iand_imm(b, geometry_index_dw, BITFIELD_MASK(29)); - break; - } - - case nir_ray_query_value_intersection_primitive_index: - sysval = brw_nir_rt_load_primitive_id_from_hit(b, NULL /* is_procedural */, &hit_in); - break; - - case nir_ray_query_value_intersection_barycentrics: - sysval = hit_in.tri_bary; - break; - - case nir_ray_query_value_intersection_front_face: - sysval = hit_in.front_face; - break; - - case nir_ray_query_value_intersection_object_ray_direction: - sysval = world_ray_in.dir; - break; - - case nir_ray_query_value_intersection_object_ray_origin: - sysval = world_ray_in.orig; - break; - - case nir_ray_query_value_intersection_object_to_world: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.object_to_world[nir_intrinsic_column(intrin)]; - break; - } - - case nir_ray_query_value_intersection_world_to_object: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.world_to_object[nir_intrinsic_column(intrin)]; - break; - } - - case nir_ray_query_value_intersection_candidate_aabb_opaque: - sysval = hit_in.front_face; - break; - - case nir_ray_query_value_tmin: - sysval = world_ray_in.t_near; - break; - - case nir_ray_query_value_flags: - sysval = nir_u2u32(b, world_ray_in.ray_flags); - break; - - case nir_ray_query_value_world_ray_direction: - sysval = world_ray_in.dir; - break; - - case nir_ray_query_value_world_ray_origin: - sysval = world_ray_in.orig; - break; - - case nir_ray_query_value_intersection_triangle_vertex_positions: { - struct brw_nir_rt_bvh_primitive_leaf_positions_defs pos; - brw_nir_rt_load_bvh_primitive_leaf_positions(b, &pos, hit_in.prim_leaf_ptr); - sysval = pos.positions[nir_intrinsic_column(intrin)]; - break; - } - - default: - unreachable("Invalid ray query"); - } - - assert(sysval); - nir_def_rewrite_uses(&intrin->def, sysval); - break; - } - - default: - unreachable("Invalid intrinsic"); - } -} - -static void -lower_ray_query_impl(nir_function_impl *impl, struct lowering_state *state) -{ - nir_builder _b, *b = &_b; - _b = nir_builder_at(nir_before_impl(impl)); - - state->rq_globals = nir_load_ray_query_global_intel(b); - - brw_nir_rt_load_globals_addr(b, &state->globals, state->rq_globals); - - nir_foreach_block_safe(block, impl) { - nir_foreach_instr_safe(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - if (intrin->intrinsic != nir_intrinsic_rq_initialize && - intrin->intrinsic != nir_intrinsic_rq_terminate && - intrin->intrinsic != nir_intrinsic_rq_proceed && - intrin->intrinsic != nir_intrinsic_rq_generate_intersection && - intrin->intrinsic != nir_intrinsic_rq_confirm_intersection && - intrin->intrinsic != nir_intrinsic_rq_load) - continue; - - lower_ray_query_intrinsic(b, intrin, state); - } - } - - nir_metadata_preserve(impl, nir_metadata_none); -} - -bool -brw_nir_lower_ray_queries(nir_shader *shader, - const struct intel_device_info *devinfo) -{ - assert(exec_list_length(&shader->functions) == 1); - - struct lowering_state state = { - .devinfo = devinfo, - .impl = nir_shader_get_entrypoint(shader), - .queries = _mesa_pointer_hash_table_create(NULL), - }; - - /* Map all query variable to internal type variables */ - nir_foreach_function_temp_variable(var, state.impl) - register_opaque_var(var, &state); - hash_table_foreach(state.queries, entry) - create_internal_var(entry->data, &state); - - bool progress = state.n_queries > 0; - - if (progress) { - lower_ray_query_impl(state.impl, &state); - - nir_remove_dead_derefs(shader); - nir_remove_dead_variables(shader, - nir_var_shader_temp | nir_var_function_temp, - NULL); - - nir_metadata_preserve(state.impl, nir_metadata_none); - } - - ralloc_free(state.queries); - - return progress; -} diff --git a/src/intel/compiler/elk/brw_nir_lower_rt_intrinsics.c b/src/intel/compiler/elk/brw_nir_lower_rt_intrinsics.c deleted file mode 100644 index d3653251b74..00000000000 --- a/src/intel/compiler/elk/brw_nir_lower_rt_intrinsics.c +++ /dev/null @@ -1,386 +0,0 @@ -/* - * Copyright (c) 2020 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_nir_rt.h" -#include "brw_nir_rt_builder.h" - -static nir_def * -build_leaf_is_procedural(nir_builder *b, struct brw_nir_rt_mem_hit_defs *hit) -{ - switch (b->shader->info.stage) { - case MESA_SHADER_ANY_HIT: - /* Any-hit shaders are always compiled into intersection shaders for - * procedural geometry. If we got here in an any-hit shader, it's for - * triangles. - */ - return nir_imm_false(b); - - case MESA_SHADER_INTERSECTION: - return nir_imm_true(b); - - default: - return nir_ieq_imm(b, hit->leaf_type, - BRW_RT_BVH_NODE_TYPE_PROCEDURAL); - } -} - -static void -lower_rt_intrinsics_impl(nir_function_impl *impl, - const struct intel_device_info *devinfo) -{ - bool progress = false; - - nir_builder build = nir_builder_at(nir_before_impl(impl)); - nir_builder *b = &build; - - struct brw_nir_rt_globals_defs globals; - brw_nir_rt_load_globals(b, &globals); - - nir_def *hotzone_addr = brw_nir_rt_sw_hotzone_addr(b, devinfo); - nir_def *hotzone = nir_load_global(b, hotzone_addr, 16, 4, 32); - - gl_shader_stage stage = b->shader->info.stage; - struct brw_nir_rt_mem_ray_defs world_ray_in = {}; - struct brw_nir_rt_mem_ray_defs object_ray_in = {}; - struct brw_nir_rt_mem_hit_defs hit_in = {}; - switch (stage) { - case MESA_SHADER_ANY_HIT: - case MESA_SHADER_CLOSEST_HIT: - case MESA_SHADER_INTERSECTION: - brw_nir_rt_load_mem_hit(b, &hit_in, - stage == MESA_SHADER_CLOSEST_HIT); - brw_nir_rt_load_mem_ray(b, &object_ray_in, - BRW_RT_BVH_LEVEL_OBJECT); - FALLTHROUGH; - - case MESA_SHADER_MISS: - brw_nir_rt_load_mem_ray(b, &world_ray_in, - BRW_RT_BVH_LEVEL_WORLD); - break; - - default: - break; - } - - nir_def *thread_stack_base_addr = brw_nir_rt_sw_stack_addr(b, devinfo); - nir_def *stack_base_offset = nir_channel(b, hotzone, 0); - nir_def *stack_base_addr = - nir_iadd(b, thread_stack_base_addr, nir_u2u64(b, stack_base_offset)); - ASSERTED bool seen_scratch_base_ptr_load = false; - ASSERTED bool found_resume = false; - - nir_foreach_block(block, impl) { - nir_foreach_instr_safe(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - - b->cursor = nir_after_instr(&intrin->instr); - - nir_def *sysval = NULL; - switch (intrin->intrinsic) { - case nir_intrinsic_load_scratch_base_ptr: - assert(nir_intrinsic_base(intrin) == 1); - seen_scratch_base_ptr_load = true; - sysval = stack_base_addr; - break; - - case nir_intrinsic_btd_stack_push_intel: { - int32_t stack_size = nir_intrinsic_stack_size(intrin); - if (stack_size > 0) { - nir_def *child_stack_offset = - nir_iadd_imm(b, stack_base_offset, stack_size); - nir_store_global(b, hotzone_addr, 16, child_stack_offset, 0x1); - } - nir_instr_remove(instr); - break; - } - - case nir_intrinsic_rt_resume: - /* This is the first "interesting" instruction */ - assert(block == nir_start_block(impl)); - assert(!seen_scratch_base_ptr_load); - found_resume = true; - - int32_t stack_size = nir_intrinsic_stack_size(intrin); - if (stack_size > 0) { - stack_base_offset = - nir_iadd_imm(b, stack_base_offset, -stack_size); - nir_store_global(b, hotzone_addr, 16, stack_base_offset, 0x1); - stack_base_addr = nir_iadd(b, thread_stack_base_addr, - nir_u2u64(b, stack_base_offset)); - } - nir_instr_remove(instr); - break; - - case nir_intrinsic_load_uniform: { - /* We don't want to lower this in the launch trampoline. */ - if (stage == MESA_SHADER_COMPUTE) - break; - - sysval = brw_nir_load_global_const(b, intrin, - nir_load_btd_global_arg_addr_intel(b), - BRW_RT_PUSH_CONST_OFFSET); - - break; - } - - case nir_intrinsic_load_ray_launch_id: - sysval = nir_channels(b, hotzone, 0xe); - break; - - case nir_intrinsic_load_ray_launch_size: - sysval = globals.launch_size; - break; - - case nir_intrinsic_load_ray_world_origin: - sysval = world_ray_in.orig; - break; - - case nir_intrinsic_load_ray_world_direction: - sysval = world_ray_in.dir; - break; - - case nir_intrinsic_load_ray_object_origin: - sysval = object_ray_in.orig; - break; - - case nir_intrinsic_load_ray_object_direction: - sysval = object_ray_in.dir; - break; - - case nir_intrinsic_load_ray_t_min: - /* It shouldn't matter which we pull this from */ - sysval = world_ray_in.t_near; - break; - - case nir_intrinsic_load_ray_t_max: - if (stage == MESA_SHADER_MISS) - sysval = world_ray_in.t_far; - else - sysval = hit_in.t; - break; - - case nir_intrinsic_load_primitive_id: - sysval = brw_nir_rt_load_primitive_id_from_hit(b, - build_leaf_is_procedural(b, &hit_in), - &hit_in); - break; - - case nir_intrinsic_load_instance_id: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.instance_index; - break; - } - - case nir_intrinsic_load_ray_object_to_world: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.object_to_world[nir_intrinsic_column(intrin)]; - break; - } - - case nir_intrinsic_load_ray_world_to_object: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.world_to_object[nir_intrinsic_column(intrin)]; - break; - } - - case nir_intrinsic_load_ray_hit_kind: { - nir_def *tri_hit_kind = - nir_bcsel(b, hit_in.front_face, - nir_imm_int(b, BRW_RT_HIT_KIND_FRONT_FACE), - nir_imm_int(b, BRW_RT_HIT_KIND_BACK_FACE)); - sysval = nir_bcsel(b, build_leaf_is_procedural(b, &hit_in), - hit_in.aabb_hit_kind, tri_hit_kind); - break; - } - - case nir_intrinsic_load_ray_flags: - /* We need to fetch the original ray flags we stored in the - * leaf pointer, because the actual ray flags we get here - * will include any flags passed on the pipeline at creation - * time, and the spec for IncomingRayFlagsKHR says: - * Setting pipeline flags on the raytracing pipeline must not - * cause any corresponding flags to be set in variables with - * this decoration. - */ - sysval = nir_u2u32(b, world_ray_in.inst_leaf_ptr); - break; - - case nir_intrinsic_load_cull_mask: - sysval = nir_u2u32(b, world_ray_in.ray_mask); - break; - - case nir_intrinsic_load_ray_geometry_index: { - nir_def *geometry_index_dw = - nir_load_global(b, nir_iadd_imm(b, hit_in.prim_leaf_ptr, 4), 4, - 1, 32); - sysval = nir_iand_imm(b, geometry_index_dw, BITFIELD_MASK(29)); - break; - } - - case nir_intrinsic_load_ray_instance_custom_index: { - struct brw_nir_rt_bvh_instance_leaf_defs leaf; - brw_nir_rt_load_bvh_instance_leaf(b, &leaf, hit_in.inst_leaf_ptr); - sysval = leaf.instance_id; - break; - } - - case nir_intrinsic_load_shader_record_ptr: - /* We can't handle this intrinsic in resume shaders because the - * handle we get there won't be from the original SBT. The shader - * call lowering/splitting pass should have ensured that this - * value was spilled from the initial shader and unspilled in any - * resume shaders that need it. - */ - assert(!found_resume); - sysval = nir_load_btd_local_arg_addr_intel(b); - break; - - case nir_intrinsic_load_ray_base_mem_addr_intel: - sysval = globals.base_mem_addr; - break; - - case nir_intrinsic_load_ray_hw_stack_size_intel: - sysval = nir_imul_imm(b, globals.hw_stack_size, 64); - break; - - case nir_intrinsic_load_ray_sw_stack_size_intel: - sysval = nir_imul_imm(b, globals.sw_stack_size, 64); - break; - - case nir_intrinsic_load_ray_num_dss_rt_stacks_intel: - sysval = globals.num_dss_rt_stacks; - break; - - case nir_intrinsic_load_ray_hit_sbt_addr_intel: - sysval = globals.hit_sbt_addr; - break; - - case nir_intrinsic_load_ray_hit_sbt_stride_intel: - sysval = globals.hit_sbt_stride; - break; - - case nir_intrinsic_load_ray_miss_sbt_addr_intel: - sysval = globals.miss_sbt_addr; - break; - - case nir_intrinsic_load_ray_miss_sbt_stride_intel: - sysval = globals.miss_sbt_stride; - break; - - case nir_intrinsic_load_callable_sbt_addr_intel: - sysval = globals.call_sbt_addr; - break; - - case nir_intrinsic_load_callable_sbt_stride_intel: - sysval = globals.call_sbt_stride; - break; - - case nir_intrinsic_load_btd_resume_sbt_addr_intel: - sysval = nir_pack_64_2x32_split(b, - nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_RESUME_SBT_ADDR_LOW), - nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_RESUME_SBT_ADDR_HIGH)); - break; - - case nir_intrinsic_load_leaf_procedural_intel: - sysval = build_leaf_is_procedural(b, &hit_in); - break; - - case nir_intrinsic_load_ray_triangle_vertex_positions: { - struct brw_nir_rt_bvh_primitive_leaf_positions_defs pos; - brw_nir_rt_load_bvh_primitive_leaf_positions(b, &pos, hit_in.prim_leaf_ptr); - sysval = pos.positions[nir_intrinsic_column(intrin)]; - break; - } - - case nir_intrinsic_load_leaf_opaque_intel: { - if (stage == MESA_SHADER_INTERSECTION) { - /* In intersection shaders, the opaque bit is passed to us in - * the front_face bit. - */ - sysval = hit_in.front_face; - } else { - nir_def *flags_dw = - nir_load_global(b, nir_iadd_imm(b, hit_in.prim_leaf_ptr, 4), 4, - 1, 32); - sysval = nir_i2b(b, nir_iand_imm(b, flags_dw, 1u << 30)); - } - break; - } - - default: - continue; - } - - progress = true; - - if (sysval) { - nir_def_rewrite_uses(&intrin->def, - sysval); - nir_instr_remove(&intrin->instr); - } - } - } - - nir_metadata_preserve(impl, - progress ? - nir_metadata_none : - (nir_metadata_block_index | - nir_metadata_dominance)); -} - -/** Lower ray-tracing system values and intrinsics - * - * In most 3D shader stages, intrinsics are a fairly thin wrapper around - * hardware functionality and system values represent magic bits that come - * into the shader from FF hardware. Ray-tracing, however, looks a bit more - * like the OpenGL 1.0 world where the underlying hardware is simple and most - * of the API implementation is software. - * - * In particular, most things that are treated as system values (or built-ins - * in SPIR-V) don't get magically dropped into registers for us. Instead, we - * have to fetch them from the relevant data structures shared with the - * ray-tracing hardware. Most come from either the RT_DISPATCH_GLOBALS or - * from one of the MemHit data structures. Some, such as primitive_id require - * us to fetch the leaf address from the MemHit struct and then manually read - * the data out of the BVH. Instead of trying to emit all this code deep in - * the back-end where we can't effectively optimize it, we lower it all to - * global memory access in NIR. - * - * Once this pass is complete, the only real system values left are the two - * argument pointer system values for BTD dispatch: btd_local_arg_addr and - * btd_global_arg_addr. - */ -void -brw_nir_lower_rt_intrinsics(nir_shader *nir, - const struct intel_device_info *devinfo) -{ - nir_foreach_function_impl(impl, nir) { - lower_rt_intrinsics_impl(impl, devinfo); - } -} diff --git a/src/intel/compiler/elk/brw_nir_lower_shader_calls.c b/src/intel/compiler/elk/brw_nir_lower_shader_calls.c deleted file mode 100644 index 739e6375023..00000000000 --- a/src/intel/compiler/elk/brw_nir_lower_shader_calls.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright © 2020 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_nir_rt.h" -#include "brw_nir_rt_builder.h" -#include "nir_phi_builder.h" - -UNUSED static bool -no_load_scratch_base_ptr_intrinsic(nir_shader *shader) -{ - nir_foreach_function_impl(impl, shader) { - nir_foreach_block(block, impl) { - nir_foreach_instr(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - if (intrin->intrinsic == nir_intrinsic_load_scratch_base_ptr) - return false; - } - } - } - - return true; -} - -/** Insert the appropriate return instruction at the end of the shader */ -void -brw_nir_lower_shader_returns(nir_shader *shader) -{ - nir_function_impl *impl = nir_shader_get_entrypoint(shader); - - /* Reserve scratch space at the start of the shader's per-thread scratch - * space for the return BINDLESS_SHADER_RECORD address and data payload. - * When a shader is called, the calling shader will write the return BSR - * address in this region of the callee's scratch space. - * - * We could also put it at the end of the caller's scratch space. However, - * doing this way means that a shader never accesses its caller's scratch - * space unless given an explicit pointer (such as for ray payloads). It - * also makes computing the address easier given that we want to apply an - * alignment to the scratch offset to ensure we can make alignment - * assumptions in the called shader. - * - * This isn't needed for ray-gen shaders because they end the thread and - * never return to the calling trampoline shader. - */ - assert(no_load_scratch_base_ptr_intrinsic(shader)); - if (shader->info.stage != MESA_SHADER_RAYGEN) - shader->scratch_size += BRW_BTD_STACK_CALLEE_DATA_SIZE; - - nir_builder b = nir_builder_create(impl); - - set_foreach(impl->end_block->predecessors, block_entry) { - struct nir_block *block = (void *)block_entry->key; - b.cursor = nir_after_block_before_jump(block); - - switch (shader->info.stage) { - case MESA_SHADER_RAYGEN: - /* A raygen shader is always the root of the shader call tree. When - * it ends, we retire the bindless stack ID and no further shaders - * will be executed. - */ - assert(impl->end_block->predecessors->entries == 1); - brw_nir_btd_retire(&b); - break; - - case MESA_SHADER_ANY_HIT: - /* The default action of an any-hit shader is to accept the ray - * intersection. Any-hit shaders may have more than one exit. Only - * the final "normal" exit will actually need to accept the - * intersection as any others should come from nir_jump_halt - * instructions inserted after ignore_ray_intersection or - * terminate_ray or the like. However, inserting an accept after - * the ignore or terminate is safe because it'll get deleted later. - */ - nir_accept_ray_intersection(&b); - break; - - case MESA_SHADER_CALLABLE: - case MESA_SHADER_MISS: - case MESA_SHADER_CLOSEST_HIT: - /* Callable, miss, and closest-hit shaders don't take any special - * action at the end. They simply return back to the previous shader - * in the call stack. - */ - assert(impl->end_block->predecessors->entries == 1); - brw_nir_btd_return(&b); - break; - - case MESA_SHADER_INTERSECTION: - /* This will be handled by brw_nir_lower_intersection_shader */ - break; - - default: - unreachable("Invalid callable shader stage"); - } - } - - nir_metadata_preserve(impl, nir_metadata_block_index | - nir_metadata_dominance); -} - -static void -store_resume_addr(nir_builder *b, nir_intrinsic_instr *call) -{ - uint32_t call_idx = nir_intrinsic_call_idx(call); - uint32_t offset = nir_intrinsic_stack_size(call); - - /* First thing on the called shader's stack is the resume address - * followed by a pointer to the payload. - */ - nir_def *resume_record_addr = - nir_iadd_imm(b, nir_load_btd_resume_sbt_addr_intel(b), - call_idx * BRW_BTD_RESUME_SBT_STRIDE); - /* By the time we get here, any remaining shader/function memory - * pointers have been lowered to SSA values. - */ - nir_def *payload_addr = - nir_get_shader_call_payload_src(call)->ssa; - brw_nir_rt_store_scratch(b, offset, BRW_BTD_STACK_ALIGN, - nir_vec2(b, resume_record_addr, payload_addr), - 0xf /* write_mask */); - - nir_btd_stack_push_intel(b, offset); -} - -static bool -lower_shader_trace_ray_instr(struct nir_builder *b, nir_instr *instr, void *data) -{ - struct brw_bs_prog_key *key = data; - - if (instr->type != nir_instr_type_intrinsic) - return false; - - /* Leave nir_intrinsic_rt_resume to be lowered by - * brw_nir_lower_rt_intrinsics() - */ - nir_intrinsic_instr *call = nir_instr_as_intrinsic(instr); - if (call->intrinsic != nir_intrinsic_rt_trace_ray) - return false; - - b->cursor = nir_instr_remove(instr); - - store_resume_addr(b, call); - - nir_def *as_addr = call->src[0].ssa; - nir_def *ray_flags = call->src[1].ssa; - /* From the SPIR-V spec: - * - * "Only the 8 least-significant bits of Cull Mask are used by this - * instruction - other bits are ignored. - * - * Only the 4 least-significant bits of SBT Offset and SBT Stride are - * used by this instruction - other bits are ignored. - * - * Only the 16 least-significant bits of Miss Index are used by this - * instruction - other bits are ignored." - */ - nir_def *cull_mask = nir_iand_imm(b, call->src[2].ssa, 0xff); - nir_def *sbt_offset = nir_iand_imm(b, call->src[3].ssa, 0xf); - nir_def *sbt_stride = nir_iand_imm(b, call->src[4].ssa, 0xf); - nir_def *miss_index = nir_iand_imm(b, call->src[5].ssa, 0xffff); - nir_def *ray_orig = call->src[6].ssa; - nir_def *ray_t_min = call->src[7].ssa; - nir_def *ray_dir = call->src[8].ssa; - nir_def *ray_t_max = call->src[9].ssa; - - nir_def *root_node_ptr = - brw_nir_rt_acceleration_structure_to_root_node(b, as_addr); - - /* The hardware packet requires an address to the first element of the - * hit SBT. - * - * In order to calculate this, we must multiply the "SBT Offset" - * provided to OpTraceRay by the SBT stride provided for the hit SBT in - * the call to vkCmdTraceRay() and add that to the base address of the - * hit SBT. This stride is not to be confused with the "SBT Stride" - * provided to OpTraceRay which is in units of this stride. It's a - * rather terrible overload of the word "stride". The hardware docs - * calls the SPIR-V stride value the "shader index multiplier" which is - * a much more sane name. - */ - nir_def *hit_sbt_stride_B = - nir_load_ray_hit_sbt_stride_intel(b); - nir_def *hit_sbt_offset_B = - nir_imul(b, sbt_offset, nir_u2u32(b, hit_sbt_stride_B)); - nir_def *hit_sbt_addr = - nir_iadd(b, nir_load_ray_hit_sbt_addr_intel(b), - nir_u2u64(b, hit_sbt_offset_B)); - - /* The hardware packet takes an address to the miss BSR. */ - nir_def *miss_sbt_stride_B = - nir_load_ray_miss_sbt_stride_intel(b); - nir_def *miss_sbt_offset_B = - nir_imul(b, miss_index, nir_u2u32(b, miss_sbt_stride_B)); - nir_def *miss_sbt_addr = - nir_iadd(b, nir_load_ray_miss_sbt_addr_intel(b), - nir_u2u64(b, miss_sbt_offset_B)); - - struct brw_nir_rt_mem_ray_defs ray_defs = { - .root_node_ptr = root_node_ptr, - /* Combine the shader value given to traceRayEXT() with the pipeline - * creation value VkPipelineCreateFlags. - */ - .ray_flags = nir_ior_imm(b, nir_u2u16(b, ray_flags), key->pipeline_ray_flags), - .ray_mask = cull_mask, - .hit_group_sr_base_ptr = hit_sbt_addr, - .hit_group_sr_stride = nir_u2u16(b, hit_sbt_stride_B), - .miss_sr_ptr = miss_sbt_addr, - .orig = ray_orig, - .t_near = ray_t_min, - .dir = ray_dir, - .t_far = ray_t_max, - .shader_index_multiplier = sbt_stride, - /* The instance leaf pointer is unused in the top level BVH traversal - * since we always start from the root node. We can reuse that field to - * store the ray_flags handed to traceRayEXT(). This will be reloaded - * when the shader accesses gl_IncomingRayFlagsEXT (see - * nir_intrinsic_load_ray_flags brw_nir_lower_rt_intrinsic.c) - */ - .inst_leaf_ptr = nir_u2u64(b, ray_flags), - }; - brw_nir_rt_store_mem_ray(b, &ray_defs, BRW_RT_BVH_LEVEL_WORLD); - - nir_trace_ray_intel(b, - nir_load_btd_global_arg_addr_intel(b), - nir_imm_int(b, BRW_RT_BVH_LEVEL_WORLD), - nir_imm_int(b, GEN_RT_TRACE_RAY_INITAL), - .synchronous = false); - return true; -} - -static bool -lower_shader_call_instr(struct nir_builder *b, nir_intrinsic_instr *call, - void *data) -{ - if (call->intrinsic != nir_intrinsic_rt_execute_callable) - return false; - - b->cursor = nir_instr_remove(&call->instr); - - store_resume_addr(b, call); - - nir_def *sbt_offset32 = - nir_imul(b, call->src[0].ssa, - nir_u2u32(b, nir_load_callable_sbt_stride_intel(b))); - nir_def *sbt_addr = - nir_iadd(b, nir_load_callable_sbt_addr_intel(b), - nir_u2u64(b, sbt_offset32)); - brw_nir_btd_spawn(b, sbt_addr); - return true; -} - -bool -brw_nir_lower_shader_calls(nir_shader *shader, struct brw_bs_prog_key *key) -{ - bool a = nir_shader_instructions_pass(shader, - lower_shader_trace_ray_instr, - nir_metadata_none, - key); - bool b = nir_shader_intrinsics_pass(shader, lower_shader_call_instr, - nir_metadata_block_index | - nir_metadata_dominance, - NULL); - return a || b; -} - -/** Creates a trivial return shader - * - * In most cases this shader doesn't actually do anything. It just needs to - * return to the caller. - * - * By default, our HW has the ability to handle the fact that a shader is not - * available and will execute the next following shader in the tracing call. - * For instance, a RAYGEN shader traces a ray, the tracing generates a hit, - * but there is no ANYHIT shader available. The HW should follow up by - * execution the CLOSESTHIT shader. - * - * This default behavior can be changed through the RT_CTRL register - * (privileged access) and when NULL shader checks are disabled, the HW will - * instead call the call stack handler (this shader). This is what i915 is - * doing as part of Wa_14013202645. - * - * In order to ensure the call to the CLOSESTHIT shader, this shader needs to - * commit the ray and will not proceed with the BTD return. Similarly when the - * same thing happen with the INTERSECTION shader, we should just carry on the - * ray traversal with the continue operation. - * - */ -nir_shader * -brw_nir_create_trivial_return_shader(const struct brw_compiler *compiler, - void *mem_ctx) -{ - const nir_shader_compiler_options *nir_options = - compiler->nir_options[MESA_SHADER_CALLABLE]; - - nir_builder _b = nir_builder_init_simple_shader(MESA_SHADER_CALLABLE, - nir_options, - "RT Trivial Return"); - nir_builder *b = &_b; - - ralloc_steal(mem_ctx, b->shader); - nir_shader *nir = b->shader; - - NIR_PASS_V(nir, brw_nir_lower_shader_returns); - - return nir; -} diff --git a/src/intel/compiler/elk/brw_nir_rt.c b/src/intel/compiler/elk/brw_nir_rt.c deleted file mode 100644 index b5daa1090de..00000000000 --- a/src/intel/compiler/elk/brw_nir_rt.c +++ /dev/null @@ -1,536 +0,0 @@ -/* - * Copyright © 2020 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "intel_nir.h" -#include "brw_nir_rt.h" -#include "brw_nir_rt_builder.h" -#include "intel_nir.h" - -static bool -resize_deref(nir_builder *b, nir_deref_instr *deref, - unsigned num_components, unsigned bit_size) -{ - if (deref->def.num_components == num_components && - deref->def.bit_size == bit_size) - return false; - - /* NIR requires array indices have to match the deref bit size */ - if (deref->def.bit_size != bit_size && - (deref->deref_type == nir_deref_type_array || - deref->deref_type == nir_deref_type_ptr_as_array)) { - b->cursor = nir_before_instr(&deref->instr); - nir_def *idx; - if (nir_src_is_const(deref->arr.index)) { - idx = nir_imm_intN_t(b, nir_src_as_int(deref->arr.index), bit_size); - } else { - idx = nir_i2iN(b, deref->arr.index.ssa, bit_size); - } - nir_src_rewrite(&deref->arr.index, idx); - } - - deref->def.num_components = num_components; - deref->def.bit_size = bit_size; - - return true; -} - -static bool -lower_rt_io_derefs(nir_shader *shader) -{ - nir_function_impl *impl = nir_shader_get_entrypoint(shader); - - bool progress = false; - - unsigned num_shader_call_vars = 0; - nir_foreach_variable_with_modes(var, shader, nir_var_shader_call_data) - num_shader_call_vars++; - - unsigned num_ray_hit_attrib_vars = 0; - nir_foreach_variable_with_modes(var, shader, nir_var_ray_hit_attrib) - num_ray_hit_attrib_vars++; - - /* At most one payload is allowed because it's an input. Technically, this - * is also true for hit attribute variables. However, after we inline an - * any-hit shader into an intersection shader, we can end up with multiple - * hit attribute variables. They'll end up mapping to a cast from the same - * base pointer so this is fine. - */ - assert(num_shader_call_vars <= 1); - - nir_builder b = nir_builder_at(nir_before_impl(impl)); - - nir_def *call_data_addr = NULL; - if (num_shader_call_vars > 0) { - assert(shader->scratch_size >= BRW_BTD_STACK_CALLEE_DATA_SIZE); - call_data_addr = - brw_nir_rt_load_scratch(&b, BRW_BTD_STACK_CALL_DATA_PTR_OFFSET, 8, - 1, 64); - progress = true; - } - - gl_shader_stage stage = shader->info.stage; - nir_def *hit_attrib_addr = NULL; - if (num_ray_hit_attrib_vars > 0) { - assert(stage == MESA_SHADER_ANY_HIT || - stage == MESA_SHADER_CLOSEST_HIT || - stage == MESA_SHADER_INTERSECTION); - nir_def *hit_addr = - brw_nir_rt_mem_hit_addr(&b, stage == MESA_SHADER_CLOSEST_HIT); - /* The vec2 barycentrics are in 2nd and 3rd dwords of MemHit */ - nir_def *bary_addr = nir_iadd_imm(&b, hit_addr, 4); - hit_attrib_addr = nir_bcsel(&b, nir_load_leaf_procedural_intel(&b), - brw_nir_rt_hit_attrib_data_addr(&b), - bary_addr); - progress = true; - } - - nir_foreach_block(block, impl) { - nir_foreach_instr_safe(instr, block) { - if (instr->type != nir_instr_type_deref) - continue; - - nir_deref_instr *deref = nir_instr_as_deref(instr); - if (nir_deref_mode_is(deref, nir_var_shader_call_data)) { - deref->modes = nir_var_function_temp; - if (deref->deref_type == nir_deref_type_var) { - b.cursor = nir_before_instr(&deref->instr); - nir_deref_instr *cast = - nir_build_deref_cast(&b, call_data_addr, - nir_var_function_temp, - deref->var->type, 0); - nir_def_rewrite_uses(&deref->def, - &cast->def); - nir_instr_remove(&deref->instr); - progress = true; - } - } else if (nir_deref_mode_is(deref, nir_var_ray_hit_attrib)) { - deref->modes = nir_var_function_temp; - if (deref->deref_type == nir_deref_type_var) { - b.cursor = nir_before_instr(&deref->instr); - nir_deref_instr *cast = - nir_build_deref_cast(&b, hit_attrib_addr, - nir_var_function_temp, - deref->type, 0); - nir_def_rewrite_uses(&deref->def, - &cast->def); - nir_instr_remove(&deref->instr); - progress = true; - } - } - - /* We're going to lower all function_temp memory to scratch using - * 64-bit addresses. We need to resize all our derefs first or else - * nir_lower_explicit_io will have a fit. - */ - if (nir_deref_mode_is(deref, nir_var_function_temp) && - resize_deref(&b, deref, 1, 64)) - progress = true; - } - } - - if (progress) { - nir_metadata_preserve(impl, nir_metadata_block_index | - nir_metadata_dominance); - } else { - nir_metadata_preserve(impl, nir_metadata_all); - } - - return progress; -} - -/** Lowers ray-tracing shader I/O and scratch access - * - * SPV_KHR_ray_tracing adds three new types of I/O, each of which need their - * own bit of special care: - * - * - Shader payload data: This is represented by the IncomingCallableData - * and IncomingRayPayload storage classes which are both represented by - * nir_var_call_data in NIR. There is at most one of these per-shader and - * they contain payload data passed down the stack from the parent shader - * when it calls executeCallable() or traceRay(). In our implementation, - * the actual storage lives in the calling shader's scratch space and we're - * passed a pointer to it. - * - * - Hit attribute data: This is represented by the HitAttribute storage - * class in SPIR-V and nir_var_ray_hit_attrib in NIR. For triangle - * geometry, it's supposed to contain two floats which are the barycentric - * coordinates. For AABS/procedural geometry, it contains the hit data - * written out by the intersection shader. In our implementation, it's a - * 64-bit pointer which points either to the u/v area of the relevant - * MemHit data structure or the space right after the HW ray stack entry. - * - * - Shader record buffer data: This allows read-only access to the data - * stored in the SBT right after the bindless shader handles. It's - * effectively a UBO with a magic address. Coming out of spirv_to_nir, - * we get a nir_intrinsic_load_shader_record_ptr which is cast to a - * nir_var_mem_global deref and all access happens through that. The - * shader_record_ptr system value is handled in brw_nir_lower_rt_intrinsics - * and we assume nir_lower_explicit_io is called elsewhere thanks to - * VK_KHR_buffer_device_address so there's really nothing to do here. - * - * We also handle lowering any remaining function_temp variables to scratch at - * this point. This gets rid of any remaining arrays and also takes care of - * the sending side of ray payloads where we pass pointers to a function_temp - * variable down the call stack. - */ -static void -lower_rt_io_and_scratch(nir_shader *nir) -{ - /* First, we to ensure all the I/O variables have explicit types. Because - * these are shader-internal and don't come in from outside, they don't - * have an explicit memory layout and we have to assign them one. - */ - NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, - nir_var_function_temp | - nir_var_shader_call_data | - nir_var_ray_hit_attrib, - glsl_get_natural_size_align_bytes); - - /* Now patch any derefs to I/O vars */ - NIR_PASS_V(nir, lower_rt_io_derefs); - - /* Finally, lower any remaining function_temp, mem_constant, or - * ray_hit_attrib access to 64-bit global memory access. - */ - NIR_PASS_V(nir, nir_lower_explicit_io, - nir_var_function_temp | - nir_var_mem_constant | - nir_var_ray_hit_attrib, - nir_address_format_64bit_global); -} - -static void -build_terminate_ray(nir_builder *b) -{ - nir_def *skip_closest_hit = nir_test_mask(b, nir_load_ray_flags(b), - BRW_RT_RAY_FLAG_SKIP_CLOSEST_HIT_SHADER); - nir_push_if(b, skip_closest_hit); - { - /* The shader that calls traceRay() is unable to access any ray hit - * information except for that which is explicitly written into the ray - * payload by shaders invoked during the trace. If there's no closest- - * hit shader, then accepting the hit has no observable effect; it's - * just extra memory traffic for no reason. - */ - brw_nir_btd_return(b); - nir_jump(b, nir_jump_halt); - } - nir_push_else(b, NULL); - { - /* The closest hit shader is in the same shader group as the any-hit - * shader that we're currently in. We can get the address for its SBT - * handle by looking at the shader record pointer and subtracting the - * size of a SBT handle. The BINDLESS_SHADER_RECORD for a closest hit - * shader is the first one in the SBT handle. - */ - nir_def *closest_hit = - nir_iadd_imm(b, nir_load_shader_record_ptr(b), - -BRW_RT_SBT_HANDLE_SIZE); - - brw_nir_rt_commit_hit(b); - brw_nir_btd_spawn(b, closest_hit); - nir_jump(b, nir_jump_halt); - } - nir_pop_if(b, NULL); -} - -/** Lowers away ray walk intrinsics - * - * This lowers terminate_ray, ignore_ray_intersection, and the NIR-specific - * accept_ray_intersection intrinsics to the appropriate Intel-specific - * intrinsics. - */ -static bool -lower_ray_walk_intrinsics(nir_shader *shader, - const struct intel_device_info *devinfo) -{ - assert(shader->info.stage == MESA_SHADER_ANY_HIT || - shader->info.stage == MESA_SHADER_INTERSECTION); - - nir_function_impl *impl = nir_shader_get_entrypoint(shader); - - nir_builder b = nir_builder_create(impl); - - bool progress = false; - nir_foreach_block_safe(block, impl) { - nir_foreach_instr_safe(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - - switch (intrin->intrinsic) { - case nir_intrinsic_ignore_ray_intersection: { - b.cursor = nir_instr_remove(&intrin->instr); - - /* We put the newly emitted code inside a dummy if because it's - * going to contain a jump instruction and we don't want to deal - * with that mess here. It'll get dealt with by our control-flow - * optimization passes. - */ - nir_push_if(&b, nir_imm_true(&b)); - nir_trace_ray_intel(&b, - nir_load_btd_global_arg_addr_intel(&b), - nir_imm_int(&b, BRW_RT_BVH_LEVEL_OBJECT), - nir_imm_int(&b, GEN_RT_TRACE_RAY_CONTINUE), - .synchronous = false); - nir_jump(&b, nir_jump_halt); - nir_pop_if(&b, NULL); - progress = true; - break; - } - - case nir_intrinsic_accept_ray_intersection: { - b.cursor = nir_instr_remove(&intrin->instr); - - nir_def *terminate = nir_test_mask(&b, nir_load_ray_flags(&b), - BRW_RT_RAY_FLAG_TERMINATE_ON_FIRST_HIT); - nir_push_if(&b, terminate); - { - build_terminate_ray(&b); - } - nir_push_else(&b, NULL); - { - nir_trace_ray_intel(&b, - nir_load_btd_global_arg_addr_intel(&b), - nir_imm_int(&b, BRW_RT_BVH_LEVEL_OBJECT), - nir_imm_int(&b, GEN_RT_TRACE_RAY_COMMIT), - .synchronous = false); - nir_jump(&b, nir_jump_halt); - } - nir_pop_if(&b, NULL); - progress = true; - break; - } - - case nir_intrinsic_terminate_ray: { - b.cursor = nir_instr_remove(&intrin->instr); - build_terminate_ray(&b); - progress = true; - break; - } - - default: - break; - } - } - } - - if (progress) { - nir_metadata_preserve(impl, nir_metadata_none); - } else { - nir_metadata_preserve(impl, nir_metadata_all); - } - - return progress; -} - -void -brw_nir_lower_raygen(nir_shader *nir) -{ - assert(nir->info.stage == MESA_SHADER_RAYGEN); - NIR_PASS_V(nir, brw_nir_lower_shader_returns); - lower_rt_io_and_scratch(nir); -} - -void -brw_nir_lower_any_hit(nir_shader *nir, const struct intel_device_info *devinfo) -{ - assert(nir->info.stage == MESA_SHADER_ANY_HIT); - NIR_PASS_V(nir, brw_nir_lower_shader_returns); - NIR_PASS_V(nir, lower_ray_walk_intrinsics, devinfo); - lower_rt_io_and_scratch(nir); -} - -void -brw_nir_lower_closest_hit(nir_shader *nir) -{ - assert(nir->info.stage == MESA_SHADER_CLOSEST_HIT); - NIR_PASS_V(nir, brw_nir_lower_shader_returns); - lower_rt_io_and_scratch(nir); -} - -void -brw_nir_lower_miss(nir_shader *nir) -{ - assert(nir->info.stage == MESA_SHADER_MISS); - NIR_PASS_V(nir, brw_nir_lower_shader_returns); - lower_rt_io_and_scratch(nir); -} - -void -brw_nir_lower_callable(nir_shader *nir) -{ - assert(nir->info.stage == MESA_SHADER_CALLABLE); - NIR_PASS_V(nir, brw_nir_lower_shader_returns); - lower_rt_io_and_scratch(nir); -} - -void -brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection, - const nir_shader *any_hit, - const struct intel_device_info *devinfo) -{ - assert(intersection->info.stage == MESA_SHADER_INTERSECTION); - assert(any_hit == NULL || any_hit->info.stage == MESA_SHADER_ANY_HIT); - NIR_PASS_V(intersection, brw_nir_lower_shader_returns); - NIR_PASS_V(intersection, brw_nir_lower_intersection_shader, - any_hit, devinfo); - NIR_PASS_V(intersection, lower_ray_walk_intrinsics, devinfo); - lower_rt_io_and_scratch(intersection); -} - -static nir_def * -build_load_uniform(nir_builder *b, unsigned offset, - unsigned num_components, unsigned bit_size) -{ - return nir_load_uniform(b, num_components, bit_size, nir_imm_int(b, 0), - .base = offset, - .range = num_components * bit_size / 8); -} - -#define load_trampoline_param(b, name, num_components, bit_size) \ - build_load_uniform((b), offsetof(struct brw_rt_raygen_trampoline_params, name), \ - (num_components), (bit_size)) - -nir_shader * -brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler, - void *mem_ctx) -{ - const struct intel_device_info *devinfo = compiler->devinfo; - const nir_shader_compiler_options *nir_options = - compiler->nir_options[MESA_SHADER_COMPUTE]; - - STATIC_ASSERT(sizeof(struct brw_rt_raygen_trampoline_params) == 32); - - nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, - nir_options, - "RT Ray-Gen Trampoline"); - ralloc_steal(mem_ctx, b.shader); - - b.shader->info.workgroup_size_variable = true; - - /* The RT global data and raygen BINDLESS_SHADER_RECORD addresses are - * passed in as push constants in the first register. We deal with the - * raygen BSR address here; the global data we'll deal with later. - */ - b.shader->num_uniforms = 32; - nir_def *raygen_param_bsr_addr = - load_trampoline_param(&b, raygen_bsr_addr, 1, 64); - nir_def *is_indirect = - nir_i2b(&b, load_trampoline_param(&b, is_indirect, 1, 8)); - nir_def *local_shift = - nir_u2u32(&b, load_trampoline_param(&b, local_group_size_log2, 3, 8)); - - nir_def *raygen_indirect_bsr_addr; - nir_push_if(&b, is_indirect); - { - raygen_indirect_bsr_addr = - nir_load_global_constant(&b, raygen_param_bsr_addr, - 8 /* align */, - 1 /* components */, - 64 /* bit_size */); - } - nir_pop_if(&b, NULL); - - nir_def *raygen_bsr_addr = - nir_if_phi(&b, raygen_indirect_bsr_addr, raygen_param_bsr_addr); - - nir_def *global_id = nir_load_workgroup_id_zero_base(&b); - nir_def *simd_channel = nir_load_subgroup_invocation(&b); - nir_def *local_x = - nir_ubfe(&b, simd_channel, nir_imm_int(&b, 0), - nir_channel(&b, local_shift, 0)); - nir_def *local_y = - nir_ubfe(&b, simd_channel, nir_channel(&b, local_shift, 0), - nir_channel(&b, local_shift, 1)); - nir_def *local_z = - nir_ubfe(&b, simd_channel, - nir_iadd(&b, nir_channel(&b, local_shift, 0), - nir_channel(&b, local_shift, 1)), - nir_channel(&b, local_shift, 2)); - nir_def *launch_id = - nir_iadd(&b, nir_ishl(&b, global_id, local_shift), - nir_vec3(&b, local_x, local_y, local_z)); - - nir_def *launch_size = nir_load_ray_launch_size(&b); - nir_push_if(&b, nir_ball(&b, nir_ult(&b, launch_id, launch_size))); - { - nir_store_global(&b, brw_nir_rt_sw_hotzone_addr(&b, devinfo), 16, - nir_vec4(&b, nir_imm_int(&b, 0), /* Stack ptr */ - nir_channel(&b, launch_id, 0), - nir_channel(&b, launch_id, 1), - nir_channel(&b, launch_id, 2)), - 0xf /* write mask */); - - brw_nir_btd_spawn(&b, raygen_bsr_addr); - } - nir_push_else(&b, NULL); - { - /* Even though these invocations aren't being used for anything, the - * hardware allocated stack IDs for them. They need to retire them. - */ - brw_nir_btd_retire(&b); - } - nir_pop_if(&b, NULL); - - nir_shader *nir = b.shader; - nir->info.name = ralloc_strdup(nir, "RT: TraceRay trampoline"); - nir_validate_shader(nir, "in brw_nir_create_raygen_trampoline"); - - struct brw_nir_compiler_opts opts = {}; - brw_preprocess_nir(compiler, nir, &opts); - - NIR_PASS_V(nir, brw_nir_lower_rt_intrinsics, devinfo); - - b = nir_builder_create(nir_shader_get_entrypoint(b.shader)); - /* brw_nir_lower_rt_intrinsics will leave us with a btd_global_arg_addr - * intrinsic which doesn't exist in compute shaders. We also created one - * above when we generated the BTD spawn intrinsic. Now we go through and - * replace them with a uniform load. - */ - nir_foreach_block(block, b.impl) { - nir_foreach_instr_safe(instr, block) { - if (instr->type != nir_instr_type_intrinsic) - continue; - - nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); - if (intrin->intrinsic != nir_intrinsic_load_btd_global_arg_addr_intel) - continue; - - b.cursor = nir_before_instr(&intrin->instr); - nir_def *global_arg_addr = - load_trampoline_param(&b, rt_disp_globals_addr, 1, 64); - nir_def_rewrite_uses(&intrin->def, - global_arg_addr); - nir_instr_remove(instr); - } - } - - NIR_PASS_V(nir, brw_nir_lower_cs_intrinsics, devinfo, NULL); - - const bool is_scalar = true; - brw_nir_optimize(nir, is_scalar, devinfo); - - return nir; -} diff --git a/src/intel/compiler/elk/brw_nir_rt.h b/src/intel/compiler/elk/brw_nir_rt.h deleted file mode 100644 index 4215d348e0c..00000000000 --- a/src/intel/compiler/elk/brw_nir_rt.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright © 2020 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef BRW_NIR_RT_H -#define BRW_NIR_RT_H - -#include "brw_nir.h" -#include "brw_rt.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void brw_nir_lower_raygen(nir_shader *nir); -void brw_nir_lower_any_hit(nir_shader *nir, - const struct intel_device_info *devinfo); -void brw_nir_lower_closest_hit(nir_shader *nir); -void brw_nir_lower_miss(nir_shader *nir); -void brw_nir_lower_callable(nir_shader *nir); -void brw_nir_lower_combined_intersection_any_hit(nir_shader *intersection, - const nir_shader *any_hit, - const struct intel_device_info *devinfo); - -/* We reserve the first 16B of the stack for callee data pointers */ -#define BRW_BTD_STACK_RESUME_BSR_ADDR_OFFSET 0 -#define BRW_BTD_STACK_CALL_DATA_PTR_OFFSET 8 -#define BRW_BTD_STACK_CALLEE_DATA_SIZE 16 - -/* We require the stack to be 8B aligned at the start of a shader */ -#define BRW_BTD_STACK_ALIGN 8 - -bool brw_nir_lower_ray_queries(nir_shader *shader, - const struct intel_device_info *devinfo); - -void brw_nir_lower_shader_returns(nir_shader *shader); - -bool brw_nir_lower_shader_calls(nir_shader *shader, struct brw_bs_prog_key *key); - -void brw_nir_lower_rt_intrinsics(nir_shader *shader, - const struct intel_device_info *devinfo); -void brw_nir_lower_intersection_shader(nir_shader *intersection, - const nir_shader *any_hit, - const struct intel_device_info *devinfo); - -nir_shader * -brw_nir_create_raygen_trampoline(const struct brw_compiler *compiler, - void *mem_ctx); -nir_shader * -brw_nir_create_trivial_return_shader(const struct brw_compiler *compiler, - void *mem_ctx); - -#ifdef __cplusplus -} -#endif - -#endif /* BRW_NIR_RT_H */ diff --git a/src/intel/compiler/elk/brw_nir_rt_builder.h b/src/intel/compiler/elk/brw_nir_rt_builder.h deleted file mode 100644 index 3f8189e4155..00000000000 --- a/src/intel/compiler/elk/brw_nir_rt_builder.h +++ /dev/null @@ -1,990 +0,0 @@ -/* - * Copyright © 2020 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef BRW_NIR_RT_BUILDER_H -#define BRW_NIR_RT_BUILDER_H - -/* This file provides helpers to access memory based data structures that the - * RT hardware reads/writes and their locations. - * - * See also "Memory Based Data Structures for Ray Tracing" (BSpec 47547) and - * "Ray Tracing Address Computation for Memory Resident Structures" (BSpec - * 47550). - */ - -#include "brw_rt.h" -#include "nir_builder.h" - -#define is_access_for_builder(b) \ - ((b)->shader->info.stage == MESA_SHADER_FRAGMENT ? \ - ACCESS_INCLUDE_HELPERS : 0) - -static inline nir_def * -brw_nir_rt_load(nir_builder *b, nir_def *addr, unsigned align, - unsigned components, unsigned bit_size) -{ - return nir_build_load_global(b, components, bit_size, addr, - .align_mul = align, - .access = is_access_for_builder(b)); -} - -static inline void -brw_nir_rt_store(nir_builder *b, nir_def *addr, unsigned align, - nir_def *value, unsigned write_mask) -{ - nir_build_store_global(b, value, addr, - .align_mul = align, - .write_mask = (write_mask) & - BITFIELD_MASK(value->num_components), - .access = is_access_for_builder(b)); -} - -static inline nir_def * -brw_nir_rt_load_const(nir_builder *b, unsigned components, - nir_def *addr, nir_def *pred) -{ - return nir_load_global_const_block_intel(b, components, addr, pred); -} - -static inline nir_def * -brw_load_btd_dss_id(nir_builder *b) -{ - return nir_load_topology_id_intel(b, .base = BRW_TOPOLOGY_ID_DSS); -} - -static inline nir_def * -brw_nir_rt_load_num_simd_lanes_per_dss(nir_builder *b, - const struct intel_device_info *devinfo) -{ - return nir_imm_int(b, devinfo->num_thread_per_eu * - devinfo->max_eus_per_subslice * - 16 /* The RT computation is based off SIMD16 */); -} - -static inline nir_def * -brw_load_eu_thread_simd(nir_builder *b) -{ - return nir_load_topology_id_intel(b, .base = BRW_TOPOLOGY_ID_EU_THREAD_SIMD); -} - -static inline nir_def * -brw_nir_rt_async_stack_id(nir_builder *b) -{ - return nir_iadd(b, nir_umul_32x16(b, nir_load_ray_num_dss_rt_stacks_intel(b), - brw_load_btd_dss_id(b)), - nir_load_btd_stack_id_intel(b)); -} - -static inline nir_def * -brw_nir_rt_sync_stack_id(nir_builder *b) -{ - return brw_load_eu_thread_simd(b); -} - -/* We have our own load/store scratch helpers because they emit a global - * memory read or write based on the scratch_base_ptr system value rather - * than a load/store_scratch intrinsic. - */ -static inline nir_def * -brw_nir_rt_load_scratch(nir_builder *b, uint32_t offset, unsigned align, - unsigned num_components, unsigned bit_size) -{ - nir_def *addr = - nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 64, 1), offset); - return brw_nir_rt_load(b, addr, MIN2(align, BRW_BTD_STACK_ALIGN), - num_components, bit_size); -} - -static inline void -brw_nir_rt_store_scratch(nir_builder *b, uint32_t offset, unsigned align, - nir_def *value, nir_component_mask_t write_mask) -{ - nir_def *addr = - nir_iadd_imm(b, nir_load_scratch_base_ptr(b, 1, 64, 1), offset); - brw_nir_rt_store(b, addr, MIN2(align, BRW_BTD_STACK_ALIGN), - value, write_mask); -} - -static inline void -brw_nir_btd_spawn(nir_builder *b, nir_def *record_addr) -{ - nir_btd_spawn_intel(b, nir_load_btd_global_arg_addr_intel(b), record_addr); -} - -static inline void -brw_nir_btd_retire(nir_builder *b) -{ - nir_btd_retire_intel(b); -} - -/** This is a pseudo-op which does a bindless return - * - * It loads the return address from the stack and calls btd_spawn to spawn the - * resume shader. - */ -static inline void -brw_nir_btd_return(struct nir_builder *b) -{ - nir_def *resume_addr = - brw_nir_rt_load_scratch(b, BRW_BTD_STACK_RESUME_BSR_ADDR_OFFSET, - 8 /* align */, 1, 64); - brw_nir_btd_spawn(b, resume_addr); -} - -static inline void -assert_def_size(nir_def *def, unsigned num_components, unsigned bit_size) -{ - assert(def->num_components == num_components); - assert(def->bit_size == bit_size); -} - -static inline nir_def * -brw_nir_num_rt_stacks(nir_builder *b, - const struct intel_device_info *devinfo) -{ - return nir_imul_imm(b, nir_load_ray_num_dss_rt_stacks_intel(b), - intel_device_info_dual_subslice_id_bound(devinfo)); -} - -static inline nir_def * -brw_nir_rt_sw_hotzone_addr(nir_builder *b, - const struct intel_device_info *devinfo) -{ - nir_def *offset32 = - nir_imul_imm(b, brw_nir_rt_async_stack_id(b), - BRW_RT_SIZEOF_HOTZONE); - - offset32 = nir_iadd(b, offset32, nir_ineg(b, - nir_imul_imm(b, brw_nir_num_rt_stacks(b, devinfo), - BRW_RT_SIZEOF_HOTZONE))); - - return nir_iadd(b, nir_load_ray_base_mem_addr_intel(b), - nir_i2i64(b, offset32)); -} - -static inline nir_def * -brw_nir_rt_sync_stack_addr(nir_builder *b, - nir_def *base_mem_addr, - const struct intel_device_info *devinfo) -{ - /* For Ray queries (Synchronous Ray Tracing), the formula is similar but - * goes down from rtMemBasePtr : - * - * syncBase = RTDispatchGlobals.rtMemBasePtr - * - (DSSID * NUM_SIMD_LANES_PER_DSS + SyncStackID + 1) - * * syncStackSize - * - * We assume that we can calculate a 32-bit offset first and then add it - * to the 64-bit base address at the end. - */ - nir_def *offset32 = - nir_imul(b, - nir_iadd(b, - nir_imul(b, brw_load_btd_dss_id(b), - brw_nir_rt_load_num_simd_lanes_per_dss(b, devinfo)), - nir_iadd_imm(b, brw_nir_rt_sync_stack_id(b), 1)), - nir_imm_int(b, BRW_RT_SIZEOF_RAY_QUERY)); - return nir_isub(b, base_mem_addr, nir_u2u64(b, offset32)); -} - -static inline nir_def * -brw_nir_rt_stack_addr(nir_builder *b) -{ - /* From the BSpec "Address Computation for Memory Based Data Structures: - * Ray and TraversalStack (Async Ray Tracing)": - * - * stackBase = RTDispatchGlobals.rtMemBasePtr - * + (DSSID * RTDispatchGlobals.numDSSRTStacks + stackID) - * * RTDispatchGlobals.stackSizePerRay // 64B aligned - * - * We assume that we can calculate a 32-bit offset first and then add it - * to the 64-bit base address at the end. - */ - nir_def *offset32 = - nir_imul(b, brw_nir_rt_async_stack_id(b), - nir_load_ray_hw_stack_size_intel(b)); - return nir_iadd(b, nir_load_ray_base_mem_addr_intel(b), - nir_u2u64(b, offset32)); -} - -static inline nir_def * -brw_nir_rt_mem_hit_addr_from_addr(nir_builder *b, - nir_def *stack_addr, - bool committed) -{ - return nir_iadd_imm(b, stack_addr, committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); -} - -static inline nir_def * -brw_nir_rt_mem_hit_addr(nir_builder *b, bool committed) -{ - return nir_iadd_imm(b, brw_nir_rt_stack_addr(b), - committed ? 0 : BRW_RT_SIZEOF_HIT_INFO); -} - -static inline nir_def * -brw_nir_rt_hit_attrib_data_addr(nir_builder *b) -{ - return nir_iadd_imm(b, brw_nir_rt_stack_addr(b), - BRW_RT_OFFSETOF_HIT_ATTRIB_DATA); -} - -static inline nir_def * -brw_nir_rt_mem_ray_addr(nir_builder *b, - nir_def *stack_addr, - enum brw_rt_bvh_level bvh_level) -{ - /* From the BSpec "Address Computation for Memory Based Data Structures: - * Ray and TraversalStack (Async Ray Tracing)": - * - * rayBase = stackBase + sizeof(HitInfo) * 2 // 64B aligned - * rayPtr = rayBase + bvhLevel * sizeof(Ray); // 64B aligned - * - * In Vulkan, we always have exactly two levels of BVH: World and Object. - */ - uint32_t offset = BRW_RT_SIZEOF_HIT_INFO * 2 + - bvh_level * BRW_RT_SIZEOF_RAY; - return nir_iadd_imm(b, stack_addr, offset); -} - -static inline nir_def * -brw_nir_rt_sw_stack_addr(nir_builder *b, - const struct intel_device_info *devinfo) -{ - nir_def *addr = nir_load_ray_base_mem_addr_intel(b); - - nir_def *offset32 = nir_imul(b, brw_nir_num_rt_stacks(b, devinfo), - nir_load_ray_hw_stack_size_intel(b)); - addr = nir_iadd(b, addr, nir_u2u64(b, offset32)); - - nir_def *offset_in_stack = - nir_imul(b, nir_u2u64(b, brw_nir_rt_async_stack_id(b)), - nir_u2u64(b, nir_load_ray_sw_stack_size_intel(b))); - - return nir_iadd(b, addr, offset_in_stack); -} - -static inline nir_def * -nir_unpack_64_4x16_split_z(nir_builder *b, nir_def *val) -{ - return nir_unpack_32_2x16_split_x(b, nir_unpack_64_2x32_split_y(b, val)); -} - -struct brw_nir_rt_globals_defs { - nir_def *base_mem_addr; - nir_def *call_stack_handler_addr; - nir_def *hw_stack_size; - nir_def *num_dss_rt_stacks; - nir_def *hit_sbt_addr; - nir_def *hit_sbt_stride; - nir_def *miss_sbt_addr; - nir_def *miss_sbt_stride; - nir_def *sw_stack_size; - nir_def *launch_size; - nir_def *call_sbt_addr; - nir_def *call_sbt_stride; - nir_def *resume_sbt_addr; -}; - -static inline void -brw_nir_rt_load_globals_addr(nir_builder *b, - struct brw_nir_rt_globals_defs *defs, - nir_def *addr) -{ - nir_def *data; - data = brw_nir_rt_load_const(b, 16, addr, nir_imm_true(b)); - defs->base_mem_addr = nir_pack_64_2x32(b, nir_trim_vector(b, data, 2)); - - defs->call_stack_handler_addr = - nir_pack_64_2x32(b, nir_channels(b, data, 0x3 << 2)); - - defs->hw_stack_size = nir_channel(b, data, 4); - defs->num_dss_rt_stacks = nir_iand_imm(b, nir_channel(b, data, 5), 0xffff); - defs->hit_sbt_addr = - nir_pack_64_2x32_split(b, nir_channel(b, data, 8), - nir_extract_i16(b, nir_channel(b, data, 9), - nir_imm_int(b, 0))); - defs->hit_sbt_stride = - nir_unpack_32_2x16_split_y(b, nir_channel(b, data, 9)); - defs->miss_sbt_addr = - nir_pack_64_2x32_split(b, nir_channel(b, data, 10), - nir_extract_i16(b, nir_channel(b, data, 11), - nir_imm_int(b, 0))); - defs->miss_sbt_stride = - nir_unpack_32_2x16_split_y(b, nir_channel(b, data, 11)); - defs->sw_stack_size = nir_channel(b, data, 12); - defs->launch_size = nir_channels(b, data, 0x7u << 13); - - data = brw_nir_rt_load_const(b, 8, nir_iadd_imm(b, addr, 64), nir_imm_true(b)); - defs->call_sbt_addr = - nir_pack_64_2x32_split(b, nir_channel(b, data, 0), - nir_extract_i16(b, nir_channel(b, data, 1), - nir_imm_int(b, 0))); - defs->call_sbt_stride = - nir_unpack_32_2x16_split_y(b, nir_channel(b, data, 1)); - - defs->resume_sbt_addr = - nir_pack_64_2x32(b, nir_channels(b, data, 0x3 << 2)); -} - -static inline void -brw_nir_rt_load_globals(nir_builder *b, - struct brw_nir_rt_globals_defs *defs) -{ - brw_nir_rt_load_globals_addr(b, defs, nir_load_btd_global_arg_addr_intel(b)); -} - -static inline nir_def * -brw_nir_rt_unpack_leaf_ptr(nir_builder *b, nir_def *vec2) -{ - /* Hit record leaf pointers are 42-bit and assumed to be in 64B chunks. - * This leaves 22 bits at the top for other stuff. - */ - nir_def *ptr64 = nir_imul_imm(b, nir_pack_64_2x32(b, vec2), 64); - - /* The top 16 bits (remember, we shifted by 6 already) contain garbage - * that we need to get rid of. - */ - nir_def *ptr_lo = nir_unpack_64_2x32_split_x(b, ptr64); - nir_def *ptr_hi = nir_unpack_64_2x32_split_y(b, ptr64); - ptr_hi = nir_extract_i16(b, ptr_hi, nir_imm_int(b, 0)); - return nir_pack_64_2x32_split(b, ptr_lo, ptr_hi); -} - -/** - * MemHit memory layout (BSpec 47547) : - * - * name bits description - * - t 32 hit distance of current hit (or initial traversal distance) - * - u 32 barycentric hit coordinates - * - v 32 barycentric hit coordinates - * - primIndexDelta 16 prim index delta for compressed meshlets and quads - * - valid 1 set if there is a hit - * - leafType 3 type of node primLeafPtr is pointing to - * - primLeafIndex 4 index of the hit primitive inside the leaf - * - bvhLevel 3 the instancing level at which the hit occured - * - frontFace 1 whether we hit the front-facing side of a triangle (also used to pass opaque flag when calling intersection shaders) - * - pad0 4 unused bits - * - primLeafPtr 42 pointer to BVH leaf node (multiple of 64 bytes) - * - hitGroupRecPtr0 22 LSB of hit group record of the hit triangle (multiple of 16 bytes) - * - instLeafPtr 42 pointer to BVH instance leaf node (in multiple of 64 bytes) - * - hitGroupRecPtr1 22 MSB of hit group record of the hit triangle (multiple of 32 bytes) - */ -struct brw_nir_rt_mem_hit_defs { - nir_def *t; - nir_def *tri_bary; /**< Only valid for triangle geometry */ - nir_def *aabb_hit_kind; /**< Only valid for AABB geometry */ - nir_def *valid; - nir_def *leaf_type; - nir_def *prim_index_delta; - nir_def *prim_leaf_index; - nir_def *bvh_level; - nir_def *front_face; - nir_def *done; /**< Only for ray queries */ - nir_def *prim_leaf_ptr; - nir_def *inst_leaf_ptr; -}; - -static inline void -brw_nir_rt_load_mem_hit_from_addr(nir_builder *b, - struct brw_nir_rt_mem_hit_defs *defs, - nir_def *stack_addr, - bool committed) -{ - nir_def *hit_addr = - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, committed); - - nir_def *data = brw_nir_rt_load(b, hit_addr, 16, 4, 32); - defs->t = nir_channel(b, data, 0); - defs->aabb_hit_kind = nir_channel(b, data, 1); - defs->tri_bary = nir_channels(b, data, 0x6); - nir_def *bitfield = nir_channel(b, data, 3); - defs->prim_index_delta = - nir_ubitfield_extract(b, bitfield, nir_imm_int(b, 0), nir_imm_int(b, 16)); - defs->valid = nir_i2b(b, nir_iand_imm(b, bitfield, 1u << 16)); - defs->leaf_type = - nir_ubitfield_extract(b, bitfield, nir_imm_int(b, 17), nir_imm_int(b, 3)); - defs->prim_leaf_index = - nir_ubitfield_extract(b, bitfield, nir_imm_int(b, 20), nir_imm_int(b, 4)); - defs->bvh_level = - nir_ubitfield_extract(b, bitfield, nir_imm_int(b, 24), nir_imm_int(b, 3)); - defs->front_face = nir_i2b(b, nir_iand_imm(b, bitfield, 1 << 27)); - defs->done = nir_i2b(b, nir_iand_imm(b, bitfield, 1 << 28)); - - data = brw_nir_rt_load(b, nir_iadd_imm(b, hit_addr, 16), 16, 4, 32); - defs->prim_leaf_ptr = - brw_nir_rt_unpack_leaf_ptr(b, nir_channels(b, data, 0x3 << 0)); - defs->inst_leaf_ptr = - brw_nir_rt_unpack_leaf_ptr(b, nir_channels(b, data, 0x3 << 2)); -} - -static inline void -brw_nir_rt_load_mem_hit(nir_builder *b, - struct brw_nir_rt_mem_hit_defs *defs, - bool committed) -{ - brw_nir_rt_load_mem_hit_from_addr(b, defs, brw_nir_rt_stack_addr(b), - committed); -} - -static inline void -brw_nir_memcpy_global(nir_builder *b, - nir_def *dst_addr, uint32_t dst_align, - nir_def *src_addr, uint32_t src_align, - uint32_t size) -{ - /* We're going to copy in 16B chunks */ - assert(size % 16 == 0); - dst_align = MIN2(dst_align, 16); - src_align = MIN2(src_align, 16); - - for (unsigned offset = 0; offset < size; offset += 16) { - nir_def *data = - brw_nir_rt_load(b, nir_iadd_imm(b, src_addr, offset), 16, - 4, 32); - brw_nir_rt_store(b, nir_iadd_imm(b, dst_addr, offset), 16, - data, 0xf /* write_mask */); - } -} - -static inline void -brw_nir_memclear_global(nir_builder *b, - nir_def *dst_addr, uint32_t dst_align, - uint32_t size) -{ - /* We're going to copy in 16B chunks */ - assert(size % 16 == 0); - dst_align = MIN2(dst_align, 16); - - nir_def *zero = nir_imm_ivec4(b, 0, 0, 0, 0); - for (unsigned offset = 0; offset < size; offset += 16) { - brw_nir_rt_store(b, nir_iadd_imm(b, dst_addr, offset), dst_align, - zero, 0xf /* write_mask */); - } -} - -static inline nir_def * -brw_nir_rt_query_done(nir_builder *b, nir_def *stack_addr) -{ - struct brw_nir_rt_mem_hit_defs hit_in = {}; - brw_nir_rt_load_mem_hit_from_addr(b, &hit_in, stack_addr, - false /* committed */); - - return hit_in.done; -} - -static inline void -brw_nir_rt_set_dword_bit_at(nir_builder *b, - nir_def *addr, - uint32_t addr_offset, - uint32_t bit) -{ - nir_def *dword_addr = nir_iadd_imm(b, addr, addr_offset); - nir_def *dword = brw_nir_rt_load(b, dword_addr, 4, 1, 32); - brw_nir_rt_store(b, dword_addr, 4, nir_ior_imm(b, dword, 1u << bit), 0x1); -} - -static inline void -brw_nir_rt_query_mark_done(nir_builder *b, nir_def *stack_addr) -{ - brw_nir_rt_set_dword_bit_at(b, - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, - false /* committed */), - 4 * 3 /* dword offset */, 28 /* bit */); -} - -/* This helper clears the 3rd dword of the MemHit structure where the valid - * bit is located. - */ -static inline void -brw_nir_rt_query_mark_init(nir_builder *b, nir_def *stack_addr) -{ - nir_def *dword_addr; - - for (uint32_t i = 0; i < 2; i++) { - dword_addr = - nir_iadd_imm(b, - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, - i == 0 /* committed */), - 4 * 3 /* dword offset */); - brw_nir_rt_store(b, dword_addr, 4, nir_imm_int(b, 0), 0x1); - } -} - -/* This helper is pretty much a memcpy of uncommitted into committed hit - * structure, just adding the valid bit. - */ -static inline void -brw_nir_rt_commit_hit_addr(nir_builder *b, nir_def *stack_addr) -{ - nir_def *dst_addr = - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, true /* committed */); - nir_def *src_addr = - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, false /* committed */); - - for (unsigned offset = 0; offset < BRW_RT_SIZEOF_HIT_INFO; offset += 16) { - nir_def *data = - brw_nir_rt_load(b, nir_iadd_imm(b, src_addr, offset), 16, 4, 32); - - if (offset == 0) { - data = nir_vec4(b, - nir_channel(b, data, 0), - nir_channel(b, data, 1), - nir_channel(b, data, 2), - nir_ior_imm(b, - nir_channel(b, data, 3), - 0x1 << 16 /* valid */)); - - /* Also write the potential hit as we change it. */ - brw_nir_rt_store(b, nir_iadd_imm(b, src_addr, offset), 16, - data, 0xf /* write_mask */); - } - - brw_nir_rt_store(b, nir_iadd_imm(b, dst_addr, offset), 16, - data, 0xf /* write_mask */); - } -} - -static inline void -brw_nir_rt_commit_hit(nir_builder *b) -{ - nir_def *stack_addr = brw_nir_rt_stack_addr(b); - brw_nir_rt_commit_hit_addr(b, stack_addr); -} - -static inline void -brw_nir_rt_generate_hit_addr(nir_builder *b, nir_def *stack_addr, nir_def *t_val) -{ - nir_def *committed_addr = - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, true /* committed */); - nir_def *potential_addr = - brw_nir_rt_mem_hit_addr_from_addr(b, stack_addr, false /* committed */); - - /* Set: - * - * potential.t = t_val; - * potential.valid = true; - */ - nir_def *potential_hit_dwords_0_3 = - brw_nir_rt_load(b, potential_addr, 16, 4, 32); - potential_hit_dwords_0_3 = - nir_vec4(b, - t_val, - nir_channel(b, potential_hit_dwords_0_3, 1), - nir_channel(b, potential_hit_dwords_0_3, 2), - nir_ior_imm(b, nir_channel(b, potential_hit_dwords_0_3, 3), - (0x1 << 16) /* valid */)); - brw_nir_rt_store(b, potential_addr, 16, potential_hit_dwords_0_3, 0xf /* write_mask */); - - /* Set: - * - * committed.t = t_val; - * committed.u = 0.0f; - * committed.v = 0.0f; - * committed.valid = true; - * committed.leaf_type = potential.leaf_type; - * committed.bvh_level = BRW_RT_BVH_LEVEL_OBJECT; - * committed.front_face = false; - * committed.prim_leaf_index = 0; - * committed.done = false; - */ - nir_def *committed_hit_dwords_0_3 = - brw_nir_rt_load(b, committed_addr, 16, 4, 32); - committed_hit_dwords_0_3 = - nir_vec4(b, - t_val, - nir_imm_float(b, 0.0f), - nir_imm_float(b, 0.0f), - nir_ior_imm(b, - nir_ior_imm(b, nir_channel(b, potential_hit_dwords_0_3, 3), 0x000e0000), - (0x1 << 16) /* valid */ | - (BRW_RT_BVH_LEVEL_OBJECT << 24) /* leaf_type */)); - brw_nir_rt_store(b, committed_addr, 16, committed_hit_dwords_0_3, 0xf /* write_mask */); - - /* Set: - * - * committed.prim_leaf_ptr = potential.prim_leaf_ptr; - * committed.inst_leaf_ptr = potential.inst_leaf_ptr; - */ - brw_nir_memcpy_global(b, - nir_iadd_imm(b, committed_addr, 16), 16, - nir_iadd_imm(b, potential_addr, 16), 16, - 16); -} - -struct brw_nir_rt_mem_ray_defs { - nir_def *orig; - nir_def *dir; - nir_def *t_near; - nir_def *t_far; - nir_def *root_node_ptr; - nir_def *ray_flags; - nir_def *hit_group_sr_base_ptr; - nir_def *hit_group_sr_stride; - nir_def *miss_sr_ptr; - nir_def *shader_index_multiplier; - nir_def *inst_leaf_ptr; - nir_def *ray_mask; -}; - -static inline void -brw_nir_rt_store_mem_ray_query_at_addr(nir_builder *b, - nir_def *ray_addr, - const struct brw_nir_rt_mem_ray_defs *defs) -{ - assert_def_size(defs->orig, 3, 32); - assert_def_size(defs->dir, 3, 32); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 0), 16, - nir_vec4(b, nir_channel(b, defs->orig, 0), - nir_channel(b, defs->orig, 1), - nir_channel(b, defs->orig, 2), - nir_channel(b, defs->dir, 0)), - ~0 /* write mask */); - - assert_def_size(defs->t_near, 1, 32); - assert_def_size(defs->t_far, 1, 32); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 16), 16, - nir_vec4(b, nir_channel(b, defs->dir, 1), - nir_channel(b, defs->dir, 2), - defs->t_near, - defs->t_far), - ~0 /* write mask */); - - assert_def_size(defs->root_node_ptr, 1, 64); - assert_def_size(defs->ray_flags, 1, 16); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 32), 16, - nir_vec2(b, nir_unpack_64_2x32_split_x(b, defs->root_node_ptr), - nir_pack_32_2x16_split(b, - nir_unpack_64_4x16_split_z(b, defs->root_node_ptr), - defs->ray_flags)), - 0x3 /* write mask */); - - /* leaf_ptr is optional */ - nir_def *inst_leaf_ptr; - if (defs->inst_leaf_ptr) { - inst_leaf_ptr = defs->inst_leaf_ptr; - } else { - inst_leaf_ptr = nir_imm_int64(b, 0); - } - - assert_def_size(inst_leaf_ptr, 1, 64); - assert_def_size(defs->ray_mask, 1, 32); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 56), 8, - nir_vec2(b, nir_unpack_64_2x32_split_x(b, inst_leaf_ptr), - nir_pack_32_2x16_split(b, - nir_unpack_64_4x16_split_z(b, inst_leaf_ptr), - nir_unpack_32_2x16_split_x(b, defs->ray_mask))), - ~0 /* write mask */); -} - -static inline void -brw_nir_rt_store_mem_ray(nir_builder *b, - const struct brw_nir_rt_mem_ray_defs *defs, - enum brw_rt_bvh_level bvh_level) -{ - nir_def *ray_addr = - brw_nir_rt_mem_ray_addr(b, brw_nir_rt_stack_addr(b), bvh_level); - - assert_def_size(defs->orig, 3, 32); - assert_def_size(defs->dir, 3, 32); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 0), 16, - nir_vec4(b, nir_channel(b, defs->orig, 0), - nir_channel(b, defs->orig, 1), - nir_channel(b, defs->orig, 2), - nir_channel(b, defs->dir, 0)), - ~0 /* write mask */); - - assert_def_size(defs->t_near, 1, 32); - assert_def_size(defs->t_far, 1, 32); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 16), 16, - nir_vec4(b, nir_channel(b, defs->dir, 1), - nir_channel(b, defs->dir, 2), - defs->t_near, - defs->t_far), - ~0 /* write mask */); - - assert_def_size(defs->root_node_ptr, 1, 64); - assert_def_size(defs->ray_flags, 1, 16); - assert_def_size(defs->hit_group_sr_base_ptr, 1, 64); - assert_def_size(defs->hit_group_sr_stride, 1, 16); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 32), 16, - nir_vec4(b, nir_unpack_64_2x32_split_x(b, defs->root_node_ptr), - nir_pack_32_2x16_split(b, - nir_unpack_64_4x16_split_z(b, defs->root_node_ptr), - defs->ray_flags), - nir_unpack_64_2x32_split_x(b, defs->hit_group_sr_base_ptr), - nir_pack_32_2x16_split(b, - nir_unpack_64_4x16_split_z(b, defs->hit_group_sr_base_ptr), - defs->hit_group_sr_stride)), - ~0 /* write mask */); - - /* leaf_ptr is optional */ - nir_def *inst_leaf_ptr; - if (defs->inst_leaf_ptr) { - inst_leaf_ptr = defs->inst_leaf_ptr; - } else { - inst_leaf_ptr = nir_imm_int64(b, 0); - } - - assert_def_size(defs->miss_sr_ptr, 1, 64); - assert_def_size(defs->shader_index_multiplier, 1, 32); - assert_def_size(inst_leaf_ptr, 1, 64); - assert_def_size(defs->ray_mask, 1, 32); - brw_nir_rt_store(b, nir_iadd_imm(b, ray_addr, 48), 16, - nir_vec4(b, nir_unpack_64_2x32_split_x(b, defs->miss_sr_ptr), - nir_pack_32_2x16_split(b, - nir_unpack_64_4x16_split_z(b, defs->miss_sr_ptr), - nir_unpack_32_2x16_split_x(b, - nir_ishl(b, defs->shader_index_multiplier, - nir_imm_int(b, 8)))), - nir_unpack_64_2x32_split_x(b, inst_leaf_ptr), - nir_pack_32_2x16_split(b, - nir_unpack_64_4x16_split_z(b, inst_leaf_ptr), - nir_unpack_32_2x16_split_x(b, defs->ray_mask))), - ~0 /* write mask */); -} - -static inline void -brw_nir_rt_load_mem_ray_from_addr(nir_builder *b, - struct brw_nir_rt_mem_ray_defs *defs, - nir_def *ray_base_addr, - enum brw_rt_bvh_level bvh_level) -{ - nir_def *ray_addr = brw_nir_rt_mem_ray_addr(b, - ray_base_addr, - bvh_level); - - nir_def *data[4] = { - brw_nir_rt_load(b, nir_iadd_imm(b, ray_addr, 0), 16, 4, 32), - brw_nir_rt_load(b, nir_iadd_imm(b, ray_addr, 16), 16, 4, 32), - brw_nir_rt_load(b, nir_iadd_imm(b, ray_addr, 32), 16, 4, 32), - brw_nir_rt_load(b, nir_iadd_imm(b, ray_addr, 48), 16, 4, 32), - }; - - defs->orig = nir_trim_vector(b, data[0], 3); - defs->dir = nir_vec3(b, nir_channel(b, data[0], 3), - nir_channel(b, data[1], 0), - nir_channel(b, data[1], 1)); - defs->t_near = nir_channel(b, data[1], 2); - defs->t_far = nir_channel(b, data[1], 3); - defs->root_node_ptr = - nir_pack_64_2x32_split(b, nir_channel(b, data[2], 0), - nir_extract_i16(b, nir_channel(b, data[2], 1), - nir_imm_int(b, 0))); - defs->ray_flags = - nir_unpack_32_2x16_split_y(b, nir_channel(b, data[2], 1)); - defs->hit_group_sr_base_ptr = - nir_pack_64_2x32_split(b, nir_channel(b, data[2], 2), - nir_extract_i16(b, nir_channel(b, data[2], 3), - nir_imm_int(b, 0))); - defs->hit_group_sr_stride = - nir_unpack_32_2x16_split_y(b, nir_channel(b, data[2], 3)); - defs->miss_sr_ptr = - nir_pack_64_2x32_split(b, nir_channel(b, data[3], 0), - nir_extract_i16(b, nir_channel(b, data[3], 1), - nir_imm_int(b, 0))); - defs->shader_index_multiplier = - nir_ushr(b, nir_unpack_32_2x16_split_y(b, nir_channel(b, data[3], 1)), - nir_imm_int(b, 8)); - defs->inst_leaf_ptr = - nir_pack_64_2x32_split(b, nir_channel(b, data[3], 2), - nir_extract_i16(b, nir_channel(b, data[3], 3), - nir_imm_int(b, 0))); - defs->ray_mask = - nir_unpack_32_2x16_split_y(b, nir_channel(b, data[3], 3)); -} - -static inline void -brw_nir_rt_load_mem_ray(nir_builder *b, - struct brw_nir_rt_mem_ray_defs *defs, - enum brw_rt_bvh_level bvh_level) -{ - brw_nir_rt_load_mem_ray_from_addr(b, defs, brw_nir_rt_stack_addr(b), - bvh_level); -} - -struct brw_nir_rt_bvh_instance_leaf_defs { - nir_def *shader_index; - nir_def *contribution_to_hit_group_index; - nir_def *world_to_object[4]; - nir_def *instance_id; - nir_def *instance_index; - nir_def *object_to_world[4]; -}; - -static inline void -brw_nir_rt_load_bvh_instance_leaf(nir_builder *b, - struct brw_nir_rt_bvh_instance_leaf_defs *defs, - nir_def *leaf_addr) -{ - nir_def *leaf_desc = brw_nir_rt_load(b, leaf_addr, 4, 2, 32); - - defs->shader_index = - nir_iand_imm(b, nir_channel(b, leaf_desc, 0), (1 << 24) - 1); - defs->contribution_to_hit_group_index = - nir_iand_imm(b, nir_channel(b, leaf_desc, 1), (1 << 24) - 1); - - defs->world_to_object[0] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 16), 4, 3, 32); - defs->world_to_object[1] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 28), 4, 3, 32); - defs->world_to_object[2] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 40), 4, 3, 32); - /* The last column of the matrices is swapped between the two probably - * because it makes it easier/faster for hardware somehow. - */ - defs->object_to_world[3] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 52), 4, 3, 32); - - nir_def *data = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 64), 4, 4, 32); - defs->instance_id = nir_channel(b, data, 2); - defs->instance_index = nir_channel(b, data, 3); - - defs->object_to_world[0] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 80), 4, 3, 32); - defs->object_to_world[1] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 92), 4, 3, 32); - defs->object_to_world[2] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 104), 4, 3, 32); - defs->world_to_object[3] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 116), 4, 3, 32); -} - -struct brw_nir_rt_bvh_primitive_leaf_defs { - nir_def *shader_index; - nir_def *geom_mask; - nir_def *geom_index; - nir_def *type; - nir_def *geom_flags; -}; - -static inline void -brw_nir_rt_load_bvh_primitive_leaf(nir_builder *b, - struct brw_nir_rt_bvh_primitive_leaf_defs *defs, - nir_def *leaf_addr) -{ - nir_def *desc = brw_nir_rt_load(b, leaf_addr, 4, 2, 32); - - defs->shader_index = - nir_ubitfield_extract(b, nir_channel(b, desc, 0), - nir_imm_int(b, 23), nir_imm_int(b, 0)); - defs->geom_mask = - nir_ubitfield_extract(b, nir_channel(b, desc, 0), - nir_imm_int(b, 31), nir_imm_int(b, 24)); - - defs->geom_index = - nir_ubitfield_extract(b, nir_channel(b, desc, 1), - nir_imm_int(b, 28), nir_imm_int(b, 0)); - defs->type = - nir_ubitfield_extract(b, nir_channel(b, desc, 1), - nir_imm_int(b, 29), nir_imm_int(b, 29)); - defs->geom_flags = - nir_ubitfield_extract(b, nir_channel(b, desc, 1), - nir_imm_int(b, 31), nir_imm_int(b, 30)); -} - -struct brw_nir_rt_bvh_primitive_leaf_positions_defs { - nir_def *positions[3]; -}; - -static inline void -brw_nir_rt_load_bvh_primitive_leaf_positions(nir_builder *b, - struct brw_nir_rt_bvh_primitive_leaf_positions_defs *defs, - nir_def *leaf_addr) -{ - for (unsigned i = 0; i < ARRAY_SIZE(defs->positions); i++) { - defs->positions[i] = - brw_nir_rt_load(b, nir_iadd_imm(b, leaf_addr, 16 + i * 4 * 3), 4, 3, 32); - } -} - -static inline nir_def * -brw_nir_rt_load_primitive_id_from_hit(nir_builder *b, - nir_def *is_procedural, - const struct brw_nir_rt_mem_hit_defs *defs) -{ - if (!is_procedural) { - is_procedural = - nir_ieq_imm(b, defs->leaf_type, - BRW_RT_BVH_NODE_TYPE_PROCEDURAL); - } - - nir_def *prim_id_proc, *prim_id_quad; - nir_push_if(b, is_procedural); - { - /* For procedural leafs, the index is in dw[3]. */ - nir_def *offset = - nir_iadd_imm(b, nir_ishl_imm(b, defs->prim_leaf_index, 2), 12); - prim_id_proc = nir_load_global(b, nir_iadd(b, defs->prim_leaf_ptr, - nir_u2u64(b, offset)), - 4, /* align */ 1, 32); - } - nir_push_else(b, NULL); - { - /* For quad leafs, the index is dw[2] and there is a 16bit additional - * offset in dw[3]. - */ - prim_id_quad = nir_load_global(b, nir_iadd_imm(b, defs->prim_leaf_ptr, 8), - 4, /* align */ 1, 32); - prim_id_quad = nir_iadd(b, - prim_id_quad, - defs->prim_index_delta); - } - nir_pop_if(b, NULL); - - return nir_if_phi(b, prim_id_proc, prim_id_quad); -} - -static inline nir_def * -brw_nir_rt_acceleration_structure_to_root_node(nir_builder *b, - nir_def *as_addr) -{ - /* The HW memory structure in which we specify what acceleration structure - * to traverse, takes the address to the root node in the acceleration - * structure, not the acceleration structure itself. To find that, we have - * to read the root node offset from the acceleration structure which is - * the first QWord. - * - * But if the acceleration structure pointer is NULL, then we should return - * NULL as root node pointer. - * - * TODO: we could optimize this by assuming that for a given version of the - * BVH, we can find the root node at a given offset. - */ - nir_def *root_node_ptr, *null_node_ptr; - nir_push_if(b, nir_ieq_imm(b, as_addr, 0)); - { - null_node_ptr = nir_imm_int64(b, 0); - } - nir_push_else(b, NULL); - { - root_node_ptr = - nir_iadd(b, as_addr, brw_nir_rt_load(b, as_addr, 256, 1, 64)); - } - nir_pop_if(b, NULL); - - return nir_if_phi(b, null_node_ptr, root_node_ptr); -} - -#endif /* BRW_NIR_RT_BUILDER_H */ diff --git a/src/intel/compiler/elk/brw_rt.h b/src/intel/compiler/elk/brw_rt.h deleted file mode 100644 index 2cf1851ff59..00000000000 --- a/src/intel/compiler/elk/brw_rt.h +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright © 2020 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef BRW_RT_H -#define BRW_RT_H - -#include - -#include "compiler/shader_enums.h" -#include "util/macros.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** Vulkan defines shaderGroupHandleSize = 32 */ -#define BRW_RT_SBT_HANDLE_SIZE 32 - -/** RT_DISPATCH_GLOBALS size (see gen_rt.xml) */ -#define BRW_RT_DISPATCH_GLOBALS_SIZE 80 - -/** Offset after the RT dispatch globals at which "push" constants live */ -#define BRW_RT_PUSH_CONST_OFFSET 128 - -/** Stride of the resume SBT */ -#define BRW_BTD_RESUME_SBT_STRIDE 8 - -/* Vulkan always uses exactly two levels of BVH: world and object. At the API - * level, these are referred to as top and bottom. - */ -enum brw_rt_bvh_level { - BRW_RT_BVH_LEVEL_WORLD = 0, - BRW_RT_BVH_LEVEL_OBJECT = 1, -}; -#define BRW_RT_MAX_BVH_LEVELS 2 - -enum brw_rt_bvh_node_type { - BRW_RT_BVH_NODE_TYPE_INTERNAL = 0, - BRW_RT_BVH_NODE_TYPE_INSTANCE = 1, - BRW_RT_BVH_NODE_TYPE_PROCEDURAL = 3, - BRW_RT_BVH_NODE_TYPE_QUAD = 4, -}; - -/** HitKind values returned for triangle geometry - * - * This enum must match the SPIR-V enum. - */ -enum brw_rt_hit_kind { - BRW_RT_HIT_KIND_FRONT_FACE = 0xfe, - BRW_RT_HIT_KIND_BACK_FACE = 0xff, -}; - -/** Ray flags - * - * This enum must match the SPIR-V RayFlags enum. - */ -enum brw_rt_ray_flags { - BRW_RT_RAY_FLAG_FORCE_OPAQUE = 0x01, - BRW_RT_RAY_FLAG_FORCE_NON_OPAQUE = 0x02, - BRW_RT_RAY_FLAG_TERMINATE_ON_FIRST_HIT = 0x04, - BRW_RT_RAY_FLAG_SKIP_CLOSEST_HIT_SHADER = 0x08, - BRW_RT_RAY_FLAG_CULL_BACK_FACING_TRIANGLES = 0x10, - BRW_RT_RAY_FLAG_CULL_FRONT_FACING_TRIANGLES = 0x20, - BRW_RT_RAY_FLAG_CULL_OPAQUE = 0x40, - BRW_RT_RAY_FLAG_CULL_NON_OPAQUE = 0x80, - BRW_RT_RAY_FLAG_SKIP_TRIANGLES = 0x100, - BRW_RT_RAY_FLAG_SKIP_AABBS = 0x200, -}; - -struct brw_rt_scratch_layout { - /** Number of stack IDs per DSS */ - uint32_t stack_ids_per_dss; - - /** Start offset (in bytes) of the hardware MemRay stack */ - uint32_t ray_stack_start; - - /** Stride (in bytes) of the hardware MemRay stack */ - uint32_t ray_stack_stride; - - /** Start offset (in bytes) of the SW stacks */ - uint64_t sw_stack_start; - - /** Size (in bytes) of the SW stack for a single shader invocation */ - uint32_t sw_stack_size; - - /** Total size (in bytes) of the RT scratch memory area */ - uint64_t total_size; -}; - -/** Parameters passed to the raygen trampoline shader - * - * This struct is carefully construected to be 32B and must be passed to the - * raygen trampoline shader as as inline constant data. - */ -struct brw_rt_raygen_trampoline_params { - /** The GPU address of the RT_DISPATCH_GLOBALS */ - uint64_t rt_disp_globals_addr; - - /** The GPU address of the BINDLESS_SHADER_RECORD for the raygen shader */ - uint64_t raygen_bsr_addr; - - /** 1 if this is an indirect dispatch, 0 otherwise */ - uint8_t is_indirect; - - /** The integer log2 of the local group size - * - * Ray-tracing shaders don't have a concept of local vs. global workgroup - * size. They only have a single 3D launch size. The raygen trampoline - * shader is always dispatched with a local workgroup size equal to the - * SIMD width but the shape of the local workgroup is determined at - * dispatch time based on the shape of the launch and passed to the - * trampoline via this field. (There's no sense having a Z dimension on - * the local workgroup if the launch is 2D.) - * - * We use the integer log2 of the size because there's no point in - * non-power-of-two sizes and shifts are cheaper than division. - */ - uint8_t local_group_size_log2[3]; - - uint32_t pad[3]; -}; - -/** Size of the "hot zone" in bytes - * - * The hot zone is a SW-defined data structure which is a single uvec4 - * containing two bits of information: - * - * - hotzone.x: Stack offset (in bytes) - * - * This is the offset (in bytes) into the per-thread scratch space at which - * the current shader's stack starts. This is incremented by the calling - * shader prior to any shader call type instructions and gets decremented - * by the resume shader as part of completing the return operation. - * - * - * - hotzone.yzw: The launch ID associated with the current thread - * - * Inside a bindless shader, the only information we have is the DSS ID - * from the hardware EU and a per-DSS stack ID. In particular, the three- - * dimensional launch ID is lost the moment we leave the raygen trampoline. - */ -#define BRW_RT_SIZEOF_HOTZONE 16 - -/* From the BSpec "Address Computation for Memory Based Data Structures: - * Ray and TraversalStack (Async Ray Tracing)": - * - * sizeof(Ray) = 64B, sizeof(HitInfo) = 32B, sizeof(TravStack) = 32B. - */ -#define BRW_RT_SIZEOF_RAY 64 -#define BRW_RT_SIZEOF_HIT_INFO 32 -#define BRW_RT_SIZEOF_TRAV_STACK 32 - -/* From the BSpec: - * - * syncStackSize = (maxBVHLevels % 2 == 1) ? - * (sizeof(HitInfo) * 2 + - * (sizeof(Ray) + sizeof(TravStack)) * maxBVHLevels + 32B) : - * (sizeof(HitInfo) * 2 + - * (sizeof(Ray) + sizeof(TravStack)) * maxBVHLevels); - * - * The select is just to align to 64B. - */ -#define BRW_RT_SIZEOF_RAY_QUERY \ - (BRW_RT_SIZEOF_HIT_INFO * 2 + \ - (BRW_RT_SIZEOF_RAY + BRW_RT_SIZEOF_TRAV_STACK) * BRW_RT_MAX_BVH_LEVELS + \ - (BRW_RT_MAX_BVH_LEVELS % 2 ? 32 : 0)) - -#define BRW_RT_SIZEOF_SHADOW_RAY_QUERY \ - (BRW_RT_SIZEOF_HIT_INFO * 2 + \ - (BRW_RT_SIZEOF_RAY + BRW_RT_SIZEOF_TRAV_STACK) * BRW_RT_MAX_BVH_LEVELS) - -#define BRW_RT_SIZEOF_HW_STACK \ - (BRW_RT_SIZEOF_HIT_INFO * 2 + \ - BRW_RT_SIZEOF_RAY * BRW_RT_MAX_BVH_LEVELS + \ - BRW_RT_SIZEOF_TRAV_STACK * BRW_RT_MAX_BVH_LEVELS) - -/* This is a mesa-defined region for hit attribute data */ -#define BRW_RT_SIZEOF_HIT_ATTRIB_DATA 64 -#define BRW_RT_OFFSETOF_HIT_ATTRIB_DATA BRW_RT_SIZEOF_HW_STACK - -#define BRW_RT_ASYNC_STACK_STRIDE \ - ALIGN_POT(BRW_RT_OFFSETOF_HIT_ATTRIB_DATA + \ - BRW_RT_SIZEOF_HIT_ATTRIB_DATA, 64) - -static inline void -brw_rt_compute_scratch_layout(struct brw_rt_scratch_layout *layout, - const struct intel_device_info *devinfo, - uint32_t stack_ids_per_dss, - uint32_t sw_stack_size) -{ - layout->stack_ids_per_dss = stack_ids_per_dss; - - const uint32_t dss_count = intel_device_info_dual_subslice_id_bound(devinfo); - const uint32_t num_stack_ids = dss_count * stack_ids_per_dss; - - uint64_t size = 0; - - /* The first thing in our scratch area is an array of "hot zones" which - * store the stack offset as well as the launch IDs for each active - * invocation. - */ - size += BRW_RT_SIZEOF_HOTZONE * num_stack_ids; - - /* Next, we place the HW ray stacks */ - assert(size % 64 == 0); /* Cache-line aligned */ - assert(size < UINT32_MAX); - layout->ray_stack_start = size; - layout->ray_stack_stride = BRW_RT_ASYNC_STACK_STRIDE; - size += num_stack_ids * layout->ray_stack_stride; - - /* Finally, we place the SW stacks for the individual ray-tracing shader - * invocations. We align these to 64B to ensure that we don't have any - * shared cache lines which could hurt performance. - */ - assert(size % 64 == 0); - layout->sw_stack_start = size; - layout->sw_stack_size = ALIGN(sw_stack_size, 64); - - /* Currently it's always the case that sw_stack_size is a power of - * two, but power-of-two SW stack sizes are prone to causing - * collisions in the hashing function used by the L3 to map memory - * addresses to banks, which can cause stack accesses from most - * DSSes to bottleneck on a single L3 bank. Fix it by padding the - * SW stack by a single cacheline if it was a power of two. - */ - if (layout->sw_stack_size > 64 && - util_is_power_of_two_nonzero(layout->sw_stack_size)) - layout->sw_stack_size += 64; - - size += num_stack_ids * layout->sw_stack_size; - - layout->total_size = size; -} - -static inline uint32_t -brw_rt_ray_queries_hw_stacks_size(const struct intel_device_info *devinfo) -{ - /* Maximum slice/subslice/EU ID can be computed from the max_scratch_ids - * which includes all the threads. - */ - uint32_t max_eu_id = devinfo->max_scratch_ids[MESA_SHADER_COMPUTE]; - uint32_t max_simd_size = 16; /* Cannot run in SIMD32 with ray queries */ - return max_eu_id * max_simd_size * BRW_RT_SIZEOF_RAY_QUERY; -} - -static inline uint32_t -brw_rt_ray_queries_shadow_stack_size(const struct intel_device_info *devinfo) -{ - /* Maximum slice/subslice/EU ID can be computed from the max_scratch_ids - * which includes all the threads. - */ - uint32_t max_eu_id = devinfo->max_scratch_ids[MESA_SHADER_COMPUTE]; - uint32_t max_simd_size = 16; /* Cannot run in SIMD32 with ray queries */ - return max_eu_id * max_simd_size * BRW_RT_SIZEOF_SHADOW_RAY_QUERY; -} - -static inline uint32_t -brw_rt_ray_queries_shadow_stacks_size(const struct intel_device_info *devinfo, - uint32_t ray_queries) -{ - /* Don't bother a shadow stack if we only have a single query. We can - * directly write in the HW buffer. - */ - return (ray_queries > 1 ? ray_queries : 0) * brw_rt_ray_queries_shadow_stack_size(devinfo) + - ray_queries * 4; /* Ctrl + Level data */ -} - -#ifdef __cplusplus -} -#endif - -#endif /* BRW_RT_H */ diff --git a/src/intel/compiler/elk/intel_clc.c b/src/intel/compiler/elk/intel_clc.c deleted file mode 100644 index 6e7ba453eaf..00000000000 --- a/src/intel/compiler/elk/intel_clc.c +++ /dev/null @@ -1,676 +0,0 @@ -/* - * Copyright © 2021 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_compiler.h" -#include "brw_kernel.h" -#include "compiler/brw_disasm.h" -#include "compiler/clc/clc.h" -#include "compiler/glsl_types.h" -#include "compiler/nir/nir_serialize.h" -#include "dev/intel_debug.h" -#include "util/build_id.h" -#include "util/disk_cache.h" -#include "util/macros.h" -#include "util/mesa-sha1.h" -#include "util/u_dynarray.h" - -#include -#include -#include -#include -#include -#include -#include - -/* Shader functions */ -#define SPIR_V_MAGIC_NUMBER 0x07230203 - -static struct disk_cache * -get_disk_cache(struct brw_compiler *compiler) -{ -#ifdef ENABLE_SHADER_CACHE - char renderer[14]; - ASSERTED int len = snprintf(renderer, sizeof(renderer), "brw_clc_%04x", - compiler->devinfo->pci_device_id); - assert(len == sizeof(renderer) - 2); - - const struct build_id_note *note = - build_id_find_nhdr_for_addr(get_disk_cache); - if (note == NULL) { - fprintf(stderr, "Failed to find build-id\n"); - abort(); - } - - unsigned build_id_len = build_id_length(note); - if (build_id_len < 20) { - fprintf(stderr, "build-id too short. It needs to be a SHA\n"); - abort(); - } - - struct mesa_sha1 sha1_ctx; - uint8_t sha1[20]; - _mesa_sha1_init(&sha1_ctx); - _mesa_sha1_update(&sha1_ctx, build_id_data(note), build_id_len); - _mesa_sha1_final(&sha1_ctx, sha1); - - char timestamp[41]; - _mesa_sha1_format(timestamp, sha1); - - const uint64_t driver_flags = brw_get_compiler_config_value(compiler); - - return disk_cache_create(renderer, timestamp, driver_flags); -#endif - return NULL; -} - -static void -compiler_log(void *data, unsigned *id, const char *fmt, ...) -{ - va_list args; - va_start(args, fmt); - if (INTEL_DEBUG(DEBUG_CS)) - vfprintf(stderr, fmt, args); - va_end(args); -} - -static void -msg_callback(void *priv, const char *msg) -{ - (void)priv; - fprintf(stderr, "%s", msg); -} - -static void -print_u32_data(FILE *fp, const char *prefix, const char *arr_name, - const uint32_t *data, size_t len) -{ - assert(len % 4 == 0); - fprintf(fp, "static const uint32_t %s_%s[] = {", prefix, arr_name); - for (unsigned i = 0; i < (len / 4); i++) { - if (i % 4 == 0) - fprintf(fp,"\n "); - - fprintf(fp, " 0x%08" PRIx32 ",", data[i]); - } - fprintf(fp, "\n};\n"); -} - -static void -print_u8_data(FILE *fp, const char *prefix, const char *arr_name, - const uint8_t *data, size_t len) -{ - fprintf(fp, "static const uint8_t %s_%s[] = {", prefix, arr_name); - for (unsigned i = 0; i < len; i++) { - if (i % 16 == 0) - fprintf(fp,"\n "); - - fprintf(fp, " 0x%02" PRIx8 ",", data[i]); - } - fprintf(fp, "\n};\n"); -} - -static const char * -reloc_type_str(enum brw_shader_reloc_type type) -{ - switch (type) { -#define CASE(e) case e: return #e; - CASE(BRW_SHADER_RELOC_TYPE_U32) - CASE(BRW_SHADER_RELOC_TYPE_MOV_IMM) -#undef CASE - default: - unreachable("Unknown relocation type"); - } -} - -static void -print_cs_prog_data_fields(FILE *fp, const char *prefix, const char *pad, - const struct brw_cs_prog_data *cs_prog_data) -{ -#define PROG_DATA_FIELD(fmt, field) \ - fprintf(fp, "%s." #field " = " fmt ",\n", pad, cs_prog_data->field) - -#define PROG_DATA_BOOL_FIELD(field) \ - fprintf(fp, "%s." #field " = %s,\n", pad, \ - cs_prog_data->field ? "true" : "false") - - PROG_DATA_FIELD("%u", base.nr_params); - assert(cs_prog_data->base.stage == MESA_SHADER_COMPUTE); - fprintf(fp, "%s.base.stage = MESA_SHADER_COMPUTE,\n", pad); - assert(cs_prog_data->base.zero_push_reg == 0); - assert(cs_prog_data->base.push_reg_mask_param == 0); - PROG_DATA_FIELD("%u", base.curb_read_length); - PROG_DATA_FIELD("%u", base.total_scratch); - PROG_DATA_FIELD("%u", base.total_shared); - PROG_DATA_FIELD("%u", base.program_size); - PROG_DATA_FIELD("%u", base.const_data_size); - PROG_DATA_FIELD("%u", base.const_data_offset); - PROG_DATA_FIELD("%u", base.num_relocs); - fprintf(fp, "%s.base.relocs = %s_relocs,\n", pad, prefix); - assert(!cs_prog_data->base.has_ubo_pull); - assert(cs_prog_data->base.dispatch_grf_start_reg == 0); - assert(!cs_prog_data->base.use_alt_mode); - assert(cs_prog_data->base.param == 0); - PROG_DATA_BOOL_FIELD(base.uses_atomic_load_store); - fprintf(fp, "%s.local_size = { %u, %u, %u },\n", pad, - cs_prog_data->local_size[0], - cs_prog_data->local_size[1], - cs_prog_data->local_size[2]); - fprintf(fp, "%s.prog_offset = { %u, %u, %u },\n", pad, - cs_prog_data->prog_offset[0], - cs_prog_data->prog_offset[1], - cs_prog_data->prog_offset[2]); - PROG_DATA_FIELD("%u", prog_mask); - PROG_DATA_FIELD("%u", prog_spilled); - PROG_DATA_BOOL_FIELD(uses_barrier); - PROG_DATA_BOOL_FIELD(uses_num_work_groups); - assert(!cs_prog_data->uses_inline_data); - assert(!cs_prog_data->uses_btd_stack_ids); - PROG_DATA_FIELD("%u", push.per_thread.dwords); - PROG_DATA_FIELD("%u", push.per_thread.regs); - PROG_DATA_FIELD("%u", push.per_thread.size); - PROG_DATA_FIELD("%u", push.cross_thread.dwords); - PROG_DATA_FIELD("%u", push.cross_thread.regs); - PROG_DATA_FIELD("%u", push.cross_thread.size); - -#undef PROG_DATA_FIELD -#undef PROG_DATA_BOOL_FIELD -} - -static void -print_kernel(FILE *fp, const char *prefix, - const struct brw_kernel *kernel, - const struct brw_isa_info *isa) -{ - struct mesa_sha1 sha1_ctx; - _mesa_sha1_init(&sha1_ctx); - -#define SHA1_UPDATE_VALUE(val) \ - _mesa_sha1_update(&sha1_ctx, &val, sizeof(val)) - - fprintf(fp, "#include \"intel/compiler/brw_kernel.h\"\n"); - fprintf(fp, "\n"); - - fprintf(fp, "static const struct brw_shader_reloc %s_relocs[] = {\n", - prefix); - for (unsigned i = 0; i < kernel->prog_data.base.num_relocs; i++) { - const struct brw_shader_reloc *reloc = &kernel->prog_data.base.relocs[i]; - fprintf(fp, " { %"PRIu32", %s, %"PRIu32", %"PRIu32" },\n", - reloc->id, reloc_type_str(reloc->type), - reloc->offset, reloc->delta); - } - fprintf(fp, "};\n"); - _mesa_sha1_update(&sha1_ctx, kernel->prog_data.base.relocs, - kernel->prog_data.base.num_relocs * - sizeof(kernel->prog_data.base.relocs[0])); - - /* Get rid of the pointers before we hash */ - struct brw_cs_prog_data cs_prog_data = kernel->prog_data; - cs_prog_data.base.relocs = NULL; - assert(cs_prog_data.base.param == NULL); - _mesa_sha1_update(&sha1_ctx, &cs_prog_data, sizeof(cs_prog_data)); - - SHA1_UPDATE_VALUE(kernel->args_size); - SHA1_UPDATE_VALUE(kernel->arg_count); - _mesa_sha1_update(&sha1_ctx, kernel->args, - kernel->arg_count * sizeof(kernel->args[0])); - - fprintf(fp, "static const struct brw_kernel_arg_desc %s_args[] = {\n", - prefix); - for (unsigned i = 0; i < kernel->arg_count; i++) { - fprintf(fp, " { %d, %d },\n", - kernel->args[i].offset, kernel->args[i].size); - } - fprintf(fp, "};\n\n"); - - _mesa_sha1_update(&sha1_ctx, kernel->code, - kernel->prog_data.base.program_size); - - fprintf(fp, "#if 0 /* BEGIN KERNEL ASSEMBLY */\n"); - fprintf(fp, "\n"); - brw_disassemble_with_errors(isa, kernel->code, 0, fp); - fprintf(fp, "\n"); - fprintf(fp, "#endif /* END KERNEL ASSEMBLY */\n"); - print_u32_data(fp, prefix, "code", kernel->code, - kernel->prog_data.base.program_size); - - fprintf(fp, "static const struct brw_kernel %s = {\n", prefix); - fprintf(fp, " .prog_data = {\n"); - print_cs_prog_data_fields(fp, prefix, " ", &kernel->prog_data); - fprintf(fp, " },\n"); - fprintf(fp, " .args_size = %d,\n", (int)kernel->args_size); - fprintf(fp, " .arg_count = %d,\n", (int)kernel->arg_count); - fprintf(fp, " .args = %s_args,\n", prefix); - fprintf(fp, " .code = %s_code,\n", prefix); - fprintf(fp, "};\n"); - - unsigned char sha1[20]; - _mesa_sha1_final(&sha1_ctx, sha1); - char sha1_str[41]; - _mesa_sha1_format(sha1_str, sha1); - fprintf(fp, "const char *%s_sha1 = \"%s\";\n", prefix, sha1_str); -} - -static void -print_usage(char *exec_name, FILE *f) -{ - fprintf(f, -"Usage: %s [options] -- [clang args]\n" -"Options:\n" -" -h --help Print this help.\n" -" -e, --entrypoint Specify the entry-point name.\n" -" -L, --llvm17-wa Enable LLVM 17 workarounds for opaque pointers" -" -p, --platform Specify the target platform name.\n" -" --prefix Prefix for variable names in generated C code.\n" -" -o, --out Specify the output filename.\n" -" -i, --in Specify one input filename. Accepted multiple times.\n" -" -s, --spv Specify the output filename for spirv.\n" -" -n, --nir Specify whether to output serialized NIR instead of ISA.\n" -" -t, --text Specify the output filename for the parsed text\n" -" -v, --verbose Print more information during compilation.\n" -" -M, --llvm-version Print LLVM version.\n" - , exec_name); -} - -#define OPT_PREFIX 1000 - -struct intel_clc_params { - char *entry_point; - char *platform; - char *outfile; - char *spv_outfile; - char *txt_outfile; - char *prefix; - - bool output_nir; - bool print_info; - bool llvm17_wa; - - void *mem_ctx; - - struct intel_device_info devinfo; -}; - -#include "compiler/spirv/nir_spirv.h" - -static int -output_nir(const struct intel_clc_params *params, struct clc_binary *binary) -{ - struct spirv_to_nir_options spirv_options = { - .environment = NIR_SPIRV_OPENCL, - .caps = { - .address = true, - .groups = true, - .image_write_without_format = true, - .int8 = true, - .int16 = true, - .int64 = true, - .int64_atomics = true, - .kernel = true, - .linkage = true, /* We receive linked kernel from clc */ - .float_controls = true, - .generic_pointers = true, - .storage_8bit = true, - .storage_16bit = true, - .subgroup_arithmetic = true, - .subgroup_basic = true, - .subgroup_ballot = true, - .subgroup_dispatch = true, - .subgroup_quad = true, - .subgroup_shuffle = true, - .subgroup_vote = true, - - .intel_subgroup_shuffle = true, - .intel_subgroup_buffer_block_io = true, - }, - .shared_addr_format = nir_address_format_62bit_generic, - .global_addr_format = nir_address_format_62bit_generic, - .temp_addr_format = nir_address_format_62bit_generic, - .constant_addr_format = nir_address_format_64bit_global, - .create_library = true, - }; - - FILE *fp = params->outfile != NULL ? - fopen(params->outfile, "w") : stdout; - if (!fp) { - fprintf(stderr, "Failed to open %s\n", params->outfile); - return -1; - } - - spirv_library_to_nir_builder(fp, binary->data, binary->size / 4, - &spirv_options); - - nir_shader *nir = brw_nir_from_spirv(params->mem_ctx, - binary->data, binary->size, - params->llvm17_wa); - if (!nir) { - fprintf(stderr, "Failed to generate NIR out of SPIRV\n"); - return -1; - } - - struct blob blob; - blob_init(&blob); - nir_serialize(&blob, nir, false /* strip */); - print_u8_data(fp, params->prefix, "nir", blob.data, blob.size); - blob_finish(&blob); - - if (params->outfile) - fclose(fp); - - return 0; -} - -static int -output_isa(const struct intel_clc_params *params, struct clc_binary *binary) -{ - struct brw_kernel kernel = {}; - char *error_str; - - struct brw_isa_info _isa, *isa = &_isa; - brw_init_isa_info(isa, ¶ms->devinfo); - - struct brw_compiler *compiler = brw_compiler_create(params->mem_ctx, - ¶ms->devinfo); - compiler->shader_debug_log = compiler_log; - compiler->shader_perf_log = compiler_log; - struct disk_cache *disk_cache = get_disk_cache(compiler); - - if (!brw_kernel_from_spirv(compiler, disk_cache, &kernel, NULL, params->mem_ctx, - binary->data, binary->size, - params->entry_point, &error_str)) { - fprintf(stderr, "Compile failed: %s\n", error_str); - return -1; - } - - if (params->print_info) { - fprintf(stdout, "kernel info:\n"); - fprintf(stdout, " uses_barrier : %u\n", kernel.prog_data.uses_barrier); - fprintf(stdout, " uses_num_work_groups : %u\n", kernel.prog_data.uses_num_work_groups); - fprintf(stdout, " uses_inline_data : %u\n", kernel.prog_data.uses_inline_data); - fprintf(stdout, " local_size : %ux%ux%u\n", - kernel.prog_data.local_size[0], - kernel.prog_data.local_size[1], - kernel.prog_data.local_size[2]); - fprintf(stdout, " curb_read_length : %u\n", kernel.prog_data.base.curb_read_length); - fprintf(stdout, " total_scratch : %u\n", kernel.prog_data.base.total_scratch); - fprintf(stdout, " total_shared : %u\n", kernel.prog_data.base.total_shared); - fprintf(stdout, " program_size : %u\n", kernel.prog_data.base.program_size); - fprintf(stdout, " const_data_size : %u\n", kernel.prog_data.base.const_data_size); - fprintf(stdout, " uses_atomic_load_store : %u\n", kernel.prog_data.base.uses_atomic_load_store); - fprintf(stdout, " dispatch_grf_start_reg : %u\n", kernel.prog_data.base.dispatch_grf_start_reg); - } - - char *prefix = params->prefix; - char prefix_tmp[256]; - if (prefix == NULL) { - bool is_pt_5 = (params->devinfo.verx10 % 10) == 5; - snprintf(prefix_tmp, sizeof(prefix_tmp), "gfx%d%s_clc_%s", - params->devinfo.ver, is_pt_5 ? "5" : "", params->entry_point); - prefix = prefix_tmp; - } - - if (params->outfile != NULL) { - FILE *fp = fopen(params->outfile, "w"); - print_kernel(fp, prefix, &kernel, isa); - fclose(fp); - } else { - print_kernel(stdout, prefix, &kernel, isa); - } - - return 0; -} - -static void -print_llvm_version(FILE *out) -{ - fprintf(out, "%s\n", MESA_LLVM_VERSION_STRING); -} - -int main(int argc, char **argv) -{ - int exit_code = 0; - - process_intel_debug_variable(); - - static struct option long_options[] ={ - {"help", no_argument, 0, 'h'}, - {"entrypoint", required_argument, 0, 'e'}, - {"platform", required_argument, 0, 'p'}, - {"prefix", required_argument, 0, OPT_PREFIX}, - {"in", required_argument, 0, 'i'}, - {"out", required_argument, 0, 'o'}, - {"spv", required_argument, 0, 's'}, - {"text", required_argument, 0, 't'}, - {"nir", no_argument, 0, 'n'}, - {"llvm17-wa", no_argument, 0, 'L'}, - {"llvm-version", no_argument, 0, 'M'}, - {"verbose", no_argument, 0, 'v'}, - {0, 0, 0, 0} - }; - - struct intel_clc_params params = {}; - - struct util_dynarray clang_args; - struct util_dynarray input_files; - - struct clc_binary spirv_obj = {0}; - struct clc_parsed_spirv parsed_spirv_data = {0}; - struct disk_cache *disk_cache = NULL; - - params.mem_ctx = ralloc_context(NULL); - - util_dynarray_init(&clang_args, params.mem_ctx); - util_dynarray_init(&input_files, params.mem_ctx); - - int ch; - while ((ch = getopt_long(argc, argv, "he:p:s:t:i:no:MLv", long_options, NULL)) != -1) - { - switch (ch) - { - case 'h': - print_usage(argv[0], stdout); - goto end; - case 'e': - params.entry_point = optarg; - break; - case 'p': - params.platform = optarg; - break; - case 'o': - params.outfile = optarg; - break; - case 'i': - util_dynarray_append(&input_files, char *, optarg); - break; - case 'n': - params.output_nir = true; - break; - case 's': - params.spv_outfile = optarg; - break; - case 't': - params.txt_outfile = optarg; - break; - case 'v': - params.print_info = true; - break; - case 'L': - params.llvm17_wa = true; - break; - case 'M': - print_llvm_version(stdout); - return EXIT_SUCCESS; - case OPT_PREFIX: - params.prefix = optarg; - break; - default: - fprintf(stderr, "Unrecognized option \"%s\".\n", optarg); - print_usage(argv[0], stderr); - goto fail; - } - } - - for (int i = optind; i < argc; i++) { - util_dynarray_append(&clang_args, char *, argv[i]); - } - - if (util_dynarray_num_elements(&input_files, char *) == 0) { - fprintf(stderr, "No input file(s).\n"); - print_usage(argv[0], stderr); - goto fail; - } - - struct clc_logger logger = { - .error = msg_callback, - .warning = msg_callback, - }; - - size_t total_size = 0; - char *all_inputs = NULL; - util_dynarray_foreach(&input_files, char *, infile) { - int fd = open(*infile, O_RDONLY); - if (fd < 0) { - fprintf(stderr, "Failed to open %s\n", *infile); - goto fail; - } - - off_t len = lseek(fd, 0, SEEK_END); - size_t new_size = total_size + len; - all_inputs = reralloc_size(params.mem_ctx, all_inputs, new_size + 1); - if (!all_inputs) { - fprintf(stderr, "Failed to allocate memory\n"); - goto fail; - } - lseek(fd, 0, SEEK_SET); - read(fd, all_inputs + total_size, len); - close(fd); - total_size = new_size; - all_inputs[total_size] = '\0'; - } - - if (params.txt_outfile) { - FILE *fp = fopen(params.txt_outfile, "w"); - fwrite(all_inputs, total_size, 1, fp); - fclose(fp); - } - - const char *allowed_spirv_extensions[] = { - "SPV_EXT_shader_atomic_float_add", - "SPV_EXT_shader_atomic_float_min_max", - "SPV_KHR_float_controls", - "SPV_INTEL_subgroups", - NULL, - }; - - struct clc_compile_args clc_args = { - .source = { - .name = "intel_clc_files", - .value = all_inputs, - }, - .features = { - .fp16 = true, - .intel_subgroups = true, - .subgroups = true, - .subgroups_ifp = true, - }, - .args = util_dynarray_begin(&clang_args), - .num_args = util_dynarray_num_elements(&clang_args, char *), - .allowed_spirv_extensions = allowed_spirv_extensions, - }; - - if (!clc_compile_c_to_spirv(&clc_args, &logger, &spirv_obj)) { - goto fail; - } - - if (params.spv_outfile) { - FILE *fp = fopen(params.spv_outfile, "w"); - fwrite(spirv_obj.data, spirv_obj.size, 1, fp); - fclose(fp); - } - - glsl_type_singleton_init_or_ref(); - - if (params.output_nir) { - exit_code = output_nir(¶ms, &spirv_obj); - } else { - if (params.platform == NULL) { - fprintf(stderr, "No target platform name specified.\n"); - print_usage(argv[0], stderr); - goto fail; - } - - int pci_id = intel_device_name_to_pci_device_id(params.platform); - if (pci_id < 0) { - fprintf(stderr, "Invalid target platform name: %s\n", params.platform); - goto fail; - } - - if (!intel_get_device_info_from_pci_id(pci_id, ¶ms.devinfo)) { - fprintf(stderr, "Failed to get device information.\n"); - goto fail; - } - - if (params.devinfo.verx10 < 125) { - fprintf(stderr, "Platform currently not supported.\n"); - goto fail; - } - - if (params.entry_point == NULL) { - fprintf(stderr, "No entry-point name specified.\n"); - print_usage(argv[0], stderr); - goto fail; - } - - struct clc_parsed_spirv parsed_spirv_data; - if (!clc_parse_spirv(&spirv_obj, &logger, &parsed_spirv_data)) - goto fail; - - const struct clc_kernel_info *kernel_info = NULL; - for (unsigned i = 0; i < parsed_spirv_data.num_kernels; i++) { - if (strcmp(parsed_spirv_data.kernels[i].name, params.entry_point) == 0) { - kernel_info = &parsed_spirv_data.kernels[i]; - break; - } - } - if (kernel_info == NULL) { - fprintf(stderr, "Kernel entrypoint %s not found\n", params.entry_point); - goto fail; - } - - exit_code = output_isa(¶ms, &spirv_obj); - } - - glsl_type_singleton_decref(); - - goto end; - -fail: - exit_code = 1; - -end: - disk_cache_destroy(disk_cache); - clc_free_parsed_spirv(&parsed_spirv_data); - clc_free_spirv(&spirv_obj); - ralloc_free(params.mem_ctx); - - return exit_code; -} diff --git a/src/intel/compiler/elk/meson.build b/src/intel/compiler/elk/meson.build index a5651c3a05d..e755ffbb285 100644 --- a/src/intel/compiler/elk/meson.build +++ b/src/intel/compiler/elk/meson.build @@ -65,7 +65,6 @@ libintel_compiler_elk_files = files( 'brw_fs_reg_allocate.cpp', 'brw_fs_register_coalesce.cpp', 'brw_fs_saturate_propagation.cpp', - 'brw_fs_scoreboard.cpp', 'brw_fs_sel_peephole.cpp', 'brw_fs_thread_payload.cpp', 'brw_fs_validate.cpp', @@ -81,23 +80,14 @@ libintel_compiler_elk_files = files( 'brw_ir_vec4.h', 'brw_isa_info.h', 'brw_lower_logical_sends.cpp', - 'brw_mesh.cpp', 'brw_nir.h', 'brw_nir.c', 'brw_nir_analyze_boolean_resolves.c', 'brw_nir_analyze_ubo_ranges.c', 'brw_nir_attribute_workarounds.c', - 'brw_nir_lower_cooperative_matrix.c', 'brw_nir_lower_cs_intrinsics.c', 'brw_nir_lower_alpha_to_coverage.c', - 'brw_nir_lower_intersection_shader.c', - 'brw_nir_lower_ray_queries.c', - 'brw_nir_lower_rt_intrinsics.c', - 'brw_nir_lower_shader_calls.c', 'brw_nir_lower_storage_image.c', - 'brw_nir_rt.h', - 'brw_nir_rt.c', - 'brw_nir_rt_builder.h', 'brw_packed_float.c', 'brw_predicated_break.cpp', 'brw_prim.h', @@ -105,7 +95,6 @@ libintel_compiler_elk_files = files( 'brw_reg.h', 'brw_reg_type.c', 'brw_reg_type.h', - 'brw_rt.h', 'brw_schedule_instructions.cpp', 'brw_shader.cpp', 'brw_shader.h', @@ -173,7 +162,6 @@ if with_tests 'test_fs_combine_constants.cpp', 'test_fs_copy_propagation.cpp', 'test_fs_saturate_propagation.cpp', - 'test_fs_scoreboard.cpp', 'test_simd_selection.cpp', 'test_vec4_cmod_propagation.cpp', 'test_vec4_copy_propagation.cpp', @@ -228,10 +216,6 @@ asm_testcases = [ ['ivb', 'gfx7'], ['hsw', 'gfx7.5'], ['bdw', 'gfx8'], - ['skl', 'gfx9'], - ['icl', 'gfx11'], - ['tgl', 'gfx12'], - ['dg2', 'gfx12.5'], ] test_runner = find_program('tests/run-test.py') diff --git a/src/intel/compiler/elk/test_fs_scoreboard.cpp b/src/intel/compiler/elk/test_fs_scoreboard.cpp deleted file mode 100644 index 8502fc3a4ae..00000000000 --- a/src/intel/compiler/elk/test_fs_scoreboard.cpp +++ /dev/null @@ -1,893 +0,0 @@ -/* - * Copyright © 2019 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include -#include "brw_fs.h" -#include "brw_fs_builder.h" -#include "brw_cfg.h" - -using namespace brw; - -class scoreboard_test : public ::testing::Test { -protected: - scoreboard_test(); - ~scoreboard_test() override; - - struct brw_compiler *compiler; - struct brw_compile_params params; - struct intel_device_info *devinfo; - void *ctx; - struct brw_wm_prog_data *prog_data; - struct gl_shader_program *shader_prog; - fs_visitor *v; - fs_builder bld; -}; - -scoreboard_test::scoreboard_test() - : bld(NULL, 0) -{ - ctx = ralloc_context(NULL); - compiler = rzalloc(ctx, struct brw_compiler); - devinfo = rzalloc(ctx, struct intel_device_info); - devinfo->ver = 12; - devinfo->verx10 = devinfo->ver * 10; - - compiler->devinfo = devinfo; - brw_init_isa_info(&compiler->isa, devinfo); - - params = {}; - params.mem_ctx = ctx; - - prog_data = ralloc(ctx, struct brw_wm_prog_data); - nir_shader *shader = - nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL); - - v = new fs_visitor(compiler, ¶ms, NULL, &prog_data->base, shader, 8, - false, false); - - bld = fs_builder(v).at_end(); -} - -scoreboard_test::~scoreboard_test() -{ - delete v; - v = NULL; - - ralloc_free(ctx); - ctx = NULL; -} - -static fs_inst * -instruction(bblock_t *block, int num) -{ - fs_inst *inst = (fs_inst *)block->start(); - for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; - } - return inst; -} - -static void -lower_scoreboard(fs_visitor *v) -{ - const bool print = getenv("TEST_DEBUG"); - - if (print) { - fprintf(stderr, "= Before =\n"); - v->cfg->dump(); - } - - v->lower_scoreboard(); - - if (print) { - fprintf(stderr, "\n= After =\n"); - v->cfg->dump(); - } -} - -fs_inst * -emit_SEND(const fs_builder &bld, const fs_reg &dst, - const fs_reg &desc, const fs_reg &payload) -{ - fs_inst *inst = bld.emit(SHADER_OPCODE_SEND, dst, desc, desc, payload); - inst->mlen = 1; - return inst; -} - -static tgl_swsb -tgl_swsb_testcase(unsigned regdist, unsigned sbid, enum tgl_sbid_mode mode) -{ - tgl_swsb swsb = tgl_swsb_sbid(mode, sbid); - swsb.regdist = regdist; - return swsb; -} - -bool operator ==(const tgl_swsb &a, const tgl_swsb &b) -{ - return a.mode == b.mode && - a.regdist == b.regdist && - (a.mode == TGL_SBID_NULL || a.sbid == b.sbid); -} - -std::ostream &operator<<(std::ostream &os, const tgl_swsb &swsb) { - if (swsb.regdist) - os << "@" << swsb.regdist; - - if (swsb.mode) { - if (swsb.regdist) - os << " "; - os << "$" << swsb.sbid; - if (swsb.mode & TGL_SBID_DST) - os << ".dst"; - if (swsb.mode & TGL_SBID_SRC) - os << ".src"; - } - - return os; -} - -TEST_F(scoreboard_test, RAW_inorder_inorder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - fs_reg y = v->vgrf(glsl_int_type()); - bld.ADD( x, g[1], g[2]); - bld.MUL( y, g[3], g[4]); - bld.AND(g[5], x, y); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_regdist(1)); -} - -TEST_F(scoreboard_test, RAW_inorder_outoforder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.ADD( x, g[1], g[2]); - bld.MUL( g[3], g[4], g[5]); - emit_SEND(bld, g[6], g[7], x); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_testcase(2, 0, TGL_SBID_SET)); -} - -TEST_F(scoreboard_test, RAW_outoforder_inorder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - fs_reg y = v->vgrf(glsl_int_type()); - emit_SEND(bld, x, g[1], g[2]); - bld.MUL( y, g[3], g[4]); - bld.AND( g[5], x, y); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_testcase(1, 0, TGL_SBID_DST)); -} - -TEST_F(scoreboard_test, RAW_outoforder_outoforder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - /* The second SEND depends on the first, and would need to refer to two - * SBIDs. Since it is not possible we expect a SYNC instruction to be - * added. - */ - fs_reg x = v->vgrf(glsl_int_type()); - emit_SEND(bld, x, g[1], g[2]); - emit_SEND(bld, g[3], x, g[4])->sfid++; - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(1, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - - fs_inst *sync = instruction(block0, 1); - EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); - EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_DST, 0)); - - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SET, 1)); -} - -TEST_F(scoreboard_test, WAR_inorder_inorder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.ADD(g[1], x, g[2]); - bld.MUL(g[3], g[4], g[5]); - bld.AND( x, g[6], g[7]); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_null()); -} - -TEST_F(scoreboard_test, WAR_inorder_outoforder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.ADD( g[1], x, g[2]); - bld.MUL( g[3], g[4], g[5]); - emit_SEND(bld, x, g[6], g[7]); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_testcase(2, 0, TGL_SBID_SET)); -} - -TEST_F(scoreboard_test, WAR_outoforder_inorder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - emit_SEND(bld, g[1], g[2], x); - bld.MUL( g[4], g[5], g[6]); - bld.AND( x, g[7], g[8]); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SRC, 0)); -} - -TEST_F(scoreboard_test, WAR_outoforder_outoforder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - emit_SEND(bld, g[1], g[2], x); - emit_SEND(bld, x, g[3], g[4])->sfid++; - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(1, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - - fs_inst *sync = instruction(block0, 1); - EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); - EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_SRC, 0)); - - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SET, 1)); -} - -TEST_F(scoreboard_test, WAW_inorder_inorder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.ADD( x, g[1], g[2]); - bld.MUL(g[3], g[4], g[5]); - bld.AND( x, g[6], g[7]); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - - /* NOTE: We only need this RegDist if a long instruction is followed by a - * short one. The pass is currently conservative about this and adding the - * annotation. - */ - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, WAW_inorder_outoforder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.ADD( x, g[1], g[2]); - bld.MUL( g[3], g[4], g[5]); - emit_SEND(bld, x, g[6], g[7]); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_testcase(2, 0, TGL_SBID_SET)); -} - -TEST_F(scoreboard_test, WAW_outoforder_inorder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - emit_SEND(bld, x, g[1], g[2]); - bld.MUL( g[3], g[4], g[5]); - bld.AND( x, g[6], g[7]); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_DST, 0)); -} - -TEST_F(scoreboard_test, WAW_outoforder_outoforder) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - emit_SEND(bld, x, g[1], g[2]); - emit_SEND(bld, x, g[3], g[4])->sfid++; - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(1, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - - fs_inst *sync = instruction(block0, 1); - EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); - EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_DST, 0)); - - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_sbid(TGL_SBID_SET, 1)); -} - - -TEST_F(scoreboard_test, loop1) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_DO); - - bld.ADD( x, g[1], g[2]); - bld.emit(BRW_OPCODE_WHILE)->predicate = BRW_PREDICATE_NORMAL; - - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *body = v->cfg->blocks[2]; - fs_inst *add = instruction(body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(1)); - - bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 0); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(1)); -} - -TEST_F(scoreboard_test, loop2) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - - bld.emit(BRW_OPCODE_DO); - - bld.ADD( x, g[1], g[2]); - bld.emit(BRW_OPCODE_WHILE)->predicate = BRW_PREDICATE_NORMAL; - - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - /* Now the write in ADD has the tightest RegDist for both ADD and MUL. */ - - bblock_t *body = v->cfg->blocks[2]; - fs_inst *add = instruction(body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(2)); - - bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 0); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, loop3) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_DO); - - /* For the ADD in the loop body this extra distance will always apply. */ - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - bld.XOR(g[6], g[1], g[2]); - - bld.ADD( x, g[1], g[2]); - bld.emit(BRW_OPCODE_WHILE)->predicate = BRW_PREDICATE_NORMAL; - - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *body = v->cfg->blocks[2]; - fs_inst *add = instruction(body, 4); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(5)); - - bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 0); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(1)); -} - - -TEST_F(scoreboard_test, conditional1) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.ADD( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(2)); - - bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, conditional2) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.ADD( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(5)); - - bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, conditional3) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - bld.ADD( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 3); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(5)); - - bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, conditional4) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.ADD( x, g[1], g[2]); - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(2)); - - bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(3)); -} - -TEST_F(scoreboard_test, conditional5) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.ADD( x, g[1], g[2]); - bld.emit(BRW_OPCODE_ELSE); - - bld.ROL( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(2)); - - bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 0); - EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); - EXPECT_EQ(rol->sched, tgl_swsb_regdist(2)); - - bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, conditional6) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - bld.ADD( x, g[1], g[2]); - bld.emit(BRW_OPCODE_ELSE); - - bld.XOR(g[6], g[1], g[2]); - bld.XOR(g[7], g[1], g[2]); - bld.XOR(g[8], g[1], g[2]); - bld.XOR(g[9], g[1], g[2]); - bld.ROL( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 3); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(5)); - - bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 4); - EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); - EXPECT_EQ(rol->sched, tgl_swsb_regdist(6)); - - bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, conditional7) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.ADD( x, g[1], g[2]); - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - bld.emit(BRW_OPCODE_ELSE); - - bld.ROL( x, g[1], g[2]); - bld.XOR(g[6], g[1], g[2]); - bld.XOR(g[7], g[1], g[2]); - bld.XOR(g[8], g[1], g[2]); - bld.XOR(g[9], g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(2)); - - bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 0); - EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); - EXPECT_EQ(rol->sched, tgl_swsb_regdist(2)); - - bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(6)); -} - -TEST_F(scoreboard_test, conditional8) -{ - fs_reg g[16]; - for (unsigned i = 0; i < ARRAY_SIZE(g); i++) - g[i] = v->vgrf(glsl_int_type()); - - fs_reg x = v->vgrf(glsl_int_type()); - bld.XOR( x, g[1], g[2]); - bld.XOR(g[3], g[1], g[2]); - bld.XOR(g[4], g[1], g[2]); - bld.XOR(g[5], g[1], g[2]); - bld.XOR(g[6], g[1], g[2]); - bld.XOR(g[7], g[1], g[2]); - bld.emit(BRW_OPCODE_IF); - - bld.ADD( x, g[1], g[2]); - bld.emit(BRW_OPCODE_ELSE); - - bld.ROL( x, g[1], g[2]); - - bld.emit(BRW_OPCODE_ENDIF); - bld.MUL( x, g[1], g[2]); - - v->calculate_cfg(); - lower_scoreboard(v); - - bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 0); - EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); - EXPECT_EQ(add->sched, tgl_swsb_regdist(7)); - - /* Note that the ROL will have RegDist 2 and not 7, illustrating the - * physical CFG edge between the then-block and the else-block. - */ - bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 0); - EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); - EXPECT_EQ(rol->sched, tgl_swsb_regdist(2)); - - bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); - EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); - EXPECT_EQ(mul->sched, tgl_swsb_regdist(2)); -} - -TEST_F(scoreboard_test, gfx125_RaR_over_different_pipes) -{ - devinfo->verx10 = 125; - brw_init_isa_info(&compiler->isa, devinfo); - - fs_reg a = v->vgrf(glsl_int_type()); - fs_reg b = v->vgrf(glsl_int_type()); - fs_reg f = v->vgrf(glsl_float_type()); - fs_reg x = v->vgrf(glsl_int_type()); - - bld.ADD(f, x, x); - bld.ADD(a, x, x); - bld.ADD(x, b, b); - - v->calculate_cfg(); - bblock_t *block0 = v->cfg->blocks[0]; - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - lower_scoreboard(v); - ASSERT_EQ(0, block0->start_ip); - ASSERT_EQ(2, block0->end_ip); - - EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 1)->sched, tgl_swsb_null()); - EXPECT_EQ(instruction(block0, 2)->sched, tgl_swsb_regdist(1)); -} diff --git a/src/intel/compiler/elk/tests/gen11/cr0.asm b/src/intel/compiler/elk/tests/gen11/cr0.asm deleted file mode 100644 index a6213bb0f93..00000000000 --- a/src/intel/compiler/elk/tests/gen11/cr0.asm +++ /dev/null @@ -1,7 +0,0 @@ -and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch }; diff --git a/src/intel/compiler/elk/tests/gen11/cr0.expected b/src/intel/compiler/elk/tests/gen11/cr0.expected deleted file mode 100644 index 60e24ef73ef..00000000000 --- a/src/intel/compiler/elk/tests/gen11/cr0.expected +++ /dev/null @@ -1,7 +0,0 @@ -05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff -05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff -05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff -05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff -06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00 -06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00 -06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen11/rol.asm b/src/intel/compiler/elk/tests/gen11/rol.asm deleted file mode 100644 index e8eba29ff9d..00000000000 --- a/src/intel/compiler/elk/tests/gen11/rol.asm +++ /dev/null @@ -1 +0,0 @@ -rol(16) g3<1>UD g2<0,1,0>UD g2.1<0,1,0>UD { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen11/rol.expected b/src/intel/compiler/elk/tests/gen11/rol.expected deleted file mode 100644 index e9daccab7e4..00000000000 --- a/src/intel/compiler/elk/tests/gen11/rol.expected +++ /dev/null @@ -1 +0,0 @@ -0f 00 80 00 08 02 60 20 40 00 00 02 44 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen11/ror.asm b/src/intel/compiler/elk/tests/gen11/ror.asm deleted file mode 100644 index 4a83a26ada4..00000000000 --- a/src/intel/compiler/elk/tests/gen11/ror.asm +++ /dev/null @@ -1 +0,0 @@ -ror(16) g3<1>UD g2<0,1,0>UD g2.1<0,1,0>UD { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen11/ror.expected b/src/intel/compiler/elk/tests/gen11/ror.expected deleted file mode 100644 index 1778601e0bc..00000000000 --- a/src/intel/compiler/elk/tests/gen11/ror.expected +++ /dev/null @@ -1 +0,0 @@ -0e 00 80 00 08 02 60 20 40 00 00 02 44 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen12.5/add3.asm b/src/intel/compiler/elk/tests/gen12.5/add3.asm deleted file mode 100644 index 1e81dd0031f..00000000000 --- a/src/intel/compiler/elk/tests/gen12.5/add3.asm +++ /dev/null @@ -1,7 +0,0 @@ -add3(8) g118<1>D -g117<8,8,1>D g114<8,8,1>D g115<1,1,1>D { align1 1Q I@2 }; -add3(16) g55<1>D g50<8,8,1>D g46<8,8,1>D -g53<1,1,1>D { align1 1H @2 $5.dst }; -add3(16) g111<1>D -g40<8,8,1>D -g88<8,8,1>D g111<1,1,1>D { align1 1H I@1 }; -add3(16) g49<1>D 0x0008UW g47<8,8,1>D g26<1,1,1>D { align1 1H I@4 }; -add3(16) g55<1>D 0x0008UW g53<8,8,1>D g65<1,1,1>D { align1 2H I@3 }; -add3(8) g57<1>D g52<8,8,1>D (abs)g48<8,8,1>D (abs)g59<1,1,1>D { align1 1Q I@4 }; -add3(16) g51<1>D g63<8,8,1>D -g122<8,8,1>D (abs)g27<1,1,1>D { align1 1H I@7 }; diff --git a/src/intel/compiler/elk/tests/gen12.5/add3.expected b/src/intel/compiler/elk/tests/gen12.5/add3.expected deleted file mode 100644 index e6146920beb..00000000000 --- a/src/intel/compiler/elk/tests/gen12.5/add3.expected +++ /dev/null @@ -1,7 +0,0 @@ -52 1a 03 00 68 2e 04 76 05 75 0e 0e 05 72 05 73 -52 a5 04 00 68 0e 04 37 05 32 2e 0e 05 2e 05 35 -52 19 04 00 68 2e 04 6f 05 28 8e 0e 05 58 05 6f -52 1c 04 00 60 41 04 31 08 00 0e 0e 05 2f 05 1a -52 1b 24 00 60 41 04 37 08 00 0e 0e 05 35 05 41 -52 1c 03 00 68 0e 04 39 05 34 5e 0e 05 30 05 3b -52 1f 04 00 68 0e 04 33 05 3f 9e 0e 05 7a 05 1b diff --git a/src/intel/compiler/elk/tests/gen12.5/send.asm b/src/intel/compiler/elk/tests/gen12.5/send.asm deleted file mode 100644 index 6321737809f..00000000000 --- a/src/intel/compiler/elk/tests/gen12.5/send.asm +++ /dev/null @@ -1,30 +0,0 @@ -(+f0.0.any8h) send(1) g57UD g58UD nullUD 0x6210c500 0x02000000 - ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti ) BTI 2 base_offset 0 { align1 WE_all 1N $5 }; -(+f0.0.any8h) send(1) g28UD g29UD nullUD 0x6210c500 0x02000000 - ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti ) BTI 2 base_offset 0 { align1 WE_all 1N $2 }; -(+f0.0.any32h) send(1) g57UD g58UD nullUD 0x6210c500 0x02000000 - ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, src1_len = 0 bti ) BTI 2 base_offset 0 { align1 WE_all 1N $0 }; -send(8) nullUD g79UD g10UD 0x6200f506 0x04000100 - ugm MsgDesc: ( store_cmask, a32, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 4 bti ) BTI 4 base_offset 0 { align1 1Q $0 }; -send(16) nullUD g9UD g7UD 0x44000504 a0.1<0>UD - ugm MsgDesc: ( store, a32, d32, V1, L1STATE_L3MOCS dst_len = 0, src0_len = 2, src1_len = 0 ss ) surface_state_index 0 { align1 1H @1 $0 }; -send(1) g4UD g0UD nullUD 0x0210151f 0x00000000 - tgm MsgDesc: ( fence, a32, tile, evict, normal_routing dst_len = 1, src0_len = 1, src1_len = 0 flat ) base_offset 0 { align1 WE_all 1N $3 }; -send(8) nullUD g36UD g37UD 0x02000b04 0x00000040 - slm MsgDesc: ( store, a32, d16u32, V1, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 1 flat ) base_offset 0 { align1 1Q $1 }; -send(8) nullUD g34UD g35UD 0x02000b04 0x00000040 - slm MsgDesc: ( store, a32, d16u32, V1, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 1 flat ) base_offset 0 { align1 1Q $0 }; -send(8) nullUD g6UD g7UD 0x0200f506 0x00000100 - slm MsgDesc: ( store_cmask, a32, d32, xyzw, L1STATE_L3MOCS dst_len = 0, src0_len = 1, src1_len = 4 flat ) base_offset 0 { align1 1Q $6 }; -send(16) nullUD g82UD g91UD 0x04040519 0x00000080 - slm MsgDesc: ( atomic_or, a32, d32, V1, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = 2 flat ) base_offset 0 { align1 2H $0 }; -send(1) g10UD g0UD nullUD 0x0210011f 0x00000000 - slm MsgDesc: ( fence, a32, threadgroup, none, normal_routing dst_len = 1, src0_len = 1, src1_len = 0 flat ) base_offset 0 { align1 WE_all 1N $1 }; -send(1) g23UD g117UD nullUD 0x2210c500 a0.1<0>UD - ugm MsgDesc: ( load, a32, d32, V8, transpose, L1STATE_L3MOCS dst_len = 1, src0_len = 1, bss ) src1_len = 0 ex_bso surface_state_index 0 { align1 WE_all 1N @1 $10 }; -send(8) nullUD g14UD g24UD 0x040350fc a0.1<0>UD - dp data 1 MsgDesc: (DC typed surface write, Surface = 252, SIMD16, Mask = 0x0) src1_len = 4 ex_bso mlen 2 rlen 0 { align1 1Q @1 $5 }; -send(8) nullUD g51UD g52UD 0x02000000 0x00000040 - rt accel MsgDesc: SIMD8, mlen 1 ex_mlen 1 rlen 0 { align1 1Q $2 }; -send(16) nullUD g88UD g98UD 0x02000100 0x00000080 - rt accel MsgDesc: SIMD16, mlen 1 ex_mlen 2 rlen 0 { align1 1H $6 }; diff --git a/src/intel/compiler/elk/tests/gen12.5/send.expected b/src/intel/compiler/elk/tests/gen12.5/send.expected deleted file mode 100644 index 51616dd2b3d..00000000000 --- a/src/intel/compiler/elk/tests/gen12.5/send.expected +++ /dev/null @@ -1,15 +0,0 @@ -31 45 00 88 00 00 0c 39 8e 3a 00 fa 00 00 30 04 -31 42 00 88 00 00 0c 1c 8e 1d 00 fa 00 00 30 04 -31 40 00 8c 00 00 0c 39 8e 3a 00 fa 00 00 30 04 -31 40 03 00 00 00 00 00 8c 4f 0c fa 25 0a 3c 04 -31 90 04 00 00 01 02 00 14 09 08 fa 04 07 00 04 -31 43 00 80 00 00 0c 04 0c 00 3e da 00 00 04 00 -31 41 03 00 00 00 00 00 0c 24 08 e6 0c 25 02 00 -31 40 03 00 00 00 00 00 0c 22 08 e6 0c 23 02 00 -31 46 03 00 00 00 00 00 0c 06 0c ea 24 07 3c 00 -31 40 24 00 00 00 00 00 14 52 32 ea 14 5b 00 01 -31 41 00 80 00 00 0c 0a 0c 00 3e e2 00 00 00 00 -31 9a 00 80 80 01 0e 17 8c 75 00 fa 00 00 30 00 -31 95 03 00 80 01 02 00 14 0e f8 c1 24 18 d4 00 -31 42 03 00 00 00 00 00 0c 33 00 80 0c 34 00 00 -31 46 04 00 00 00 00 00 0c 58 00 82 14 62 00 00 diff --git a/src/intel/compiler/elk/tests/gen12.5/swsb.asm b/src/intel/compiler/elk/tests/gen12.5/swsb.asm deleted file mode 100644 index 4a7b9af8daf..00000000000 --- a/src/intel/compiler/elk/tests/gen12.5/swsb.asm +++ /dev/null @@ -1,23 +0,0 @@ -mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@1 }; -mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@2 }; -mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@3 }; -mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@4 }; -mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@5 }; -mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@6 }; -mul(8) g37<1>D g99<8,8,1>D g36<16,8,2>UW { align1 1Q I@7 }; - -mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@1 }; -mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@2 }; -mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@3 }; -mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@4 }; -mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@5 }; -mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@6 }; -mov(8) g36<1>UD g35<8,8,1>F { align1 1Q F@7 }; - -add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@1 }; -add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@2 }; -add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@3 }; -add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@4 }; -add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@5 }; -add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@6 }; -add(1) a0<1>UD a0<0,1,0>UD 0x00000800UD { align1 WE_all 1N A@7 }; \ No newline at end of file diff --git a/src/intel/compiler/elk/tests/gen12.5/swsb.expected b/src/intel/compiler/elk/tests/gen12.5/swsb.expected deleted file mode 100644 index fef186c7079..00000000000 --- a/src/intel/compiler/elk/tests/gen12.5/swsb.expected +++ /dev/null @@ -1,21 +0,0 @@ -41 19 03 00 60 06 05 25 05 63 46 01 06 24 56 00 -41 1a 03 00 60 06 05 25 05 63 46 01 06 24 56 00 -41 1b 03 00 60 06 05 25 05 63 46 01 06 24 56 00 -41 1c 03 00 60 06 05 25 05 63 46 01 06 24 56 00 -41 1d 03 00 60 06 05 25 05 63 46 01 06 24 56 00 -41 1e 03 00 60 06 05 25 05 63 46 01 06 24 56 00 -41 1f 03 00 60 06 05 25 05 63 46 01 06 24 56 00 -61 11 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 -61 12 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 -61 13 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 -61 14 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 -61 15 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 -61 16 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 -61 17 03 00 20 0a 05 24 05 23 46 00 00 00 00 00 -40 09 00 80 20 82 01 10 00 10 00 02 00 08 00 00 -40 0a 00 80 20 82 01 10 00 10 00 02 00 08 00 00 -40 0b 00 80 20 82 01 10 00 10 00 02 00 08 00 00 -40 0c 00 80 20 82 01 10 00 10 00 02 00 08 00 00 -40 0d 00 80 20 82 01 10 00 10 00 02 00 08 00 00 -40 0e 00 80 20 82 01 10 00 10 00 02 00 08 00 00 -40 0f 00 80 20 82 01 10 00 10 00 02 00 08 00 00 diff --git a/src/intel/compiler/elk/tests/gen12/dp4a.asm b/src/intel/compiler/elk/tests/gen12/dp4a.asm deleted file mode 100644 index 5ae00c8aae3..00000000000 --- a/src/intel/compiler/elk/tests/gen12/dp4a.asm +++ /dev/null @@ -1,33 +0,0 @@ -dp4a(8) g10<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>D { align1 1Q @1 }; -dp4a(8) g10<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>UD { align1 1Q @1 }; -dp4a(8) g10<1>D g2<8,8,1>D g8<8,8,1>D g9<1,1,1>D { align1 1Q @1 }; -dp4a(8) g10<1>D g2<8,8,1>D g8<8,8,1>D g9<1,1,1>UD { align1 1Q @1 }; -dp4a(8) g10<1>UD g2<8,8,1>UD g6<8,8,1>UD g7<1,1,1>UD { align1 1Q @1 }; -dp4a(8) g10<1>UD g2<8,8,1>UD g8<8,8,1>UD g9<1,1,1>UD { align1 1Q @1 }; -dp4a(8) g5<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>D { align1 1Q @3 $0.dst }; -dp4a(8) g5<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>UD { align1 1Q @3 $0.dst }; -dp4a(8) g5<1>UD g2<8,8,1>UD g3<8,8,1>UD g4<1,1,1>UD { align1 1Q @3 $0.dst }; -dp4a(8) g6<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>D { align1 1Q @4 $1.dst }; -dp4a(8) g6<1>D g2<8,8,1>D g3<8,8,1>D g4<1,1,1>UD { align1 1Q @4 $1.dst }; -dp4a(8) g6<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>D { align1 1Q @4 $0.dst }; -dp4a(8) g6<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>UD { align1 1Q @4 $0.dst }; -dp4a(8) g6<1>UD g2<8,8,1>UD g3<8,8,1>UD g4<1,1,1>UD { align1 1Q @4 $1.dst }; -dp4a(8) g6<1>UD g2<8,8,1>UD g4<8,8,1>UD g5<1,1,1>UD { align1 1Q @4 $0.dst }; -dp4a(8) g7<1>D g2<8,8,1>D g5<8,8,1>D g6<1,1,1>D { align1 1Q @1 }; -dp4a(8) g7<1>D g2<8,8,1>D g5<8,8,1>D g6<1,1,1>UD { align1 1Q @1 }; -dp4a(8) g7<1>UD g2<8,8,1>UD g5<8,8,1>UD g6<1,1,1>UD { align1 1Q @1 }; -dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>D { align1 1Q @3 $0.dst }; -dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>D { align1 1Q @4 $0.dst }; -dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>UD { align1 1Q @3 $0.dst }; -dp4a(8) g8<1>D g2<8,8,1>D g4<8,8,1>D g5<1,1,1>UD { align1 1Q @4 $0.dst }; -dp4a(8) g8<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>D { align1 1Q @1 }; -dp4a(8) g8<1>D g2<8,8,1>D g6<8,8,1>D g7<1,1,1>UD { align1 1Q @1 }; -dp4a(8) g8<1>UD g2<8,8,1>UD g4<8,8,1>UD g5<1,1,1>UD { align1 1Q @3 $0.dst }; -dp4a(8) g8<1>UD g2<8,8,1>UD g4<8,8,1>UD g5<1,1,1>UD { align1 1Q @4 $0.dst }; -dp4a(8) g8<1>UD g2<8,8,1>UD g6<8,8,1>UD g7<1,1,1>UD { align1 1Q @1 }; -dp4a.sat(8) g10<1>D g5<8,8,1>D g6<8,8,1>D g7<1,1,1>D { align1 1Q @1 $2.dst }; -dp4a.sat(8) g10<1>D g5<8,8,1>D g6<8,8,1>D g7<1,1,1>UD { align1 1Q @1 $2.dst }; -dp4a.sat(8) g10<1>UD g5<8,8,1>UD g6<8,8,1>UD g7<1,1,1>UD { align1 1Q @1 $2.dst }; -dp4a.sat(8) g8<1>D g5<8,8,1>D g3<8,8,1>D g4<1,1,1>D { align1 1Q $2.dst }; -dp4a.sat(8) g8<1>D g5<8,8,1>D g3<8,8,1>D g4<1,1,1>UD { align1 1Q $2.dst }; -dp4a.sat(8) g8<1>UD g5<8,8,1>UD g3<8,8,1>UD g4<1,1,1>UD { align1 1Q $2.dst }; diff --git a/src/intel/compiler/elk/tests/gen12/dp4a.expected b/src/intel/compiler/elk/tests/gen12/dp4a.expected deleted file mode 100644 index 44904c296ff..00000000000 --- a/src/intel/compiler/elk/tests/gen12/dp4a.expected +++ /dev/null @@ -1,33 +0,0 @@ -58 01 03 00 68 0e 04 0a 05 02 0e 0e 05 06 05 07 -58 01 03 00 68 0e 04 0a 05 02 0a 0e 05 06 05 07 -58 01 03 00 68 0e 04 0a 05 02 0e 0e 05 08 05 09 -58 01 03 00 68 0e 04 0a 05 02 0a 0e 05 08 05 09 -58 01 03 00 28 0a 04 0a 05 02 0a 0a 05 06 05 07 -58 01 03 00 28 0a 04 0a 05 02 0a 0a 05 08 05 09 -58 b0 03 00 68 0e 04 05 05 02 0e 0e 05 03 05 04 -58 b0 03 00 68 0e 04 05 05 02 0a 0e 05 03 05 04 -58 b0 03 00 28 0a 04 05 05 02 0a 0a 05 03 05 04 -58 c1 03 00 68 0e 04 06 05 02 0e 0e 05 03 05 04 -58 c1 03 00 68 0e 04 06 05 02 0a 0e 05 03 05 04 -58 c0 03 00 68 0e 04 06 05 02 0e 0e 05 04 05 05 -58 c0 03 00 68 0e 04 06 05 02 0a 0e 05 04 05 05 -58 c1 03 00 28 0a 04 06 05 02 0a 0a 05 03 05 04 -58 c0 03 00 28 0a 04 06 05 02 0a 0a 05 04 05 05 -58 01 03 00 68 0e 04 07 05 02 0e 0e 05 05 05 06 -58 01 03 00 68 0e 04 07 05 02 0a 0e 05 05 05 06 -58 01 03 00 28 0a 04 07 05 02 0a 0a 05 05 05 06 -58 b0 03 00 68 0e 04 08 05 02 0e 0e 05 04 05 05 -58 c0 03 00 68 0e 04 08 05 02 0e 0e 05 04 05 05 -58 b0 03 00 68 0e 04 08 05 02 0a 0e 05 04 05 05 -58 c0 03 00 68 0e 04 08 05 02 0a 0e 05 04 05 05 -58 01 03 00 68 0e 04 08 05 02 0e 0e 05 06 05 07 -58 01 03 00 68 0e 04 08 05 02 0a 0e 05 06 05 07 -58 b0 03 00 28 0a 04 08 05 02 0a 0a 05 04 05 05 -58 c0 03 00 28 0a 04 08 05 02 0a 0a 05 04 05 05 -58 01 03 00 28 0a 04 08 05 02 0a 0a 05 06 05 07 -58 92 03 00 6c 0e 04 0a 05 05 0e 0e 05 06 05 07 -58 92 03 00 6c 0e 04 0a 05 05 0a 0e 05 06 05 07 -58 92 03 00 2c 0a 04 0a 05 05 0a 0a 05 06 05 07 -58 22 03 00 6c 0e 04 08 05 05 0e 0e 05 03 05 04 -58 22 03 00 6c 0e 04 08 05 05 0a 0e 05 03 05 04 -58 22 03 00 2c 0a 04 08 05 05 0a 0a 05 03 05 04 diff --git a/src/intel/compiler/elk/tests/gen12/send.asm b/src/intel/compiler/elk/tests/gen12/send.asm deleted file mode 100644 index 81119aa8ccf..00000000000 --- a/src/intel/compiler/elk/tests/gen12/send.asm +++ /dev/null @@ -1,43 +0,0 @@ -send(16) g113UD g12UD nullUD a0<0>UD 0x00000000 - dp data 1 MsgDesc: indirect ex_mlen 0 { align1 1H @1 $6 }; -(+f1.0) send(16) nullUD g15UD g17UD a0<0>UD 0x00000080 - dp data 1 MsgDesc: indirect ex_mlen 2 { align1 1H @1 $4 }; -send(8) g104UD g119UD nullUD 0x04116e13 0x00000000 - dp data 1 MsgDesc: (DC typed surface read, Surface = 19, SIMD8, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 2Q $8 }; -send(8) nullUD g92UD g117UD 0x020350fc a0.1<0>UD - dp data 1 MsgDesc: (DC typed surface write, Surface = 252, SIMD16, Mask = 0x0) mlen 1 rlen 0 { align1 1Q @1 $8 }; -(+f0.0.any8h) send(8) g55UD g118UD nullUD 0x02184201 0x00000000 - data MsgDesc: (DC unaligned OWORD block read, bti 1, 2) mlen 1 ex_mlen 0 rlen 1 { align1 WE_all 1Q @3 $9 }; -send(8) nullUD g126UD nullUD 0x02000000 0x00000000 - thread_spawner MsgDesc: mlen 1 ex_mlen 0 rlen 0 { align1 WE_all 1Q @1 EOT }; -send(8) g18UD g24UD nullUD 0x04115e10 0x00000000 - dp data 1 MsgDesc: (DC typed surface read, Surface = 16, SIMD16, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 1Q $1 }; -send(8) g19UD g28UD nullUD 0x04116e10 0x00000000 - dp data 1 MsgDesc: (DC typed surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 2Q @7 $2 }; -send(16) g50UD g36UD nullUD a0<0>UD 0x00000000 - sampler MsgDesc: indirect ex_mlen 0 { align1 1H @1 $3 }; -send(8) nullUD g25UD g21UD 0x02035001 0x00000100 - dp data 1 MsgDesc: (DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q $9 }; -send(8) g5UD g25UD nullUD 0x02415001 0x00000000 - dp data 1 MsgDesc: (DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 1 ex_mlen 0 rlen 4 { align1 1Q $10 }; -send(8) g27UD g35UD nullUD 0x04146efd 0x00000000 - dp data 1 MsgDesc: (DC A64 untyped surface read, Surface = 253, SIMD8, Mask = 0xe) mlen 2 ex_mlen 0 rlen 1 { align1 1Q @1 $0 }; -send(8) nullUD g36UD g38UD 0x04035001 0x00000100 - dp data 1 MsgDesc: (DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q @1 $1 }; -send(8) nullUD g126UD g118UD 0x02080007 0x00000200 - urb MsgDesc: offset 0 SIMD8 write mlen 1 ex_mlen 8 rlen 0 { align1 1Q @1 EOT }; -send(8) g14UD g37UD nullUD 0x02110401 0x00000000 - data MsgDesc: (DC byte scattered read, bti 1, 4) mlen 1 ex_mlen 0 rlen 1 { align1 1Q @1 $0 }; -send(1) g100UD g0UD nullUD 0x0219e000 0x00000000 - data MsgDesc: (DC mfence, bti 0, 32) mlen 1 ex_mlen 0 rlen 1 { align1 WE_all 1N $1 }; -send(1) g15UD g0UD nullUD 0x0219e000 0x00000000 - data MsgDesc: (DC mfence, bti 0, 32) mlen 1 ex_mlen 0 rlen 1 { align1 WE_all 1N $5 }; - -sendc(16) nullUD g119UD nullUD 0x10031000 0x00000000 - render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 0 rlen 0 { align1 1H @1 EOT }; -sendc(8) nullUD g125UD g123UD 0x04031400 0x00000080 - render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 2 ex_mlen 2 rlen 0 { align1 1Q @1 EOT }; -sendc(16) nullUD g119UD nullUD 0x10031000 0x00000000 - render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 ex_mlen 0 rlen 0 { align1 1H @1 EOT }; -sendc(16) nullUD g123UD g119UD 0x08031000 0x00000100 - render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 4 ex_mlen 4 rlen 0 { align1 1H @1 EOT }; diff --git a/src/intel/compiler/elk/tests/gen12/send.expected b/src/intel/compiler/elk/tests/gen12/send.expected deleted file mode 100644 index 3ba1ebb53c2..00000000000 --- a/src/intel/compiler/elk/tests/gen12/send.expected +++ /dev/null @@ -1,21 +0,0 @@ -31 96 04 00 00 00 05 71 04 0c 00 c0 00 00 00 00 -31 94 84 01 00 00 01 00 04 0f 00 c0 14 11 00 00 -31 48 13 00 00 00 0c 68 14 77 26 cc 00 00 5a 00 -31 98 03 00 00 01 02 00 0c 5c f8 c1 04 75 d4 00 -31 b9 03 88 00 00 0c 37 0c 76 02 a4 00 00 10 02 -31 01 03 80 04 00 00 00 0c 7e 00 70 00 00 00 00 -31 41 03 00 00 00 0c 12 14 18 20 cc 00 00 56 00 -31 f2 13 00 00 00 0c 13 14 1c 20 cc 00 00 5a 00 -31 93 04 00 00 00 05 32 04 24 00 20 00 00 00 00 -31 49 03 00 00 00 00 00 0c 19 02 c0 24 15 d4 00 -31 4a 03 00 00 00 24 05 0c 19 02 c0 00 00 54 00 -31 90 03 00 00 00 0c 1b 14 23 fa cd 00 00 1a 01 -31 91 03 00 00 00 00 00 14 24 02 c0 24 26 d4 00 -31 01 03 00 04 00 00 00 0c 7e 0e 60 44 76 00 02 -31 90 03 00 00 00 0c 0e 0c 25 02 a8 00 00 40 00 -31 41 00 80 00 00 0c 64 0c 00 00 a0 00 00 78 02 -31 45 00 80 00 00 0c 0f 0c 00 00 a0 00 00 78 02 -32 01 04 00 04 00 00 00 44 77 00 50 00 00 c4 00 -32 01 03 00 04 00 00 00 14 7d 00 58 14 7b c4 00 -32 01 04 00 04 00 00 00 44 77 00 50 00 00 c4 00 -32 01 04 00 04 00 00 00 24 7b 00 50 24 77 c4 00 diff --git a/src/intel/compiler/elk/tests/gen12/swsb.asm b/src/intel/compiler/elk/tests/gen12/swsb.asm deleted file mode 100644 index 7c813356cf3..00000000000 --- a/src/intel/compiler/elk/tests/gen12/swsb.asm +++ /dev/null @@ -1,40 +0,0 @@ -cmp.l.f0.0(8) g55<1>UD g54<8,8,1>UD 0x00000290UD { align1 1Q @1 }; -mov(16) g6<1>D g20<8,8,1>W { align1 2H @2 }; -add(16) g122<1>F g98<8,8,1>F (abs)g102<8,8,1>F { align1 1H @3 }; -shl(8) g75<1>D g122<8,8,1>D 0x00000002UD { align1 1Q @4 }; -sel.l(4) g90.4<1>D g90.3<0,1,0>D g90.4<4,4,1>D { align1 WE_all 1N @5 }; -and(16) g58<1>UD g16<8,8,1>UD g56<8,8,1>UD { align1 1H @6 }; -or.nz.f0.0(16) null<1>UD g105<8,8,1>UD g103<8,8,1>UD { align1 1H @7 }; - -math cos(16) g17<1>F g15<8,8,1>F null<8,8,1>F { align1 1H @1 $0 }; -math exp(16) g1<1>F g29<8,8,1>F null<8,8,1>F { align1 1H @5 $2 }; -math sqrt(8) g9<1>HF g6<8,8,1>HF null<8,8,1>F { align1 1Q @1 $3 }; -math intdiv(8) g103<1>D g101<8,8,1>D g35<8,8,1>D { align1 1Q @4 $4 }; -math intmod(8) g101<1>D g97<8,8,1>D g76<8,8,1>D { align1 2Q @2 $5 }; -math inv(16) g10<1>F g8<8,8,1>F null<8,8,1>F { align1 2H @2 $6 }; -math log(16) g102<1>F g100<8,8,1>F null<8,8,1>F { align1 2H @1 $7 }; -math rsq(16) g76<1>F g74<8,8,1>F null<8,8,1>F { align1 1H @7 $8 }; -math sin(16) g123<1>F g121<8,8,1>F null<8,8,1>F { align1 1H @4 $9 }; -math sqrt(16) g43<1>F g47<8,8,1>F null<8,8,1>F { align1 2H @7 $10 }; -math cos(8) g103<1>HF g98<8,8,1>HF null<8,8,1>F { align1 1Q @3 $11 }; -math exp(8) g54<1>HF g52<8,8,1>HF null<8,8,1>F { align1 1Q @1 $12 }; -math intdiv(8) g35<1>D g31<8,8,1>D g33<8,8,1>D { align1 4Q @2 $13 }; -math intmod(8) g101<1>D g97<8,8,1>D g99<8,8,1>D { align1 2Q @4 $14 }; -math inv(8) g102<1>HF g92<8,8,1>HF null<8,8,1>F { align1 1Q @6 $15 }; - -sel.ge(16) g7<1>UW g7<16,16,1>UW g89<16,8,2>UW { align1 1H @7 $0.dst }; -mov(16) a0<1>UW 0x03e0UW { align1 WE_all 1H @3 $1.dst }; -add(16) g100<1>D g102<8,8,1>D -2114D { align1 1H @3 $2.dst }; -add(16) g100<1>D g105<8,8,1>D (abs)g18<8,8,1>D { align1 1H @3 $3.dst }; -add(16) g36<1>D g36<8,8,1>D g106<8,8,1>D { align1 1H @7 $4.dst }; -and(16) g49<1>UD g45<8,8,1>UD g47<8,8,1>UD { align1 1H @3 $5.dst }; -asr(16) g102<2>W g41<16,8,2>W g28<8,8,1>UD { align1 2H @6 $6.dst }; -cmp.l.f0.0(8) g97<1>F (abs)g96<8,8,1>F 0x3d4ccccdF /* 0.05F */ { align1 1Q @3 $7.dst }; -cmp.nz.f0.0(8) g100<1>F g98<8,8,1>F g99<8,8,1>F { align1 1Q @1 $8.dst }; -(+f0.0) sel(8) g64<1>D -g15<8,8,1>D g15<8,8,1>D { align1 1Q @1 $9.dst }; -mov(16) g15<1>UD g13<8,8,1>D { align1 1H @1 $10.dst }; -mul(8) acc0<1>UD g10<8,4,2>UD g101<16,8,2>UW { align1 1Q @7 $11.dst }; -or(16) g51<1>UW g51<16,16,1>UW g75<16,8,2>UW { align1 1H @7 $12.dst }; -sel.ge(16) g28<1>W g28<16,16,1>W g92<16,8,2>W { align1 2H @7 $13.dst }; -xor(16) g10<1>UD g10<8,8,1>UD g100<8,8,1>UD { align1 1H @7 $14.dst }; -and(16) g39<1>UD g35<8,8,1>UD g37<8,8,1>UD { align1 2H @5 $15.dst }; diff --git a/src/intel/compiler/elk/tests/gen12/swsb.expected b/src/intel/compiler/elk/tests/gen12/swsb.expected deleted file mode 100644 index 223c3fecdd9..00000000000 --- a/src/intel/compiler/elk/tests/gen12/swsb.expected +++ /dev/null @@ -1,38 +0,0 @@ -70 01 03 00 20 82 05 37 05 36 46 52 90 02 00 00 -61 02 24 00 60 05 05 06 05 14 46 00 00 00 00 00 -40 03 04 00 a0 0a 05 7a 05 62 46 0a 05 66 46 01 -69 04 03 00 60 86 05 4b 05 7a 46 02 02 00 00 00 -62 05 02 80 60 06 85 5a 64 5a 00 56 85 5a 34 00 -65 06 04 00 20 02 05 3a 05 10 46 02 05 38 46 00 -66 07 04 00 20 02 01 00 05 69 46 22 05 67 46 00 -38 90 04 00 a0 0a 05 11 05 0f 46 7a 01 00 46 00 -38 d2 04 00 a0 0a 05 01 05 1d 46 3a 01 00 46 00 -38 93 03 00 90 09 05 09 05 06 46 4a 01 00 46 00 -38 c4 03 00 60 06 05 67 05 65 46 c6 05 23 46 00 -38 a5 13 00 60 06 05 65 05 61 46 d6 05 4c 46 00 -38 a6 24 00 a0 0a 05 0a 05 08 46 1a 01 00 46 00 -38 97 24 00 a0 0a 05 66 05 64 46 2a 01 00 46 00 -38 f8 04 00 a0 0a 05 4c 05 4a 46 5a 01 00 46 00 -38 c9 04 00 a0 0a 05 7b 05 79 46 6a 01 00 46 00 -38 fa 24 00 a0 0a 05 2b 05 2f 46 4a 01 00 46 00 -38 bb 03 00 90 09 05 67 05 62 46 7a 01 00 46 00 -38 9c 03 00 90 09 05 36 05 34 46 3a 01 00 46 00 -38 ad 33 00 60 06 05 23 05 1f 46 c6 05 21 46 00 -38 ce 13 00 60 06 05 65 05 61 46 d6 05 63 46 00 -38 ef 03 00 90 09 05 66 05 5c 46 1a 01 00 46 00 -62 f0 04 00 10 01 05 07 05 07 58 41 06 59 56 00 -61 b1 04 80 10 41 01 10 00 00 00 00 e0 03 e0 03 -40 b2 04 00 60 86 05 64 05 66 46 06 be f7 ff ff -40 b3 04 00 60 06 05 64 05 69 46 06 05 12 46 01 -40 f4 04 00 60 06 05 24 05 24 46 06 05 6a 46 00 -65 b5 04 00 20 02 05 31 05 2d 46 02 05 2f 46 00 -6c e6 24 00 50 05 06 66 06 29 56 02 05 1c 46 00 -70 b7 03 00 a0 9a 05 61 05 60 46 5a cd cc 4c 3d -70 98 03 00 a0 0a 05 64 05 62 46 2a 05 63 46 00 -62 99 03 01 60 26 05 40 05 0f 46 06 05 0f 46 00 -61 9a 04 00 20 06 05 0f 05 0d 46 00 00 00 00 00 -41 fb 03 00 20 02 01 20 06 0a 44 01 06 65 56 00 -66 fc 04 00 10 01 05 33 05 33 58 01 06 4b 56 00 -62 fd 24 00 50 05 05 1c 05 1c 58 45 06 5c 56 00 -67 fe 04 00 20 02 05 0a 05 0a 46 02 05 64 46 00 -65 df 24 00 20 02 05 27 05 23 46 02 05 25 46 00 diff --git a/src/intel/compiler/elk/tests/gen12/sync.asm b/src/intel/compiler/elk/tests/gen12/sync.asm deleted file mode 100644 index a47c5dec28c..00000000000 --- a/src/intel/compiler/elk/tests/gen12/sync.asm +++ /dev/null @@ -1,33 +0,0 @@ -sync nop(16) null<0,1,0>UB { align1 WE_all 1H @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 1N @7 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 3N @7 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 5N @7 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @1 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @2 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @3 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @4 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @5 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @6 }; -sync nop(1) null<0,1,0>UB { align1 WE_all 7N @7 }; -sync nop(32) null<0,1,0>UB { align1 WE_all @1 }; -sync nop(8) null<0,1,0>UB { align1 WE_all 1Q @1 }; -sync allwr(16) null<0,1,0>UB { align1 1H }; -sync allwr(8) null<0,1,0>UB { align1 1Q }; diff --git a/src/intel/compiler/elk/tests/gen12/sync.expected b/src/intel/compiler/elk/tests/gen12/sync.expected deleted file mode 100644 index 2e98e4ab791..00000000000 --- a/src/intel/compiler/elk/tests/gen12/sync.expected +++ /dev/null @@ -1,33 +0,0 @@ -01 01 04 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 00 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 10 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 20 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 02 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 03 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 04 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 05 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 06 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 07 30 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 05 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 01 03 80 00 00 00 00 00 00 00 00 00 00 00 00 -01 00 04 00 00 00 00 00 00 00 00 30 00 00 00 00 -01 00 03 00 00 00 00 00 00 00 00 30 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/add.asm b/src/intel/compiler/elk/tests/gen9/add.asm deleted file mode 100644 index 5d751c29ab0..00000000000 --- a/src/intel/compiler/elk/tests/gen9/add.asm +++ /dev/null @@ -1,40 +0,0 @@ -add(8) g124<1>F g7<8,8,1>D 1D { align1 1Q }; -add(16) g120<1>F g11<8,8,1>D 1D { align1 1H }; -add(16) g4<1>F g1<0,1,0>F -g1.4<0,1,0>F { align1 1H }; -add(8) g3.8<1>UW g3<8,8,1>UW 0x0008UW { align1 WE_all 1Q }; -add(16) g3<1>D g18<8,8,1>D g12<8,8,1>D { align1 1H }; -add(16) g6<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all 1H }; -add(32) g10<1>UW g1.4<1,4,0>UW 0x11001010V { align1 WE_all }; -add(8) g2<1>D g96<8,8,1>D -1023D { align1 1Q }; -add(8) g4<1>F g5.6<0,1,0>F g7.2<0,1,0>F { align1 1Q }; -add(8) g53<1>DF g49<4,4,1>DF g51<4,4,1>DF { align1 1Q }; -add.sat(16) g5<1>UD g3<8,8,1>UD 0x00000001UD { align1 1H }; -add(1) g125.3<1>UD g0.3<0,1,0>UD g7<0,1,0>UD { align1 WE_all 1N }; -add(8) a0<1>UW g34<16,8,2>UW 0x0080UW { align1 1Q }; -add(8) g8<1>DF g2<0,1,0>DF g3.2<0,1,0>DF { align1 2Q }; -add(16) a0<1>UW g3<16,8,2>UW 0x0040UW { align1 1H }; -add.sat.le.f0.0(8) g125<1>F -g6<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; -add.z.f0.0(8) g8<1>F g2<0,1,0>F -g2.4<0,1,0>F { align1 1Q }; -add.z.f0.0(16) g3<1>F g2<0,1,0>F -g2.1<0,1,0>F { align1 1H }; -add(8) g3<1>UD g2<8,8,1>UD 0xffffffffUD { align1 1Q }; -(+f0.0) add(8) g15<1>D -g15<8,8,1>D 31D { align1 1Q }; -add(1) a0<1>UD a0<0,1,0>UD 0x00000200UD { align1 WE_all 1N }; -add.sat(8) g124<1>F g7<8,8,1>F -g6<8,8,1>F { align1 1Q }; -add(8) g8<1>UD g6<8,8,1>D 0x00000001UD { align1 1Q }; -add(16) g11<1>UD g9<8,8,1>D 0x00000001UD { align1 1H }; -(+f0.0) add(16) g8<1>D -g8<8,8,1>D 31D { align1 1H }; -add.sat(16) g126<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1H }; -add.sat(8) g124<1>F g17<8,8,1>D 1D { align1 1Q }; -add(16) g114<1>D g118<8,8,1>D g116<8,8,1>D { align1 2H }; -add.z.f0.0(16) null<1>D g120<8,8,1>D 1D { align1 1H }; -add.z.f0.0(16) null<1>D g116<8,8,1>D 1D { align1 2H }; -add.z.f0.0(8) g3<1>D g5<8,8,1>D g4<8,8,1>D { align1 1Q }; -add(16) g20<1>UD g17<8,8,1>UD 1D { align1 1H }; -add(8) g7<1>F -g6<4>.xyxyF g6<4>.zwzwF { align16 1Q }; -add(16) g9<1>F -g7<4>.xyxyF g7<4>.zwzwF { align16 1H }; -add(8) g7<1>UD g2<8,8,1>UD -g6<8,8,1>UD { align1 WE_all 1Q }; -add.le.f0.0(16) g1<1>D g3.1<0,1,0>D -g6<8,8,1>D { align1 1H }; -add.sat(8) g10<1>UD g9<8,8,1>UD 0x00000001UD { align1 1Q }; -add(1) g14<1>UD g14<0,1,0>UD 0x00000001UD { align1 WE_all 3N }; -add(8) g25<1>Q g22<4,4,1>Q -g24<4,4,1>Q { align1 1Q }; -add(8) g12<1>Q g5<4,4,1>Q -g11<4,4,1>Q { align1 2Q }; diff --git a/src/intel/compiler/elk/tests/gen9/add.expected b/src/intel/compiler/elk/tests/gen9/add.expected deleted file mode 100644 index 438b6f14325..00000000000 --- a/src/intel/compiler/elk/tests/gen9/add.expected +++ /dev/null @@ -1,40 +0,0 @@ -40 00 60 00 e8 0a 80 2f e0 00 8d 0e 01 00 00 00 -40 00 80 00 e8 0a 00 2f 60 01 8d 0e 01 00 00 00 -40 00 80 00 e8 3a 80 20 20 00 00 3a 30 40 00 00 -40 00 60 00 4c 12 70 20 60 00 8d 16 08 00 08 00 -40 00 80 00 28 0a 60 20 40 02 8d 0a 80 01 8d 00 -40 00 80 00 4c 12 c0 20 28 00 28 36 10 10 00 11 -40 00 a0 00 4c 12 40 21 28 00 28 36 10 10 00 11 -40 00 60 00 28 0a 40 20 00 0c 8d 0e 01 fc ff ff -40 00 60 00 e8 3a 80 20 b8 00 00 3a e8 00 00 00 -40 00 60 00 c8 32 a0 26 20 06 69 32 60 06 69 00 -40 00 80 80 08 02 a0 20 60 00 8d 06 01 00 00 00 -40 00 00 00 0c 02 ac 2f 0c 00 00 02 e0 00 00 00 -40 00 60 00 40 12 00 22 40 04 ae 16 80 00 80 00 -40 10 60 00 c8 32 00 21 40 00 00 32 70 00 00 00 -40 00 80 00 40 12 00 22 60 00 ae 16 40 00 40 00 -40 00 60 86 e8 3a a0 2f c0 40 8d 3e 00 00 00 3f -40 00 60 01 e8 3a 00 21 40 00 00 3a 50 40 00 00 -40 00 80 01 e8 3a 60 20 40 00 00 3a 44 40 00 00 -40 00 60 00 08 02 60 20 40 00 8d 06 ff ff ff ff -40 00 61 00 28 0a e0 21 e0 41 8d 0e 1f 00 00 00 -40 00 00 00 04 00 00 22 00 02 00 06 00 02 00 00 -40 00 60 80 e8 3a 80 2f e0 00 8d 3a c0 40 8d 00 -40 00 60 00 08 0a 00 21 c0 00 8d 06 01 00 00 00 -40 00 80 00 08 0a 60 21 20 01 8d 06 01 00 00 00 -40 00 81 00 28 0a 00 21 00 41 8d 0e 1f 00 00 00 -40 00 80 80 e8 3a c0 2f 40 00 00 3a 50 00 00 00 -40 00 60 80 e8 0a 80 2f 20 02 8d 0e 01 00 00 00 -40 20 80 00 28 0a 40 2e c0 0e 8d 0a 80 0e 8d 00 -40 00 80 01 20 0a 00 20 00 0f 8d 0e 01 00 00 00 -40 20 80 01 20 0a 00 20 80 0e 8d 0e 01 00 00 00 -40 00 60 01 28 0a 60 20 a0 00 8d 0a 80 00 8d 00 -40 00 80 00 08 02 80 22 20 02 8d 0e 01 00 00 00 -40 01 60 00 e8 3a ef 20 c4 40 64 3a ce 00 6e 00 -40 01 80 00 e8 3a 2f 21 e4 40 64 3a ee 00 6e 00 -40 00 60 00 0c 02 e0 20 40 00 8d 02 c0 40 8d 00 -40 00 80 06 28 0a 20 20 64 00 00 0a c0 40 8d 00 -40 00 60 80 08 02 40 21 20 01 8d 06 01 00 00 00 -40 10 00 00 0c 02 c0 21 c0 01 00 06 01 00 00 00 -40 00 60 00 28 4b 20 23 c0 02 69 4a 00 43 69 00 -40 10 60 00 28 4b 80 21 a0 00 69 4a 60 41 69 00 diff --git a/src/intel/compiler/elk/tests/gen9/and.asm b/src/intel/compiler/elk/tests/gen9/and.asm deleted file mode 100644 index 2f5d123fc84..00000000000 --- a/src/intel/compiler/elk/tests/gen9/and.asm +++ /dev/null @@ -1,29 +0,0 @@ -and(8) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1Q }; -and(16) g3<1>UD g2<0,1,0>UD ~g2.2<0,1,0>D { align1 1H }; -and(8) g8<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1Q }; -and(16) g18<1>UD g0.1<0,1,0>UW 0x07ffUW { align1 1H }; -and(1) g7<1>UD g5<0,1,0>UD 0x000000f0UD { align1 WE_all 1N }; -and.nz.f0.0(8) null<1>UD g36<8,8,1>UD g37<8,8,1>UD { align1 1Q }; -and.nz.f0.0(16) null<1>UD g70<8,8,1>UD g72<8,8,1>UD { align1 1H }; -and.z.f0.0(16) g21<1>UD g19<8,8,1>UD g17<8,8,1>UD { align1 1H }; -and(8) g61<1>UD g79<8,8,1>UD g32.1<8,4,2>UD { align1 2Q }; -and(8) g96<1>D ~g94<8,8,1>D ~g95<8,8,1>D { align1 1Q }; -and(16) g24<1>D ~g20<8,8,1>D ~g22<8,8,1>D { align1 1H }; -and(1) a0<1>UD g4<0,1,0>UD 0x000000ffUD { align1 WE_all 1N }; -and(16) g118<1>UD g114<8,8,1>UD 0x0000003fUD { align1 2H }; -and(1) g4<1>UD g20<0,1,0>UD 0x000000ffUD { align1 WE_all 3N }; -and.z.f0.0(8) null<1>D g13<8,8,1>UD 0x0000001fUD { align1 1Q }; -and(8) g21<1>UD g15<8,8,1>UD 0x00000003UD { align1 WE_all 1Q }; -and.z.f0.0(8) null<1>UD g20<8,8,1>UD 0x00000001UD { align1 1Q }; -and.z.f0.0(16) null<1>UD g45<8,8,1>UD 0x00000001UD { align1 1H }; -and(8) g4<1>UW g3<8,8,1>UW 0xfffcUW { align1 1Q }; -and(16) g13<1>UW g19<16,8,2>UW 0xfffcUW { align1 1H }; -and.nz.f0.0(8) null<1>UD ~g2.2<0,1,0>D g9<8,8,1>UD { align1 1Q }; -and(8) g18<1>UD ~g2.2<0,1,0>D g7<8,8,1>UD { align1 1Q }; -and.nz.f0.0(16) null<1>UD ~g2.2<0,1,0>D g14<8,8,1>UD { align1 1H }; -and(16) g30<1>UD ~g2.2<0,1,0>D g10<8,8,1>UD { align1 1H }; -and.nz.f0.0(8) g10<1>UD g9<8,8,1>UD 0x00000001UD { align1 1Q }; -and.nz.f0.0(16) g16<1>UD g14<8,8,1>UD 0x00000001UD { align1 1H }; -and.z.f0.0(8) g9<1>UD g8<8,8,1>UD 0x00000003UD { align1 1Q }; -and(8) g12<1>UQ g9<4,4,1>UQ g11<4,4,1>UQ { align1 1Q }; -and(8) g26<1>UQ g18<4,4,1>UQ g22<4,4,1>UQ { align1 2Q }; diff --git a/src/intel/compiler/elk/tests/gen9/and.expected b/src/intel/compiler/elk/tests/gen9/and.expected deleted file mode 100644 index 4f2b62ecd1a..00000000000 --- a/src/intel/compiler/elk/tests/gen9/and.expected +++ /dev/null @@ -1,29 +0,0 @@ -05 00 60 00 08 02 60 20 40 00 00 0a 48 40 00 00 -05 00 80 00 08 02 60 20 40 00 00 0a 48 40 00 00 -05 00 60 00 08 12 00 21 02 00 00 16 ff 07 ff 07 -05 00 80 00 08 12 40 22 02 00 00 16 ff 07 ff 07 -05 00 00 00 0c 02 e0 20 a0 00 00 06 f0 00 00 00 -05 00 60 02 00 02 00 20 80 04 8d 02 a0 04 8d 00 -05 00 80 02 00 02 00 20 c0 08 8d 02 00 09 8d 00 -05 00 80 01 08 02 a0 22 60 02 8d 02 20 02 8d 00 -05 10 60 00 08 02 a0 27 e0 09 8d 02 04 04 8a 00 -05 00 60 00 28 0a 00 2c c0 4b 8d 0a e0 4b 8d 00 -05 00 80 00 28 0a 00 23 80 42 8d 0a c0 42 8d 00 -05 00 00 00 04 02 00 22 80 00 00 06 ff 00 00 00 -05 20 80 00 08 02 c0 2e 40 0e 8d 06 3f 00 00 00 -05 10 00 00 0c 02 80 20 80 02 00 06 ff 00 00 00 -05 00 60 01 20 02 00 20 a0 01 8d 06 1f 00 00 00 -05 00 60 00 0c 02 a0 22 e0 01 8d 06 03 00 00 00 -05 00 60 01 00 02 00 20 80 02 8d 06 01 00 00 00 -05 00 80 01 00 02 00 20 a0 05 8d 06 01 00 00 00 -05 00 60 00 48 12 80 20 60 00 8d 16 fc ff fc ff -05 00 80 00 48 12 a0 21 60 02 ae 16 fc ff fc ff -05 00 60 02 00 0a 00 20 48 40 00 02 20 01 8d 00 -05 00 60 00 08 0a 40 22 48 40 00 02 e0 00 8d 00 -05 00 80 02 00 0a 00 20 48 40 00 02 c0 01 8d 00 -05 00 80 00 08 0a c0 23 48 40 00 02 40 01 8d 00 -05 00 60 02 08 02 40 21 20 01 8d 06 01 00 00 00 -05 00 80 02 08 02 00 22 c0 01 8d 06 01 00 00 00 -05 00 60 01 08 02 20 21 00 01 8d 06 03 00 00 00 -05 00 60 00 08 43 80 21 20 01 69 42 60 01 69 00 -05 10 60 00 08 43 40 23 40 02 69 42 c0 02 69 00 diff --git a/src/intel/compiler/elk/tests/gen9/asr.asm b/src/intel/compiler/elk/tests/gen9/asr.asm deleted file mode 100644 index 9beabc9cc8b..00000000000 --- a/src/intel/compiler/elk/tests/gen9/asr.asm +++ /dev/null @@ -1,6 +0,0 @@ -asr(8) g19<1>D g7<8,8,1>D 0x00000001UD { align1 1Q }; -asr(16) g20<1>D g2.7<0,1,0>D 0x0000001fUD { align1 1H }; -asr.nz.f0.0(8) null<1>D -g0<0,1,0>W 15D { align1 1Q }; -asr.nz.f0.0(16) null<1>D -g0<0,1,0>W 15D { align1 1H }; -asr(8) g2<1>D -g0<0,1,0>W 15D { align1 1Q }; -asr(16) g2<1>D -g0<0,1,0>W 15D { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/asr.expected b/src/intel/compiler/elk/tests/gen9/asr.expected deleted file mode 100644 index f1832cd80d7..00000000000 --- a/src/intel/compiler/elk/tests/gen9/asr.expected +++ /dev/null @@ -1,6 +0,0 @@ -0c 00 60 00 28 0a 60 22 e0 00 8d 06 01 00 00 00 -0c 00 80 00 28 0a 80 22 5c 00 00 06 1f 00 00 00 -0c 00 60 02 20 1a 00 20 00 40 00 0e 0f 00 00 00 -0c 00 80 02 20 1a 00 20 00 40 00 0e 0f 00 00 00 -0c 00 60 00 28 1a 40 20 00 40 00 0e 0f 00 00 00 -0c 00 80 00 28 1a 40 20 00 40 00 0e 0f 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/bfe.asm b/src/intel/compiler/elk/tests/gen9/bfe.asm deleted file mode 100644 index 93ec4fb18e9..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfe.asm +++ /dev/null @@ -1,4 +0,0 @@ -bfe(8) g96<1>UD g89<4,4,1>UD g30<4,4,1>UD g91<4,4,1>UD { align16 1Q }; -bfe(16) g13<1>UD g44<4,4,1>UD g115<4,4,1>UD g126<4,4,1>UD { align16 1H }; -bfe(8) g18<1>D g17<4,4,1>D g16<4,4,1>D g49<4,4,1>D { align16 1Q }; -bfe(16) g13<1>D g11<4,4,1>D g42<4,4,1>D g5<4,4,1>D { align16 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/bfe.expected b/src/intel/compiler/elk/tests/gen9/bfe.expected deleted file mode 100644 index d6a91b3c387..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfe.expected +++ /dev/null @@ -1,4 +0,0 @@ -18 01 60 00 00 90 1e 60 c8 91 05 39 3c 20 c7 16 -18 01 80 00 00 90 1e 0d c8 c1 02 39 e6 20 87 1f -18 01 60 00 00 48 1e 12 c8 11 01 39 20 20 47 0c -18 01 80 00 00 48 1e 0d c8 b1 00 39 54 20 47 01 diff --git a/src/intel/compiler/elk/tests/gen9/bfi1.asm b/src/intel/compiler/elk/tests/gen9/bfi1.asm deleted file mode 100644 index d2bfa85d7ce..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfi1.asm +++ /dev/null @@ -1,2 +0,0 @@ -bfi1(8) g20<1>UD g19<8,8,1>D g18<8,8,1>D { align1 1Q }; -bfi1(16) g16<1>UD g14<8,8,1>D g12<8,8,1>D { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/bfi1.expected b/src/intel/compiler/elk/tests/gen9/bfi1.expected deleted file mode 100644 index d8b4474c53e..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfi1.expected +++ /dev/null @@ -1,2 +0,0 @@ -19 00 60 00 08 0a 80 22 60 02 8d 0a 40 02 8d 00 -19 00 80 00 08 0a 00 22 c0 01 8d 0a 80 01 8d 00 diff --git a/src/intel/compiler/elk/tests/gen9/bfi2.asm b/src/intel/compiler/elk/tests/gen9/bfi2.asm deleted file mode 100644 index 1dadebe1753..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfi2.asm +++ /dev/null @@ -1,2 +0,0 @@ -bfi2(8) g31<1>UD g88<4,4,1>UD g90<4,4,1>UD g91<4,4,1>UD { align16 1Q }; -bfi2(16) g5<1>UD g42<4,4,1>UD g40<4,4,1>UD g126<4,4,1>UD { align16 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/bfi2.expected b/src/intel/compiler/elk/tests/gen9/bfi2.expected deleted file mode 100644 index 61eda29eaf4..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfi2.expected +++ /dev/null @@ -1,2 +0,0 @@ -1a 01 60 00 00 90 1e 1f c8 81 05 39 b4 20 c7 16 -1a 01 80 00 00 90 1e 05 c8 a1 02 39 50 20 87 1f diff --git a/src/intel/compiler/elk/tests/gen9/bfrev.asm b/src/intel/compiler/elk/tests/gen9/bfrev.asm deleted file mode 100644 index 44b45c53bae..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfrev.asm +++ /dev/null @@ -1,2 +0,0 @@ -bfrev(8) g5<1>UD g5<8,8,1>UD { align1 1Q }; -bfrev(16) g6<1>UD g8<8,8,1>UD { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/bfrev.expected b/src/intel/compiler/elk/tests/gen9/bfrev.expected deleted file mode 100644 index b4d7fb02205..00000000000 --- a/src/intel/compiler/elk/tests/gen9/bfrev.expected +++ /dev/null @@ -1,2 +0,0 @@ -17 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00 -17 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/break.asm b/src/intel/compiler/elk/tests/gen9/break.asm deleted file mode 100644 index 681b3d2c8a1..00000000000 --- a/src/intel/compiler/elk/tests/gen9/break.asm +++ /dev/null @@ -1,6 +0,0 @@ -break(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q }; -break(16) JIP: LABEL0 UIP: LABEL1 { align1 1H }; -LABEL0: -(+f0.0) break(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q }; -(+f0.0) break(16) JIP: LABEL1 UIP: LABEL1 { align1 1H }; -LABEL1: diff --git a/src/intel/compiler/elk/tests/gen9/break.expected b/src/intel/compiler/elk/tests/gen9/break.expected deleted file mode 100644 index f5448cdbdf3..00000000000 --- a/src/intel/compiler/elk/tests/gen9/break.expected +++ /dev/null @@ -1,4 +0,0 @@ -28 00 60 00 20 0e 00 20 40 00 00 00 20 00 00 00 -28 00 80 00 20 0e 00 20 30 00 00 00 10 00 00 00 -28 00 61 00 20 0e 00 20 20 00 00 00 20 00 00 00 -28 00 81 00 20 0e 00 20 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/cbit.asm b/src/intel/compiler/elk/tests/gen9/cbit.asm deleted file mode 100644 index a48d5e29182..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cbit.asm +++ /dev/null @@ -1,2 +0,0 @@ -cbit(8) g9<1>UD g31<8,8,1>UD { align1 1Q }; -cbit(16) g6<1>UD g8<8,8,1>UD { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/cbit.expected b/src/intel/compiler/elk/tests/gen9/cbit.expected deleted file mode 100644 index 8cb5ca16d1c..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cbit.expected +++ /dev/null @@ -1,2 +0,0 @@ -4d 00 60 00 08 02 20 21 e0 03 8d 00 00 00 00 00 -4d 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/cmp.asm b/src/intel/compiler/elk/tests/gen9/cmp.asm deleted file mode 100644 index 669224dcd0d..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cmp.asm +++ /dev/null @@ -1,104 +0,0 @@ -cmp.z.f0.0(8) null<1>F g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q }; -cmp.nz.f0.0(8) g59<1>DF g2.1<0,1,0>DF g59<4,4,1>DF { align1 1Q }; -cmp.nz.f0.0(8) g49<1>F g47<8,8,1>F g14.1<0,1,0>F { align1 1Q }; -cmp.nz.f0.0(8) null<1>D g7<8,8,1>D 0D { align1 1Q }; -cmp.z.f0.0(8) g5<1>D g4<8,8,1>D g2.5<0,1,0>D { align1 1Q }; -cmp.z.f0.0(16) g7<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1H }; -cmp.l.f0.0(16) g28<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H }; -cmp.ge.f0.0(16) g30<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H }; -cmp.nz.f0.0(8) g43<1>D g42<8,8,1>D g2.1<0,1,0>D { align1 1Q }; -cmp.z.f0.0(8) g86<1>DF (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q }; -cmp.le.f0.0(8) g108<1>D g106<8,8,1>D 0D { align1 1Q }; -cmp.nz.f0.0(8) null<1>DF g6.2<0,1,0>DF g66<4,4,1>DF { align1 1Q }; -cmp.l.f0.0(8) g5<1>DF g36<4,4,1>DF g53<4,4,1>DF { align1 1Q }; -cmp.ge.f0.0(8) g18<1>DF g36<4,4,1>DF g53<4,4,1>DF { align1 1Q }; -cmp.z.f0.0(8) g34<1>DF (abs)g106<4,4,1>DF g52<4,4,1>DF { align1 2Q }; -cmp.le.f0.0(16) g35<1>D g21<8,8,1>D 0D { align1 1H }; -cmp.nz.f0.0(8) null<1>DF g106<4,4,1>DF g50<4,4,1>DF { align1 2Q }; -cmp.nz.f0.0(8) g113<1>DF g3.1<0,1,0>DF g59<4,4,1>DF { align1 2Q }; -cmp.l.f0.0(8) null<1>UD g12<8,8,1>UD 0x00000004UD { align1 1Q }; -cmp.l.f0.0(8) g53<1>F g52<8,8,1>F g51<8,8,1>F { align1 1Q }; -cmp.ge.f0.0(8) g55<1>F g52<8,8,1>F g51<8,8,1>F { align1 1Q }; -cmp.ge.f0.0(8) g15<1>D (abs)g12<8,8,1>D 1D { align1 1Q }; -cmp.l.f0.0(8) null<1>D g6<0,1,0>D 2D { align1 1Q }; -(+f0.1) cmp.z.f0.1(8) null<1>D g8<8,8,1>D 0D { align1 1Q }; -cmp.nz.f0.0(16) g11<1>D g9<8,8,1>D 3D { align1 1H }; -(+f0.1) cmp.z.f0.1(16) null<1>D g11<8,8,1>D 0D { align1 1H }; -cmp.z.f0.0(8) null<1>D g22<8,8,1>D 1D { align1 1Q }; -cmp.z.f0.0(16) null<1>D g47<8,8,1>D 1D { align1 1H }; -cmp.ge.f0.0(8) g30<1>UD g29<8,8,1>UD g5.7<0,1,0>UD { align1 1Q }; -cmp.l.f0.0(8) g31<1>UD g29<8,8,1>UD g5.3<0,1,0>UD { align1 1Q }; -cmp.ge.f0.0(16) g50<1>UD g48<8,8,1>UD g7.7<0,1,0>UD { align1 1H }; -cmp.l.f0.0(16) g52<1>UD g48<8,8,1>UD g7.3<0,1,0>UD { align1 1H }; -cmp.nz.f0.0(16) g9<1>F g2.5<0,1,0>F g1.1<0,1,0>F { align1 1H }; -cmp.ge.f0.0(8) null<1>D g38<8,8,1>D 32D { align1 1Q }; -cmp.ge.f0.0(8) null<1>DF g21<4,4,1>DF g13<4,4,1>DF { align1 1Q }; -cmp.ge.f0.0(16) g3<1>D g1.1<0,1,0>D g1<0,1,0>D { align1 1H }; -cmp.l.f0.0(16) g5<1>D g1.1<0,1,0>D g1<0,1,0>D { align1 1H }; -cmp.z.f0.0(8) g25<1>F g4.3<0,1,0>F g4.1<0,1,0>F { align1 1Q }; -cmp.l.f0.0(8) g33<1>D g5<0,1,0>D 1D { align1 1Q }; -cmp.l.f0.0(8) g43<1>DF g39<4,4,1>DF g37<4,4,1>DF { align1 2Q }; -cmp.ge.f0.0(8) g46<1>DF g39<4,4,1>DF g37<4,4,1>DF { align1 2Q }; -cmp.l.f0.0(16) null<1>D g6<0,1,0>D 1D { align1 1H }; -cmp.z.f0.0(16) g62<1>F g12<8,8,1>F g6.3<0,1,0>F { align1 1H }; -cmp.nz.f0.0(8) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 1Q }; -cmp.nz.f0.0(16) null<1>F g2<0,1,0>F 0x0F /* 0F */ { align1 1H }; -cmp.ge.f0.0(16) null<1>UD g46<8,8,1>UD 0x00000040UD { align1 1H }; -cmp.z.f0.0(16) null<1>F g14<8,8,1>F g6.1<0,1,0>F { align1 1H }; -cmp.nz.f0.0(16) null<1>D g6<0,1,0>D 0D { align1 1H }; -cmp.l.f0.0(16) null<1>UD g39<8,8,1>UD 0x00000004UD { align1 1H }; -cmp.le.f0.0(8) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; -cmp.le.f0.0(16) null<1>F g2<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; -cmp.le.f0.0(8) g20<1>F g5.3<0,1,0>F 0x0F /* 0F */ { align1 1Q }; -cmp.ge.f0.0(8) null<1>F (abs)g26<8,8,1>F 0x5d5e0b6bF /* 1e+18F */ { align1 1Q }; -cmp.g.f0.0(8) g80<1>F (abs)g44<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; -cmp.ge.f0.0(16) null<1>D g67<8,8,1>D 32D { align1 1H }; -cmp.g.f0.0(8) null<1>F g124<8,8,1>F 0x0F /* 0F */ { align1 1Q }; -cmp.z.f0.0(8) g4<1>F g13<8,4,2>F g2.5<0,1,0>F { align1 2Q }; -cmp.g.f0.0(16) null<1>F g120<8,8,1>F 0x0F /* 0F */ { align1 1H }; -cmp.g.f0.0(16) g2<1>F (abs)g17<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; -cmp.l.f0.0(8) null<1>DF (abs)g5<0,1,0>DF g20<4,4,1>DF { align1 1Q }; -cmp.nz.f0.0(8) g29<1>D g22.1<8,4,2>D g3.2<0,1,0>D { align1 2Q }; -cmp.l.f0.0(8) null<1>DF g11<4,4,1>DF g8<4,4,1>DF { align1 2Q }; -cmp.nz.f0.0(8) g73<1>F g6.1<0,1,0>F g14<8,4,2>F { align1 2Q }; -cmp.g.f0.0(8) g7<1>D g2<0,1,0>D 0D { align1 1Q }; -cmp.l.f0.0(8) null<1>F g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q }; -cmp.l.f0.0(16) null<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H }; -cmp.le.f0.0(8) null<1>D g2<8,8,1>D 50D { align1 1Q }; -cmp.le.f0.0(16) null<1>D g2<8,8,1>D 50D { align1 1H }; -cmp.ge.f0.0(16) null<1>F g35<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; -cmp.le.f0.0(8) g4<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; -cmp.g.f0.0(8) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1Q }; -cmp.le.f0.0(16) g5<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; -cmp.g.f0.0(16) g7<1>UD g2<0,1,0>UD 0x00000001UD { align1 1H }; -cmp.le.f0.0(16) g121<1>F g27<8,8,1>F 0x461c3f9aF /* 9999.9F */ { align1 1H }; -cmp.z.f0.0(8) g5<1>D g14<8,4,2>D g3.1<0,1,0>D { align1 2Q }; -cmp.g.f0.0(8) null<1>D g5.2<0,1,0>D 31D { align1 1Q }; -cmp.g.f0.0(8) null<1>UD g4.2<0,1,0>UD 0x0000001fUD { align1 1Q }; -(+f0.1) cmp.nz.f0.1(8) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1Q }; -(+f0.1) cmp.nz.f0.1(16) null<1>UW g0<8,8,1>UW g0<8,8,1>UW { align1 1H }; -cmp.z.f0.0(16) null<1>D g1<8,8,1>D 1024D { align1 2H }; -cmp.l.f0.0(16) null<1>D g118<8,8,1>D 32D { align1 2H }; -cmp.nz.f0.0(8) null<1>UD g3<8,8,1>UD 0x00000000UD { align1 1Q }; -cmp.nz.f0.0(16) null<1>UD g3<8,8,1>UD 0x00000000UD { align1 1H }; -cmp.g.f0.0(16) null<1>D g2.1<0,1,0>D 0D { align1 1H }; -cmp.nz.f0.0(8) null<1>Q g6<4,4,1>Q g3<4,4,1>Q { align1 1Q }; -cmp.z.f0.0(8) g8<1>Q g5<4,4,1>Q g3<4,4,1>Q { align1 1Q }; -cmp.nz.f0.0(8) g2<1>Q g5<4,4,1>Q g3<4,4,1>Q { align1 1Q }; -cmp.nz.f0.0(8) null<1>Q g9<4,4,1>Q g4<4,4,1>Q { align1 2Q }; -cmp.z.f0.0(8) g17<1>Q g11<4,4,1>Q g4<4,4,1>Q { align1 2Q }; -cmp.nz.f0.0(8) g20<1>Q g11<4,4,1>Q g4<4,4,1>Q { align1 2Q }; -cmp.z.f0.0(8) null<1>UD g5<8,8,1>UD 0x00000000UD { align1 1Q }; -cmp.z.f0.0(16) null<1>UD g15<8,8,1>UD 0x00000000UD { align1 1H }; -cmp.g.f0.0(16) g1<1>D g8<8,8,1>D 0D { align1 1H }; -cmp.ge.f0.0(8) null<1>UD g10<8,8,1>UD g8<8,8,1>UD { align1 1Q }; -cmp.ge.f0.0(8) null<1>DF g37<4,4,1>DF g26<4,4,1>DF { align1 2Q }; -cmp.l.f0.0(8) null<1>Q g20<4,4,1>Q g25<4,4,1>Q { align1 1Q }; -cmp.l.f0.0(8) null<1>Q g2<4,4,1>Q g12<4,4,1>Q { align1 2Q }; -cmp.ge.f0.0(8) null<1>Q g20<4,4,1>Q g27<4,4,1>Q { align1 1Q }; -cmp.ge.f0.0(8) null<1>Q g2<4,4,1>Q g8<4,4,1>Q { align1 2Q }; -cmp.le.f0.0(8) null<1>UD g18<8,8,1>UD 0x000000ffUD { align1 1Q }; -cmp.le.f0.0(16) null<1>UD g32<8,8,1>UD 0x000000ffUD { align1 1H }; -cmp.z.f0.0(8) null<1>Q g12<4,4,1>Q g7<4,4,1>Q { align1 1Q }; -cmp.z.f0.0(8) null<1>Q g26<4,4,1>Q g12<4,4,1>Q { align1 2Q }; -cmp.g.f0.0(16) null<1>UD g4.2<0,1,0>UD 0x0000001fUD { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/cmp.expected b/src/intel/compiler/elk/tests/gen9/cmp.expected deleted file mode 100644 index 9e13e8c926b..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cmp.expected +++ /dev/null @@ -1,104 +0,0 @@ -10 00 60 01 e0 3a 00 20 80 02 8d 3e 00 00 80 bf -10 00 60 02 c8 32 60 27 48 00 00 32 60 07 69 00 -10 00 60 02 e8 3a 20 26 e0 05 8d 3a c4 01 00 00 -10 00 60 02 20 0a 00 20 e0 00 8d 0e 00 00 00 00 -10 00 60 01 28 0a a0 20 80 00 8d 0a 54 00 00 00 -10 00 80 01 28 0a e0 20 a0 00 8d 0a 54 00 00 00 -10 00 80 05 e8 3a 80 23 40 03 8d 3a 00 03 8d 00 -10 00 80 04 e8 3a c0 23 40 03 8d 3a 00 03 8d 00 -10 00 60 02 28 0a 60 25 40 05 8d 0a 44 00 00 00 -10 00 60 01 c8 32 c0 2a d0 20 00 32 80 08 69 00 -10 00 60 06 28 0a 80 2d 40 0d 8d 0e 00 00 00 00 -10 00 60 02 c0 32 00 20 d0 00 00 32 40 08 69 00 -10 00 60 05 c8 32 a0 20 80 04 69 32 a0 06 69 00 -10 00 60 04 c8 32 40 22 80 04 69 32 a0 06 69 00 -10 10 60 01 c8 32 40 24 40 2d 69 32 80 06 69 00 -10 00 80 06 28 0a 60 24 a0 02 8d 0e 00 00 00 00 -10 10 60 02 c0 32 00 20 40 0d 69 32 40 06 69 00 -10 10 60 02 c8 32 20 2e 68 00 00 32 60 07 69 00 -10 00 60 05 00 02 00 20 80 01 8d 06 04 00 00 00 -10 00 60 05 e8 3a a0 26 80 06 8d 3a 60 06 8d 00 -10 00 60 04 e8 3a e0 26 80 06 8d 3a 60 06 8d 00 -10 00 60 04 28 0a e0 21 80 21 8d 0e 01 00 00 00 -10 00 60 05 20 0a 00 20 c0 00 00 0e 02 00 00 00 -10 00 61 01 21 0a 00 20 00 01 8d 0e 00 00 00 00 -10 00 80 02 28 0a 60 21 20 01 8d 0e 03 00 00 00 -10 00 81 01 21 0a 00 20 60 01 8d 0e 00 00 00 00 -10 00 60 01 20 0a 00 20 c0 02 8d 0e 01 00 00 00 -10 00 80 01 20 0a 00 20 e0 05 8d 0e 01 00 00 00 -10 00 60 04 08 02 c0 23 a0 03 8d 02 bc 00 00 00 -10 00 60 05 08 02 e0 23 a0 03 8d 02 ac 00 00 00 -10 00 80 04 08 02 40 26 00 06 8d 02 fc 00 00 00 -10 00 80 05 08 02 80 26 00 06 8d 02 ec 00 00 00 -10 00 80 02 e8 3a 20 21 54 00 00 3a 24 00 00 00 -10 00 60 04 20 0a 00 20 c0 04 8d 0e 20 00 00 00 -10 00 60 04 c0 32 00 20 a0 02 69 32 a0 01 69 00 -10 00 80 04 28 0a 60 20 24 00 00 0a 20 00 00 00 -10 00 80 05 28 0a a0 20 24 00 00 0a 20 00 00 00 -10 00 60 01 e8 3a 20 23 8c 00 00 3a 84 00 00 00 -10 00 60 05 28 0a 20 24 a0 00 00 0e 01 00 00 00 -10 10 60 05 c8 32 60 25 e0 04 69 32 a0 04 69 00 -10 10 60 04 c8 32 c0 25 e0 04 69 32 a0 04 69 00 -10 00 80 05 20 0a 00 20 c0 00 00 0e 01 00 00 00 -10 00 80 01 e8 3a c0 27 80 01 8d 3a cc 00 00 00 -10 00 60 02 e0 3a 00 20 40 00 00 3e 00 00 00 00 -10 00 80 02 e0 3a 00 20 40 00 00 3e 00 00 00 00 -10 00 80 04 00 02 00 20 c0 05 8d 06 40 00 00 00 -10 00 80 01 e0 3a 00 20 c0 01 8d 3a c4 00 00 00 -10 00 80 02 20 0a 00 20 c0 00 00 0e 00 00 00 00 -10 00 80 05 00 02 00 20 e0 04 8d 06 04 00 00 00 -10 00 60 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f -10 00 80 06 e0 3a 00 20 40 00 8d 3e 00 00 00 3f -10 00 60 06 e8 3a 80 22 ac 00 00 3e 00 00 00 00 -10 00 60 04 e0 3a 00 20 40 23 8d 3e 6b 0b 5e 5d -10 00 60 03 e8 3a 00 2a 80 25 8d 3e 00 00 80 3f -10 00 80 04 20 0a 00 20 60 08 8d 0e 20 00 00 00 -10 00 60 03 e0 3a 00 20 80 0f 8d 3e 00 00 00 00 -10 10 60 01 e8 3a 80 20 a0 01 8a 3a 54 00 00 00 -10 00 80 03 e0 3a 00 20 00 0f 8d 3e 00 00 00 00 -10 00 80 03 e8 3a 40 20 20 22 8d 3e 00 00 80 3f -10 00 60 05 c0 32 00 20 a0 20 00 32 80 02 69 00 -10 10 60 02 28 0a a0 23 c4 02 8a 0a 68 00 00 00 -10 10 60 05 c0 32 00 20 60 01 69 32 00 01 69 00 -10 10 60 02 e8 3a 20 29 c4 00 00 3a c0 01 8a 00 -10 00 60 03 28 0a e0 20 40 00 00 0e 00 00 00 00 -10 00 60 05 e0 3a 00 20 90 00 00 3e 00 00 00 00 -10 00 80 05 e0 3a 00 20 d0 00 00 3e 00 00 00 00 -10 00 60 06 20 0a 00 20 40 00 8d 0e 32 00 00 00 -10 00 80 06 20 0a 00 20 40 00 8d 0e 32 00 00 00 -10 00 80 04 e0 3a 00 20 60 04 8d 3e 00 00 00 3f -10 00 60 06 08 02 80 20 40 00 00 06 01 00 00 00 -10 00 60 03 08 02 a0 20 40 00 00 06 01 00 00 00 -10 00 80 06 08 02 a0 20 40 00 00 06 01 00 00 00 -10 00 80 03 08 02 e0 20 40 00 00 06 01 00 00 00 -10 00 80 06 e8 3a 20 2f 60 03 8d 3e 9a 3f 1c 46 -10 10 60 01 28 0a a0 20 c0 01 8a 0a 64 00 00 00 -10 00 60 03 20 0a 00 20 a8 00 00 0e 1f 00 00 00 -10 00 60 03 00 02 00 20 88 00 00 06 1f 00 00 00 -10 00 61 02 41 12 00 20 00 00 8d 12 00 00 8d 00 -10 00 81 02 41 12 00 20 00 00 8d 12 00 00 8d 00 -10 20 80 01 20 0a 00 20 20 00 8d 0e 00 04 00 00 -10 20 80 05 20 0a 00 20 c0 0e 8d 0e 20 00 00 00 -10 00 60 02 00 02 00 20 60 00 8d 06 00 00 00 00 -10 00 80 02 00 02 00 20 60 00 8d 06 00 00 00 00 -10 00 80 03 20 0a 00 20 44 00 00 0e 00 00 00 00 -10 00 60 02 20 4b 00 20 c0 00 69 4a 60 00 69 00 -10 00 60 01 28 4b 00 21 a0 00 69 4a 60 00 69 00 -10 00 60 02 28 4b 40 20 a0 00 69 4a 60 00 69 00 -10 10 60 02 20 4b 00 20 20 01 69 4a 80 00 69 00 -10 10 60 01 28 4b 20 22 60 01 69 4a 80 00 69 00 -10 10 60 02 28 4b 80 22 60 01 69 4a 80 00 69 00 -10 00 60 01 00 02 00 20 a0 00 8d 06 00 00 00 00 -10 00 80 01 00 02 00 20 e0 01 8d 06 00 00 00 00 -10 00 80 03 28 0a 20 20 00 01 8d 0e 00 00 00 00 -10 00 60 04 00 02 00 20 40 01 8d 02 00 01 8d 00 -10 10 60 04 c0 32 00 20 a0 04 69 32 40 03 69 00 -10 00 60 05 20 4b 00 20 80 02 69 4a 20 03 69 00 -10 10 60 05 20 4b 00 20 40 00 69 4a 80 01 69 00 -10 00 60 04 20 4b 00 20 80 02 69 4a 60 03 69 00 -10 10 60 04 20 4b 00 20 40 00 69 4a 00 01 69 00 -10 00 60 06 00 02 00 20 40 02 8d 06 ff 00 00 00 -10 00 80 06 00 02 00 20 00 04 8d 06 ff 00 00 00 -10 00 60 01 20 4b 00 20 80 01 69 4a e0 00 69 00 -10 10 60 01 20 4b 00 20 40 03 69 4a 80 01 69 00 -10 00 80 03 00 02 00 20 88 00 00 06 1f 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/cont.asm b/src/intel/compiler/elk/tests/gen9/cont.asm deleted file mode 100644 index ca97a556e9c..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cont.asm +++ /dev/null @@ -1,4 +0,0 @@ -cont(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q }; -LABEL0: -cont(16) JIP: LABEL1 UIP: LABEL1 { align1 1H }; -LABEL1: diff --git a/src/intel/compiler/elk/tests/gen9/cont.expected b/src/intel/compiler/elk/tests/gen9/cont.expected deleted file mode 100644 index d8036df8e1c..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cont.expected +++ /dev/null @@ -1,2 +0,0 @@ -29 00 60 00 00 0e 00 34 20 00 00 00 10 00 00 00 -29 00 80 00 00 0e 00 34 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/cr0.asm b/src/intel/compiler/elk/tests/gen9/cr0.asm deleted file mode 100644 index d5b67ca9cf1..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cr0.asm +++ /dev/null @@ -1,14 +0,0 @@ -and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch }; -and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000040UD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000440UD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000080UD { align1 1N switch }; -or(1) cr0<1>UD cr0<0,1,0>UD 0x00000480UD { align1 1N switch }; diff --git a/src/intel/compiler/elk/tests/gen9/cr0.expected b/src/intel/compiler/elk/tests/gen9/cr0.expected deleted file mode 100644 index ccf8a886035..00000000000 --- a/src/intel/compiler/elk/tests/gen9/cr0.expected +++ /dev/null @@ -1,14 +0,0 @@ -05 80 00 00 00 00 00 30 00 10 00 06 3f fb ff ff -05 80 00 00 00 00 00 30 00 10 00 06 3f ff ff ff -05 80 00 00 00 00 00 30 00 10 00 06 7f fb ff ff -05 80 00 00 00 00 00 30 00 10 00 06 7f ff ff ff -05 80 00 00 00 00 00 30 00 10 00 06 bf fb ff ff -05 80 00 00 00 00 00 30 00 10 00 06 bf ff ff ff -05 80 00 00 00 00 00 30 00 10 00 06 cf ff ff ff -05 80 00 00 00 00 00 30 00 10 00 06 ff fb ff ff -06 80 00 00 00 00 00 30 00 10 00 06 00 04 00 00 -06 80 00 00 00 00 00 30 00 10 00 06 30 00 00 00 -06 80 00 00 00 00 00 30 00 10 00 06 40 00 00 00 -06 80 00 00 00 00 00 30 00 10 00 06 40 04 00 00 -06 80 00 00 00 00 00 30 00 10 00 06 80 00 00 00 -06 80 00 00 00 00 00 30 00 10 00 06 80 04 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/csel.asm b/src/intel/compiler/elk/tests/gen9/csel.asm deleted file mode 100644 index 6030fb39f26..00000000000 --- a/src/intel/compiler/elk/tests/gen9/csel.asm +++ /dev/null @@ -1,13 +0,0 @@ -csel.nz(8) g15<1>F g11<4,4,1>F (abs)g11<4,4,1>F g11<4,4,1>F { align16 1Q }; -csel.nz(16) g14<1>F g8<4,4,1>F (abs)g8<4,4,1>F g8<4,4,1>F { align16 1H }; -csel.le(8) g21<1>F (abs)g5.3<0,1,0>F g5.0<0,1,0>F g5.3<0,1,0>F { align16 1Q }; -csel.l(8) g107<1>F -g101<4,4,1>F g101<4,4,1>F g104<4,4,1>F { align16 1Q }; -csel.le(8) g21<1>F g5.0<0,1,0>F (abs)g5.1<0,1,0>F g5.1<0,1,0>F { align16 1Q }; -csel.l(8) g127<1>F g2<4,4,1>F g8<4,4,1>F g4.0<0,1,0>F { align16 1Q }; -csel.l(16) g126<1>F g2<4,4,1>F g13<4,4,1>F g6.0<0,1,0>F { align16 1H }; -csel.le(16) g13<1>F (abs)g73<4,4,1>F g58<4,4,1>F g73<4,4,1>F { align16 1H }; -csel.le(16) g15<1>F g58<4,4,1>F (abs)g73<4,4,1>F g73<4,4,1>F { align16 1H }; -csel.l(16) g69<1>F -g65<4,4,1>F g65<4,4,1>F g67<4,4,1>F { align16 1H }; -csel.sat.g(8) g125<1>F g2.3<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1Q }; -csel.g(8) g125<1>F g2.3<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1Q }; -csel.g(16) g122<1>F g2.3<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/csel.expected b/src/intel/compiler/elk/tests/gen9/csel.expected deleted file mode 100644 index 300b9154107..00000000000 --- a/src/intel/compiler/elk/tests/gen9/csel.expected +++ /dev/null @@ -1,13 +0,0 @@ -12 01 60 02 80 00 1e 0f c8 b1 00 39 16 20 c7 02 -12 01 80 02 80 00 1e 0e c8 81 00 39 10 20 07 02 -12 01 60 06 20 00 1e 15 01 56 20 00 0a 04 58 01 -12 01 60 05 40 00 1e 6b c8 51 06 39 ca 20 07 1a -12 01 60 06 80 00 1e 15 01 50 20 40 0a 04 48 01 -12 01 60 05 00 00 1e 7f c8 21 00 39 10 04 00 01 -12 01 80 05 00 00 1e 7e c8 21 00 39 1a 04 80 01 -12 01 80 06 20 00 1e 0d c8 91 04 39 74 20 47 12 -12 01 80 06 80 00 1e 0f c8 a1 03 39 92 20 47 12 -12 01 80 05 40 00 1e 45 c8 11 04 39 82 20 c7 10 -12 01 60 83 00 00 1e 7d 01 26 20 80 04 04 80 00 -12 01 60 03 00 00 1e 7d 01 26 20 80 04 04 80 00 -12 01 80 03 00 00 1e 7a 01 26 20 80 04 04 80 00 diff --git a/src/intel/compiler/elk/tests/gen9/else.asm b/src/intel/compiler/elk/tests/gen9/else.asm deleted file mode 100644 index ce868a280cd..00000000000 --- a/src/intel/compiler/elk/tests/gen9/else.asm +++ /dev/null @@ -1,4 +0,0 @@ -else(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; -else(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; -else(32) JIP: LABEL0 UIP: LABEL0 { align1 }; -LABEL0: \ No newline at end of file diff --git a/src/intel/compiler/elk/tests/gen9/else.expected b/src/intel/compiler/elk/tests/gen9/else.expected deleted file mode 100644 index c7834d75bcd..00000000000 --- a/src/intel/compiler/elk/tests/gen9/else.expected +++ /dev/null @@ -1,3 +0,0 @@ -24 00 60 00 20 0e 00 20 30 00 00 00 30 00 00 00 -24 00 80 00 20 0e 00 20 20 00 00 00 20 00 00 00 -24 00 a0 00 20 0e 00 20 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/endif.asm b/src/intel/compiler/elk/tests/gen9/endif.asm deleted file mode 100644 index 206798e2de6..00000000000 --- a/src/intel/compiler/elk/tests/gen9/endif.asm +++ /dev/null @@ -1,4 +0,0 @@ -endif(8) JIP: LABEL0 { align1 1Q }; -endif(16) JIP: LABEL0 { align1 1H }; -endif(32) JIP: LABEL0 { align1 }; -LABEL0: diff --git a/src/intel/compiler/elk/tests/gen9/endif.expected b/src/intel/compiler/elk/tests/gen9/endif.expected deleted file mode 100644 index 5f6a9feba40..00000000000 --- a/src/intel/compiler/elk/tests/gen9/endif.expected +++ /dev/null @@ -1,3 +0,0 @@ -25 00 60 00 00 0e 00 00 00 00 00 08 30 00 00 00 -25 00 80 00 00 0e 00 00 00 00 00 08 20 00 00 00 -25 00 a0 00 00 0e 00 00 00 00 00 08 10 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/fbh.asm b/src/intel/compiler/elk/tests/gen9/fbh.asm deleted file mode 100644 index fb62e766685..00000000000 --- a/src/intel/compiler/elk/tests/gen9/fbh.asm +++ /dev/null @@ -1,2 +0,0 @@ -fbh(8) g15<1>D g35<8,8,1>D { align1 1Q }; -fbh(16) g8<1>D g4<8,8,1>D { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/fbh.expected b/src/intel/compiler/elk/tests/gen9/fbh.expected deleted file mode 100644 index a3a1fcee746..00000000000 --- a/src/intel/compiler/elk/tests/gen9/fbh.expected +++ /dev/null @@ -1,2 +0,0 @@ -4b 00 60 00 28 0a e0 21 60 04 8d 00 00 00 00 00 -4b 00 80 00 28 0a 00 21 80 00 8d 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/fbl.asm b/src/intel/compiler/elk/tests/gen9/fbl.asm deleted file mode 100644 index e7f1c7020f5..00000000000 --- a/src/intel/compiler/elk/tests/gen9/fbl.asm +++ /dev/null @@ -1,3 +0,0 @@ -fbl(8) g5<1>UD g5<8,8,1>UD { align1 1Q }; -fbl(16) g6<1>UD g8<8,8,1>UD { align1 1H }; -fbl(1) g43<1>UD mask0<0,1,0>UD { align1 WE_all 1N }; diff --git a/src/intel/compiler/elk/tests/gen9/fbl.expected b/src/intel/compiler/elk/tests/gen9/fbl.expected deleted file mode 100644 index 60cb680a350..00000000000 --- a/src/intel/compiler/elk/tests/gen9/fbl.expected +++ /dev/null @@ -1,3 +0,0 @@ -4c 00 60 00 08 02 a0 20 a0 00 8d 00 00 00 00 00 -4c 00 80 00 08 02 c0 20 00 01 8d 00 00 00 00 00 -4c 00 00 00 0c 00 60 25 00 08 00 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/frc.asm b/src/intel/compiler/elk/tests/gen9/frc.asm deleted file mode 100644 index 910fbed5b59..00000000000 --- a/src/intel/compiler/elk/tests/gen9/frc.asm +++ /dev/null @@ -1,2 +0,0 @@ -frc(8) g28<1>F g4<8,8,1>F { align1 1Q }; -frc(16) g3<1>F g1<0,1,0>F { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/frc.expected b/src/intel/compiler/elk/tests/gen9/frc.expected deleted file mode 100644 index 00484ffedd3..00000000000 --- a/src/intel/compiler/elk/tests/gen9/frc.expected +++ /dev/null @@ -1,2 +0,0 @@ -43 00 60 00 e8 3a 80 23 80 00 8d 00 00 00 00 00 -43 00 80 00 e8 3a 60 20 20 00 00 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/halt.asm b/src/intel/compiler/elk/tests/gen9/halt.asm deleted file mode 100644 index 726d1917f88..00000000000 --- a/src/intel/compiler/elk/tests/gen9/halt.asm +++ /dev/null @@ -1,6 +0,0 @@ -(-f0.1.any4h) halt(8) JIP: LABEL0 UIP: LABEL0 { align1 1Q }; -halt(8) JIP: LABEL1 UIP: LABEL1 { align1 1Q }; -LABEL1: -(-f0.1.any4h) halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; -halt(16) JIP: LABEL0 UIP: LABEL0 { align1 1H }; -LABEL0: \ No newline at end of file diff --git a/src/intel/compiler/elk/tests/gen9/halt.expected b/src/intel/compiler/elk/tests/gen9/halt.expected deleted file mode 100644 index b0867fe7f81..00000000000 --- a/src/intel/compiler/elk/tests/gen9/halt.expected +++ /dev/null @@ -1,4 +0,0 @@ -2a 00 76 00 21 0e 00 20 40 00 00 00 40 00 00 00 -2a 00 60 00 20 0e 00 20 10 00 00 00 10 00 00 00 -2a 00 96 00 21 0e 00 20 20 00 00 00 20 00 00 00 -2a 00 80 00 20 0e 00 20 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/if.asm b/src/intel/compiler/elk/tests/gen9/if.asm deleted file mode 100644 index e5192c41248..00000000000 --- a/src/intel/compiler/elk/tests/gen9/if.asm +++ /dev/null @@ -1,7 +0,0 @@ -(+f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q }; -(-f0.0) if(8) JIP: LABEL0 UIP: LABEL1 { align1 1Q }; -LABEL0: -(-f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H }; -(+f0.0) if(16) JIP: LABEL1 UIP: LABEL1 { align1 1H }; -(+f0.0) if(32) JIP: LABEL1 UIP: LABEL1 { align1 }; -LABEL1: diff --git a/src/intel/compiler/elk/tests/gen9/if.expected b/src/intel/compiler/elk/tests/gen9/if.expected deleted file mode 100644 index d11bebc1730..00000000000 --- a/src/intel/compiler/elk/tests/gen9/if.expected +++ /dev/null @@ -1,5 +0,0 @@ -22 00 61 00 20 0e 00 20 50 00 00 00 20 00 00 00 -22 00 71 00 20 0e 00 20 40 00 00 00 10 00 00 00 -22 00 91 00 20 0e 00 20 30 00 00 00 30 00 00 00 -22 00 81 00 20 0e 00 20 20 00 00 00 20 00 00 00 -22 00 a1 00 20 0e 00 20 10 00 00 00 10 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/lrp.asm b/src/intel/compiler/elk/tests/gen9/lrp.asm deleted file mode 100644 index d2445c6919b..00000000000 --- a/src/intel/compiler/elk/tests/gen9/lrp.asm +++ /dev/null @@ -1,5 +0,0 @@ -lrp(8) g4<1>F g16<4,4,1>F g7.2<0,1,0>F g6.6<0,1,0>F { align16 1Q }; -lrp(16) g4<1>F g2.4<0,1,0>F g2.2<0,1,0>F g2.0<0,1,0>F { align16 1H }; -lrp.z.f0.0(8) g8<1>F g3.2<0,1,0>F g3.1<0,1,0>F g3.0<0,1,0>F { align16 1Q }; -lrp.sat(8) g7<1>F g10<4,4,1>F g13<4,4,1>F g16<4,4,1>F { align16 1Q }; -lrp.sat(16) g18<1>F g20<4,4,1>F g26<4,4,1>F g32<4,4,1>F { align16 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/lrp.expected b/src/intel/compiler/elk/tests/gen9/lrp.expected deleted file mode 100644 index b109e92a5be..00000000000 --- a/src/intel/compiler/elk/tests/gen9/lrp.expected +++ /dev/null @@ -1,5 +0,0 @@ -5c 01 60 00 00 00 1e 04 c8 01 21 80 0e 04 b0 01 -5c 01 80 00 00 00 1e 04 01 28 20 80 04 04 80 00 -5c 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00 -5c 01 60 80 00 00 1e 07 c8 a1 00 39 1a 20 07 04 -5c 01 80 80 00 00 1e 12 c8 41 01 39 34 20 07 08 diff --git a/src/intel/compiler/elk/tests/gen9/lzd.asm b/src/intel/compiler/elk/tests/gen9/lzd.asm deleted file mode 100644 index 2dba1a11453..00000000000 --- a/src/intel/compiler/elk/tests/gen9/lzd.asm +++ /dev/null @@ -1,2 +0,0 @@ -lzd(8) g25<1>UD g3.1<0,1,0>UD { align1 1Q }; -lzd(16) g27<1>UD g3.1<0,1,0>UD { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/lzd.expected b/src/intel/compiler/elk/tests/gen9/lzd.expected deleted file mode 100644 index 74afe29080d..00000000000 --- a/src/intel/compiler/elk/tests/gen9/lzd.expected +++ /dev/null @@ -1,2 +0,0 @@ -4a 00 60 00 08 02 20 23 64 00 00 00 00 00 00 00 -4a 00 80 00 08 02 60 23 64 00 00 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/mach.asm b/src/intel/compiler/elk/tests/gen9/mach.asm deleted file mode 100644 index 7f632bf16bf..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mach.asm +++ /dev/null @@ -1,4 +0,0 @@ -mach(8) g19<1>UD g17<8,8,1>UD 0xaaaaaaabUD { align1 1Q AccWrEnable }; -mach(8) g23<1>D g17<8,8,1>D 1431655766D { align1 1Q AccWrEnable }; -mach(8) g42<1>UD g39<8,8,1>UD 0xaaaaaaabUD { align1 2Q AccWrEnable }; -mach(8) g50<1>D g39<8,8,1>D 1431655766D { align1 2Q AccWrEnable }; diff --git a/src/intel/compiler/elk/tests/gen9/mach.expected b/src/intel/compiler/elk/tests/gen9/mach.expected deleted file mode 100644 index d90d46e56ef..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mach.expected +++ /dev/null @@ -1,4 +0,0 @@ -49 00 60 10 08 02 60 22 20 02 8d 06 ab aa aa aa -49 00 60 10 28 0a e0 22 20 02 8d 0e 56 55 55 55 -49 10 60 10 08 02 40 25 e0 04 8d 06 ab aa aa aa -49 10 60 10 28 0a 40 26 e0 04 8d 0e 56 55 55 55 diff --git a/src/intel/compiler/elk/tests/gen9/mad.asm b/src/intel/compiler/elk/tests/gen9/mad.asm deleted file mode 100644 index a48131f21a1..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mad.asm +++ /dev/null @@ -1,43 +0,0 @@ -mad(8) g26<1>F g22<4,4,1>F g2.4<0,1,0>F g5<4,4,1>F { align16 1Q }; -mad(16) g14<1>F g12<4,4,1>F g4<4,4,1>F g4<4,4,1>F { align16 1H }; -mad(8) g64<1>DF g62<4,4,1>DF g40<4,4,1>DF g92<4,4,1>DF { align16 1Q }; -mad(8) g80<1>DF -g50<4,4,1>DF g24<4,4,1>DF g80<4,4,1>DF { align16 1Q }; -mad(8) g27<1>DF g48<4,4,1>DF g106<4,4,1>DF g25<4,4,1>DF { align16 2Q }; -mad(8) g13<1>F -g14.0<0,1,0>F g11<4,4,1>F g6<4,4,1>F { align16 1Q }; -mad(16) g29<1>F -g33.0<0,1,0>F g25<4,4,1>F g15<4,4,1>F { align16 1H }; -mad(8) g29<1>DF g23<4,4,1>DF g27<4,4,1>DF -g25<4,4,1>DF { align16 1Q }; -mad.le.f0.0(8) g5<1>F g3<4,4,1>F g4.2<0,1,0>F g64<4,4,1>F { align16 1Q }; -mad.le.f0.0(16) g7<1>F g4<4,4,1>F g6.2<0,1,0>F g16<4,4,1>F { align16 1H }; -mad(8) g32<1>F g31<4,4,1>F g2.3<0,1,0>F -g15<4,4,1>F { align16 1Q }; -mad(16) g56<1>F g54<4,4,1>F g2.3<0,1,0>F -g5<4,4,1>F { align16 1H }; -mad.sat(8) g12<1>F g4.1<0,1,0>F g4.0<0,1,0>F g8<4,4,1>F { align16 1Q }; -mad.sat(16) g18<1>F g6.1<0,1,0>F g6.0<0,1,0>F g10<4,4,1>F { align16 1H }; -mad(8) g86<1>F g88.6<0,1,0>F -g88.7<0,1,0>F g77<4,4,1>F { align16 1Q }; -mad(8) g85<1>DF g28<4,4,1>DF g83<4,4,1>DF -g81<4,4,1>DF { align16 2Q }; -mad(8) g11<1>F -g2.0<0,1,0>F g10<4,4,1>F (abs)g5.6<0,1,0>F { align16 1Q }; -mad(8) g15<1>F g2.1<0,1,0>F g11<4,4,1>F (abs)g5.6<0,1,0>F { align16 1Q }; -mad.l.f0.0(8) g2<1>F g22<4,4,1>F g5.7<0,1,0>F g6.3<0,1,0>F { align16 1Q }; -mad(8) g79<1>DF -g39<4,4,1>DF g21<4,4,1>DF g79<4,4,1>DF { align16 2Q }; -mad(8) g117<1>F -g116<4,4,1>F g9.0<0,1,0>F -g113<4,4,1>F { align16 1Q }; -mad.ge.f0.0(8) g13<1>F g28.0<0,1,0>F g9<4,4,1>F -g2.4<0,1,0>F { align16 1Q }; -mad.ge.f0.0(16) g23<1>F g17.0<0,1,0>F g6<4,4,1>F -g3.0<0,1,0>F { align16 1H }; -mad(8) g26<1>F g2.0<0,1,0>F -g2.1<0,1,0>F (abs)g5.6<0,1,0>F { align16 1Q }; -mad(8) g70<1>F -g13<4,4,1>F -g2.1<0,1,0>F -g47<4,4,1>F { align16 1Q }; -mad(16) g95<1>F -g93<4,4,1>F g85<4,4,1>F -g85<4,4,1>F { align16 1H }; -mad(16) g5<1>F -g21<4,4,1>F -g2.1<0,1,0>F -g85<4,4,1>F { align16 1H }; -mad(16) g56<1>F g6.4<0,1,0>F -g6.5<0,1,0>F g51<4,4,1>F { align16 1H }; -mad.sat(8) g124<1>F -g7<4,4,1>F g2.6<0,1,0>F g2.1<0,1,0>F { align16 1Q }; -mad(16) g71<1>F g55.0<0,1,0>F -g55.1<0,1,0>F (abs)g1.0<0,1,0>F { align16 1H }; -mad(16) g77<1>F -g55.2<0,1,0>F g71<4,4,1>F (abs)g1.0<0,1,0>F { align16 1H }; -mad(16) g37<1>F g55.3<0,1,0>F g77<4,4,1>F (abs)g1.0<0,1,0>F { align16 1H }; -mad(8) g43<1>DF g42<4,4,1>DF -g34<4,4,1>DF g7<4,4,1>DF { align16 1Q }; -mad(8) g3<1>DF g2<4,4,1>DF -g111<4,4,1>DF g39<4,4,1>DF { align16 2Q }; -mad(8) g12<1>F -g17<4,4,1>F (abs)g7<4,4,1>F g4.0<0,1,0>F { align16 1Q }; -mad(16) g27<1>F -g22<4,4,1>F (abs)g19<4,4,1>F g29.0<0,1,0>F { align16 1H }; -mad.sat(8) g125<1>F g9<4,4,1>F g6<4,4,1>F -g64.0<0,1,0>F { align16 1Q }; -mad.l.f0.0(16) g5<1>F g9<4,4,1>F g2.7<0,1,0>F g3.3<0,1,0>F { align16 1H }; -mad(8) g6<1>DF -g55<4,4,1>DF g2<4,4,1>DF -g47<4,4,1>DF { align16 1Q }; -mad.z.f0.0(8) g8<1>F g3.2<0,1,0>F g3.1<0,1,0>F g3.0<0,1,0>F { align16 1Q }; -mad(8) g63<1>DF -g48<4,4,1>DF g56<4,4,1>DF -g44<4,4,1>DF { align16 2Q }; -mad.nz.f0.0(8) g10<1>F -g12.0<0,1,0>F g7<4,4,1>F g10<4,4,1>F { align16 1Q }; -mad.nz.f0.0(16) g15<1>F -g33.0<0,1,0>F g9<4,4,1>F g17<4,4,1>F { align16 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/mad.expected b/src/intel/compiler/elk/tests/gen9/mad.expected deleted file mode 100644 index 76df668b448..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mad.expected +++ /dev/null @@ -1,43 +0,0 @@ -5b 01 60 00 00 00 1e 1a c8 61 21 00 05 20 47 01 -5b 01 80 00 00 00 1e 0e c8 c1 00 39 08 20 07 01 -5b 01 60 00 00 d8 1e 40 c8 e1 03 39 50 20 07 17 -5b 01 60 00 40 d8 1e 50 c8 21 03 39 30 20 07 14 -5b 11 60 00 00 d8 1e 1b c8 01 03 39 d4 20 47 06 -5b 01 60 00 40 00 1e 0d 01 e0 00 39 16 20 87 01 -5b 01 80 00 40 00 1e 1d 01 10 02 39 32 20 c7 03 -5b 01 60 00 00 dc 1e 1d c8 71 01 39 36 20 47 06 -5b 01 60 06 00 00 1e 05 c8 31 20 80 08 20 07 10 -5b 01 80 06 00 00 1e 07 c8 41 20 80 0c 20 07 04 -5b 01 60 00 00 04 1e 20 c8 f1 21 c0 04 20 c7 03 -5b 01 80 00 00 04 1e 38 c8 61 23 c0 04 20 47 01 -5b 01 60 80 00 00 1e 0c 01 42 20 00 08 20 07 02 -5b 01 80 80 00 00 1e 12 01 62 20 00 0c 20 87 02 -5b 01 60 00 00 01 1e 56 01 8c 25 c0 b1 20 47 13 -5b 11 60 00 00 dc 1e 55 c8 c1 01 39 a6 20 47 14 -5b 01 60 00 40 02 1e 0b 01 20 00 39 14 04 70 01 -5b 01 60 00 00 02 1e 0f 01 22 00 39 16 04 70 01 -5b 01 60 05 00 00 1e 02 c8 61 21 c0 0b 04 98 01 -5b 11 60 00 40 d8 1e 4f c8 71 02 39 2a 20 c7 13 -5b 01 60 00 40 04 1e 75 c8 41 27 00 12 20 47 1c -5b 01 60 04 00 04 1e 0d 01 c0 01 39 12 04 a0 00 -5b 01 80 04 00 04 1e 17 01 10 01 39 0c 04 c0 00 -5b 01 60 00 00 03 1e 1a 01 20 20 40 04 04 70 01 -5b 01 60 00 40 05 1e 46 c8 d1 20 40 04 20 c7 0b -5b 01 80 00 40 04 1e 5f c8 d1 05 39 aa 20 47 15 -5b 01 80 00 40 05 1e 05 c8 51 21 40 04 20 47 15 -5b 01 80 00 00 01 1e 38 01 68 20 40 0d 20 c7 0c -5b 01 60 80 40 00 1e 7c c8 71 20 80 05 04 88 00 -5b 01 80 00 00 03 1e 47 01 70 23 40 6e 04 40 00 -5b 01 80 00 40 02 1e 4d 01 74 03 39 8e 04 40 00 -5b 01 80 00 00 02 1e 25 01 76 03 39 9a 04 40 00 -5b 01 60 00 00 d9 1e 2b c8 a1 02 39 44 20 c7 01 -5b 11 60 00 00 d9 1e 03 c8 21 00 39 de 20 c7 09 -5b 01 60 00 c0 00 1e 0c c8 11 01 39 0e 04 00 01 -5b 01 80 00 c0 00 1e 1b c8 61 01 39 26 04 40 07 -5b 01 60 80 00 04 1e 7d c8 91 00 39 0c 04 00 10 -5b 01 80 05 00 00 1e 05 c8 91 20 c0 05 04 d8 00 -5b 01 60 00 40 dc 1e 06 c8 71 03 39 04 20 c7 0b -5b 01 60 01 00 00 1e 08 01 34 20 40 06 04 c0 00 -5b 11 60 00 40 dc 1e 3f c8 01 03 39 70 20 07 0b -5b 01 60 02 40 00 1e 0a 01 c0 00 39 0e 20 87 02 -5b 01 80 02 40 00 1e 0f 01 10 02 39 12 20 47 04 diff --git a/src/intel/compiler/elk/tests/gen9/math.asm b/src/intel/compiler/elk/tests/gen9/math.asm deleted file mode 100644 index d6a54d2c389..00000000000 --- a/src/intel/compiler/elk/tests/gen9/math.asm +++ /dev/null @@ -1,31 +0,0 @@ -math sqrt(16) g20<1>F g18<8,8,1>F null<8,8,1>F { align1 1H }; -math inv(8) g95<1>F g94<8,8,1>F null<8,8,1>F { align1 1Q }; -math inv(16) g10<1>F g8<8,8,1>F null<8,8,1>F { align1 1H }; -math intmod(8) g3<1>UD g1<0,1,0>UD g1.2<0,1,0>UD { align1 1Q }; -math intmod(8) g4<1>UD g1<0,1,0>UD g1.2<0,1,0>UD { align1 2Q }; -math sqrt(8) g24<1>F g23<8,8,1>F null<8,8,1>F { align1 1Q }; -math rsq(8) g5<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q }; -math pow(8) g11<1>F g10<8,8,1>F 0x42fc6666F /* 126.2F */ { align1 1Q }; -math pow(16) g18<1>F g16<8,8,1>F 0x42fc6666F /* 126.2F */ { align1 1H }; -math log(8) g7<1>F g6<8,8,1>F null<8,8,1>F { align1 1Q }; -math log(16) g11<1>F g9<8,8,1>F null<8,8,1>F { align1 1H }; -math cos(8) g3<1>F g2<8,8,1>F null<8,8,1>F { align1 1Q }; -math cos(16) g4<1>F g2<8,8,1>F null<8,8,1>F { align1 1H }; -math intdiv(8) g4<1>UD g1<0,1,0>UD g1.4<0,1,0>UD { align1 1Q }; -math intdiv(8) g5<1>UD g1<0,1,0>UD g1.4<0,1,0>UD { align1 2Q }; -math intdiv(8) g24<1>D g4<0,1,0>D g2.2<0,1,0>D { align1 1Q }; -math sin(8) g10<1>F g9<8,8,1>F null<8,8,1>F { align1 1Q }; -math rsq(16) g68<1>F g66<8,8,1>F null<8,8,1>F { align1 1H }; -math exp(8) g124<1>F g10<8,8,1>F null<8,8,1>F { align1 1Q }; -math exp(16) g120<1>F g7<8,8,1>F null<8,8,1>F { align1 1H }; -math intdiv(8) g5<1>D g2<0,1,0>D g2.4<0,1,0>D { align1 2Q }; -math sin(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; -math.sat pow(8) g3<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1Q }; -math.sat pow(16) g3<1>F g2<0,1,0>F g2.4<0,1,0>F { align1 1H }; -math.sat sqrt(8) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; -math.sat sqrt(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; -math.sat exp(8) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; -math.sat exp(16) g3<1>F g2<0,1,0>F null<8,8,1>F { align1 1H }; -math.sat rsq(8) g127<1>F (abs)g7<8,8,1>F null<8,8,1>F { align1 1Q }; -math.sat inv(8) g124<1>F g2<0,1,0>F null<8,8,1>F { align1 1Q }; -math.sat log(8) g127<1>F g7<8,8,1>F null<8,8,1>F { align1 1Q }; diff --git a/src/intel/compiler/elk/tests/gen9/math.expected b/src/intel/compiler/elk/tests/gen9/math.expected deleted file mode 100644 index 9837a7cee3f..00000000000 --- a/src/intel/compiler/elk/tests/gen9/math.expected +++ /dev/null @@ -1,31 +0,0 @@ -38 00 80 04 e8 3a 80 22 40 02 8d 38 00 00 8d 00 -38 00 60 01 e8 3a e0 2b c0 0b 8d 38 00 00 8d 00 -38 00 80 01 e8 3a 40 21 00 01 8d 38 00 00 8d 00 -38 00 60 0d 08 02 60 20 20 00 00 02 28 00 00 00 -38 10 60 0d 08 02 80 20 20 00 00 02 28 00 00 00 -38 00 60 04 e8 3a 00 23 e0 02 8d 38 00 00 8d 00 -38 00 60 05 e8 3a a0 20 40 00 8d 38 00 00 8d 00 -38 00 60 0a e8 3a 60 21 40 01 8d 3e 66 66 fc 42 -38 00 80 0a e8 3a 40 22 00 02 8d 3e 66 66 fc 42 -38 00 60 02 e8 3a e0 20 c0 00 8d 38 00 00 8d 00 -38 00 80 02 e8 3a 60 21 20 01 8d 38 00 00 8d 00 -38 00 60 07 e8 3a 60 20 40 00 8d 38 00 00 8d 00 -38 00 80 07 e8 3a 80 20 40 00 8d 38 00 00 8d 00 -38 00 60 0c 08 02 80 20 20 00 00 02 30 00 00 00 -38 10 60 0c 08 02 a0 20 20 00 00 02 30 00 00 00 -38 00 60 0c 28 0a 00 23 80 00 00 0a 48 00 00 00 -38 00 60 06 e8 3a 40 21 20 01 8d 38 00 00 8d 00 -38 00 80 05 e8 3a 80 28 40 08 8d 38 00 00 8d 00 -38 00 60 03 e8 3a 80 2f 40 01 8d 38 00 00 8d 00 -38 00 80 03 e8 3a 00 2f e0 00 8d 38 00 00 8d 00 -38 10 60 0c 28 0a a0 20 40 00 00 0a 50 00 00 00 -38 00 80 06 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 60 8a e8 3a 60 20 40 00 00 3a 50 00 00 00 -38 00 80 8a e8 3a 60 20 40 00 00 3a 50 00 00 00 -38 00 60 84 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 80 84 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 60 83 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 80 83 e8 3a 60 20 40 00 00 38 00 00 8d 00 -38 00 60 85 e8 3a e0 2f e0 20 8d 38 00 00 8d 00 -38 00 60 81 e8 3a 80 2f 40 00 00 38 00 00 8d 00 -38 00 60 82 e8 3a e0 2f e0 00 8d 38 00 00 8d 00 diff --git a/src/intel/compiler/elk/tests/gen9/mov.asm b/src/intel/compiler/elk/tests/gen9/mov.asm deleted file mode 100644 index 833631bb9e2..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mov.asm +++ /dev/null @@ -1,139 +0,0 @@ -mov(8) g123<1>UD g1<8,8,1>UD { align1 WE_all 1Q }; -mov(8) g124<1>F 0x40c00000F /* 6F */ { align1 1Q }; -mov(8) g14<1>UD 0x00000000UD { align1 1Q }; -mov(8) g17<1>F g12<8,8,1>F { align1 1Q }; -mov.sat(8) g124<1>F g8<8,8,1>F { align1 1Q }; -mov(8) g61<2>D g22<8,8,1>D { align1 1Q }; -mov(8) g21<1>D g59<8,4,2>UD { align1 1Q }; -mov(8) g4<1>D -1D { align1 1Q }; -mov.nz.f0.0(8) null<1>D g4<8,8,1>D { align1 1Q }; -mov(1) g2.2<1>UD 0x00000000UD { align1 WE_all 1N }; -mov(4) g114<1>F g2.3<8,2,4>F { align1 WE_all 1N }; -mov(8) g126<1>F g4<8,8,1>D { align1 1Q }; -mov(16) g124<1>F g4<8,8,1>D { align1 1H }; -mov(16) g120<1>F g124<8,8,1>F { align1 1H }; -mov(16) g124<1>F 0x0F /* 0F */ { align1 1H }; -mov(16) g124<1>D 1065353216D { align1 1H }; -mov.nz.f0.0(16) null<1>D g2<0,1,0>D { align1 1H }; -mov(8) g3<1>UW 0x76543210V { align1 WE_all 1Q }; -mov(16) g20<1>UD g0.1<0,1,0>UD { align1 1H }; -mov(16) g6<1>D g3<8,8,1>UW { align1 1H }; -mov(8) g1<1>D g4<8,8,1>D { align1 2Q }; -mov(8) g5<1>D 0D { align1 2Q }; -mov(8) g2<1>F g6<8,4,1>UW { align1 1Q }; -mov(8) g7<1>D g2<8,8,1>F { align1 1Q }; -mov(16) g2<1>F g10<8,4,1>UW { align1 1H }; -mov(16) g11<1>D g2<8,8,1>F { align1 1H }; -mov(8) g80<1>DF g5<0,1,0>DF { align1 1Q }; -mov(8) g92<2>UD g6.4<0,1,0>UD { align1 1Q }; -mov(8) g62<1>Q 0xbff0000000000000Q { align1 1Q }; -mov(8) g92<2>F g92<4,4,1>DF { align1 1Q }; -mov(8) g92<1>DF g95<4,4,1>F { align1 1Q }; -mov(8) g106<1>DF g2<0,1,0>F { align1 2Q }; -mov(8) g48<1>Q 0xbff0000000000000Q { align1 2Q }; -mov(8) g127<1>UD g106.1<8,4,2>UD { align1 2Q }; -mov(8) g11<2>F g7<4,4,1>DF { align1 2Q }; -mov(8) g33<1>D g34<8,4,2>UD { align1 2Q }; -mov(8) g6<2>UD 0x00000000UD { align1 2Q }; -mov(8) g2<1>UW 0x76543210UV { align1 1Q }; -mov(8) g12<1>UD g2<8,8,1>UW { align1 1Q }; -mov(8) g7<1>UD 0x00080000UD { align1 WE_all 1Q }; -mov(1) g2<1>F 0x3e800000F /* 0.25F */ { align1 WE_all 1N }; -mov(8) g15<1>F g11<8,8,1>UD { align1 1Q }; -mov(1) f0.1<1>UW g1.14<0,1,0>UW { align1 WE_all 1N }; -mov(8) g18<1>UD g2<8,8,1>D { align1 1Q }; -mov(16) g18<1>UD g26<8,8,1>D { align1 1H }; -mov(16) g120<1>D g34<8,8,1>D { align1 1H }; -mov(8) g8<1>Q g13<4,4,1>Q { align1 1Q }; -mov(8) g21<1>UD g0<8,8,1>UD { align1 WE_all 2Q }; -mov(8) g23<1>F g6<0,1,0>F { align1 2Q }; -mov(1) g21.2<1>UD 0x000003f2UD { align1 WE_all 3N }; -mov.nz.f0.0(8) g19<1>D g3<8,4,2>UD { align1 1Q }; -mov(1) f1<1>UD g1.7<0,1,0>UD { align1 WE_all 1N }; -mov.sat(8) g126<1>F 0x0F /* 0F */ { align1 1Q }; -mov.sat(8) g124<1>F -g36<8,8,1>D { align1 1Q }; -mov(8) g41<1>F 0x0F /* 0F */ { align1 2Q }; -mov(8) g42<1>UD g11<8,8,1>D { align1 2Q }; -mov(16) g86<1>UD g88<8,8,1>UD { align1 WE_all 1H }; -mov.sat(16) g120<1>F g2<0,1,0>F { align1 1H }; -mov(16) g2<1>F g18<8,8,1>UD { align1 1H }; -mov(8) g4<1>UD 0x0F /* 0F */ { align1 1Q }; -mov(8) g8<1>DF g2<0,1,0>D { align1 1Q }; -mov(16) g8<1>UD 0x00000000UD { align1 1H }; -mov.nz.f0.0(8) g4<1>F -(abs)g2<0,1,0>F { align1 1Q }; -(+f0.0) mov(8) g4<1>F 0xbf800000F /* -1F */ { align1 1Q }; -mov.nz.f0.0(16) g4<1>F -(abs)g2<0,1,0>F { align1 1H }; -(+f0.0) mov(16) g4<1>F 0xbf800000F /* -1F */ { align1 1H }; -mov(1) f1<1>UD g1.7<0,1,0>UD { align1 WE_all 3N }; -mov(8) g32<1>DF g2<0,1,0>DF { align1 2Q }; -mov(8) g5<1>F g2<0,1,0>HF { align1 1Q }; -mov(16) g6<1>F g2<0,1,0>HF { align1 1H }; -mov(8) g7<1>UD g2<0,1,0>F { align1 1Q }; -mov(16) g15<1>UD g11<8,8,1>F { align1 1H }; -mov(16) g19<1>UD g15<16,8,2>UW { align1 1H }; -mov(1) g19<1>UD g[a0 64]<0,1,0>UD { align1 WE_all 1N }; -mov(16) g23<1>UD g21<32,8,4>UB { align1 1H }; -mov(8) g7<1>DF 0x0000000000000000DF /* 0DF */ { align1 1Q }; -mov(8) g5<1>F 0x0F /* 0F */ { align1 WE_all 1Q }; -mov(16) g4<1>UD 0x00000000UD { align1 WE_all 1H }; -mov(8) g5<2>UD g2<0,1,0>DF { align1 1Q }; -mov(8) g10<2>UD g2<0,1,0>DF { align1 2Q }; -mov(8) g3<1>DF g2<0,1,0>UD { align1 1Q }; -mov(8) g3<1>DF g2<0,1,0>UD { align1 2Q }; -mov(1) f0<1>UW 0x0000UW { align1 WE_all 1N }; -mov(1) g1<1>D 0D { align1 WE_all 1N }; -(+f0.0.any16h) mov(1) g1<1>D -1D { align1 WE_all 1N }; -mov(8) g9<1>F g2<0,1,0>W { align1 1Q }; -mov(8) g7<1>UQ g4<4,4,1>UQ { align1 1Q }; -mov(16) g11<1>UD 0x0F /* 0F */ { align1 1H }; -mov(8) g5<2>D g2<0,1,0>DF { align1 1Q }; -mov(8) g10<2>D g2<0,1,0>DF { align1 2Q }; -mov(1) f1<1>UW f0.1<0,1,0>UW { align1 WE_all 1N }; -mov(1) f1<1>UW f0.1<0,1,0>UW { align1 WE_all 3N }; -mov(16) g4<1>D 0D { align1 2H }; -mov(8) g14<1>UD g13<32,8,4>UB { align1 1Q }; -mov(16) g124<1>UD g15<8,8,1>UD { align1 2H }; -mov(16) g118<1>D g122<8,8,1>UW { align1 2H }; -mov(16) g101<1>UD 0x00000001UD { align1 2H }; -mov(1) g4<2>UW 0x00000000UD { align1 WE_all 1N }; -mov(8) g4<1>UD f0<0,1,0>UW { align1 1Q }; -mov(8) g8<1>D g2<8,8,1>UW { align1 1Q }; -mov(16) g4<1>UD f0<0,1,0>UW { align1 1H }; -mov(8) g3<1>DF -g2<0,1,0>D { align1 2Q }; -mov(8) g5<1>F g2<0,1,0>B { align1 1Q }; -mov(16) g6<1>F g2<0,1,0>B { align1 1H }; -mov(8) g4<1>DF 0x0000000000000000DF /* 0DF */ { align1 2Q }; -mov.nz.f0.0(8) g16<1>D g17<8,4,2>UD { align1 2Q }; -mov(8) g34<1>UW 0x76543210V { align1 1Q }; -mov(8) g8<1>UD 48D { align1 1Q }; -mov(16) g8<1>UD 0D { align1 1H }; -mov(8) g7<2>HF g2.1<0,1,0>F { align1 1Q }; -mov(1) g5<1>D g[a0 96]<0,1,0>D { align1 WE_all 1N }; -(+f0.0.any8h) mov(1) g2<1>D -1D { align1 WE_all 1N }; -mov(8) g9<1>UD 0D { align1 WE_all 1Q }; -mov(8) g2<2>UW g9<8,8,1>F { align1 1Q }; -mov(8) g3<1>UW g2<16,8,2>UW { align1 1Q }; -mov(8) g12<1>UW g8<16,8,2>UW { align1 WE_all 1Q }; -mov.sat(16) g13<1>F 0x3f800000F /* 1F */ { align1 1H }; -mov(16) g19<2>UW g17<8,8,1>F { align1 1H }; -mov(16) g4<1>UW g13<16,8,2>UW { align1 WE_all 1H }; -mov.nz.f0.0(8) null<1>D 0x00000000UD { align1 1Q }; -mov.nz.f0.0(16) null<1>D 0x00000000UD { align1 1H }; -mov(4) g3<1>UD tm0<4,4,1>UD { align1 WE_all 1N }; -(+f0.0.all16h) mov(1) g1<1>D -1D { align1 WE_all 1N }; -mov(8) g9<1>F g2<0,1,0>UB { align1 1Q }; -mov(16) g6<1>F g2<0,1,0>UB { align1 1H }; -mov(16) g10<2>HF g4<8,8,1>F { align1 1H }; -mov.z.f0.0(8) null<1>UD g2<8,8,1>UD { align1 1Q }; -mov.sat(8) g125<1>F g9<8,8,1>UD { align1 1Q }; -mov.z.f0.0(16) g1<1>UD g0.7<0,1,0>UD { align1 1H }; -mov.z.f0.0(8) g18<1>D g17<8,8,1>F { align1 1Q }; -mov(16) g35<1>F g15<16,8,2>W { align1 1H }; -mov(8) g23<1>Q g26<4,4,1>Q { align1 2Q }; -mov(8) g2<1>D 0x00000000UD { align1 1Q }; -mov(16) g2<1>D 0x00000000UD { align1 1H }; -(+f0.0.all8h) mov(1) g7<1>D -1D { align1 WE_all 1N }; -mov(8) g127<1>UB g2<0,1,0>UB { align1 WE_all 1Q }; -mov.z.f0.0(8) null<1>D g24<8,8,1>F { align1 1Q }; -mov.z.f0.0(16) null<1>D g76<8,8,1>F { align1 1H }; -mov(16) g7<1>D g2<16,8,2>B { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/mov.expected b/src/intel/compiler/elk/tests/gen9/mov.expected deleted file mode 100644 index c1dc96d9d60..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mov.expected +++ /dev/null @@ -1,139 +0,0 @@ -01 00 60 00 0c 02 60 2f 20 00 8d 00 00 00 00 00 -01 00 60 00 e8 3e 80 2f 00 00 00 38 00 00 c0 40 -01 00 60 00 08 06 c0 21 00 00 00 00 00 00 00 00 -01 00 60 00 e8 3a 20 22 80 01 8d 00 00 00 00 00 -01 00 60 80 e8 3a 80 2f 00 01 8d 00 00 00 00 00 -01 00 60 00 28 0a a0 47 c0 02 8d 00 00 00 00 00 -01 00 60 00 28 02 a0 22 60 07 8a 00 00 00 00 00 -01 00 60 00 28 0e 80 20 00 00 00 08 ff ff ff ff -01 00 60 02 20 0a 00 20 80 00 8d 00 00 00 00 00 -01 00 00 00 0c 06 48 20 00 00 00 00 00 00 00 00 -01 00 40 00 ec 3a 40 2e 4c 00 87 00 00 00 00 00 -01 00 60 00 e8 0a c0 2f 80 00 8d 00 00 00 00 00 -01 00 80 00 e8 0a 80 2f 80 00 8d 00 00 00 00 00 -01 00 80 00 e8 3a 00 2f 80 0f 8d 00 00 00 00 00 -01 00 80 00 e8 3e 80 2f 00 00 00 38 00 00 00 00 -01 00 80 00 28 0e 80 2f 00 00 00 08 00 00 80 3f -01 00 80 02 20 0a 00 20 40 00 00 00 00 00 00 00 -01 00 60 00 4c 36 60 20 00 00 00 30 10 32 54 76 -01 00 80 00 08 02 80 22 04 00 00 00 00 00 00 00 -01 00 80 00 28 12 c0 20 60 00 8d 00 00 00 00 00 -01 10 60 00 28 0a 20 20 80 00 8d 00 00 00 00 00 -01 10 60 00 28 0e a0 20 00 00 00 08 00 00 00 00 -01 00 60 00 e8 12 40 20 c0 00 89 00 00 00 00 00 -01 00 60 00 28 3a e0 20 40 00 8d 00 00 00 00 00 -01 00 80 00 e8 12 40 20 40 01 89 00 00 00 00 00 -01 00 80 00 28 3a 60 21 40 00 8d 00 00 00 00 00 -01 00 60 00 c8 32 00 2a a0 00 00 00 00 00 00 00 -01 00 60 00 08 02 80 4b d0 00 00 00 00 00 00 00 -01 00 60 00 28 4f c0 27 00 00 00 00 00 00 f0 bf -01 00 60 00 e8 32 80 4b 80 0b 69 00 00 00 00 00 -01 00 60 00 c8 3a 80 2b e0 0b 69 00 00 00 00 00 -01 10 60 00 c8 3a 40 2d 40 00 00 00 00 00 00 00 -01 10 60 00 28 4f 00 26 00 00 00 00 00 00 f0 bf -01 10 60 00 08 02 e0 2f 44 0d 8a 00 00 00 00 00 -01 10 60 00 e8 32 60 41 e0 00 69 00 00 00 00 00 -01 10 60 00 28 02 20 24 40 04 8a 00 00 00 00 00 -01 10 60 00 08 06 c0 40 00 00 00 00 00 00 00 00 -01 00 60 00 48 26 40 20 00 00 00 20 10 32 54 76 -01 00 60 00 08 12 80 21 40 00 8d 00 00 00 00 00 -01 00 60 00 0c 06 e0 20 00 00 00 00 00 00 08 00 -01 00 00 00 ec 3e 40 20 00 00 00 38 00 00 80 3e -01 00 60 00 e8 02 e0 21 60 01 8d 00 00 00 00 00 -01 00 00 00 44 12 02 26 3c 00 00 00 00 00 00 00 -01 00 60 00 08 0a 40 22 40 00 8d 00 00 00 00 00 -01 00 80 00 08 0a 40 22 40 03 8d 00 00 00 00 00 -01 00 80 00 28 0a 00 2f 40 04 8d 00 00 00 00 00 -01 00 60 00 28 4b 00 21 a0 01 69 00 00 00 00 00 -01 10 60 00 0c 02 a0 22 00 00 8d 00 00 00 00 00 -01 10 60 00 e8 3a e0 22 c0 00 00 00 00 00 00 00 -01 10 00 00 0c 06 a8 22 00 00 00 00 f2 03 00 00 -01 00 60 02 28 02 60 22 60 00 8a 00 00 00 00 00 -01 00 00 00 04 02 20 26 3c 00 00 00 00 00 00 00 -01 00 60 80 e8 3e c0 2f 00 00 00 38 00 00 00 00 -01 00 60 80 e8 0a 80 2f 80 44 8d 00 00 00 00 00 -01 10 60 00 e8 3e 20 25 00 00 00 38 00 00 00 00 -01 10 60 00 08 0a 40 25 60 01 8d 00 00 00 00 00 -01 00 80 00 0c 02 c0 2a 00 0b 8d 00 00 00 00 00 -01 00 80 80 e8 3a 00 2f 40 00 00 00 00 00 00 00 -01 00 80 00 e8 02 40 20 40 02 8d 00 00 00 00 00 -01 00 60 00 08 3e 80 20 00 00 00 38 00 00 00 00 -01 00 60 00 c8 0a 00 21 40 00 00 00 00 00 00 00 -01 00 80 00 08 06 00 21 00 00 00 00 00 00 00 00 -01 00 60 02 e8 3a 80 20 40 60 00 00 00 00 00 00 -01 00 61 00 e8 3e 80 20 00 00 00 38 00 00 80 bf -01 00 80 02 e8 3a 80 20 40 60 00 00 00 00 00 00 -01 00 81 00 e8 3e 80 20 00 00 00 38 00 00 80 bf -01 10 00 00 04 02 20 26 3c 00 00 00 00 00 00 00 -01 10 60 00 c8 32 00 24 40 00 00 00 00 00 00 00 -01 00 60 00 e8 52 a0 20 40 00 00 00 00 00 00 00 -01 00 80 00 e8 52 c0 20 40 00 00 00 00 00 00 00 -01 00 60 00 08 3a e0 20 40 00 00 00 00 00 00 00 -01 00 80 00 08 3a e0 21 60 01 8d 00 00 00 00 00 -01 00 80 00 08 12 60 22 e0 01 ae 00 00 00 00 00 -01 00 00 00 0c 02 60 22 40 80 00 00 00 00 00 00 -01 00 80 00 08 22 e0 22 a0 02 cf 00 00 00 00 00 -01 00 60 00 c8 56 e0 20 00 00 00 00 00 00 00 00 -01 00 60 00 ec 3e a0 20 00 00 00 38 00 00 00 00 -01 00 80 00 0c 06 80 20 00 00 00 00 00 00 00 00 -01 00 60 00 08 32 a0 40 40 00 00 00 00 00 00 00 -01 10 60 00 08 32 40 41 40 00 00 00 00 00 00 00 -01 00 60 00 c8 02 60 20 40 00 00 00 00 00 00 00 -01 10 60 00 c8 02 60 20 40 00 00 00 00 00 00 00 -01 00 00 00 44 16 00 26 00 00 00 10 00 00 00 00 -01 00 00 00 2c 0e 20 20 00 00 00 08 00 00 00 00 -01 00 0a 00 2c 0e 20 20 00 00 00 08 ff ff ff ff -01 00 60 00 e8 1a 20 21 40 00 00 00 00 00 00 00 -01 00 60 00 08 43 e0 20 80 00 69 00 00 00 00 00 -01 00 80 00 08 3e 60 21 00 00 00 38 00 00 00 00 -01 00 60 00 28 32 a0 40 40 00 00 00 00 00 00 00 -01 10 60 00 28 32 40 41 40 00 00 00 00 00 00 00 -01 00 00 00 44 10 20 26 02 06 00 00 00 00 00 00 -01 10 00 00 44 10 20 26 02 06 00 00 00 00 00 00 -01 20 80 00 28 0e 80 20 00 00 00 08 00 00 00 00 -01 00 60 00 08 22 c0 21 a0 01 cf 00 00 00 00 00 -01 20 80 00 08 02 80 2f e0 01 8d 00 00 00 00 00 -01 20 80 00 28 12 c0 2e 40 0f 8d 00 00 00 00 00 -01 20 80 00 08 06 a0 2c 00 00 00 00 01 00 00 00 -01 00 00 00 4c 06 80 40 00 00 00 00 00 00 00 00 -01 00 60 00 08 10 80 20 00 06 00 00 00 00 00 00 -01 00 60 00 28 12 00 21 40 00 8d 00 00 00 00 00 -01 00 80 00 08 10 80 20 00 06 00 00 00 00 00 00 -01 10 60 00 c8 0a 60 20 40 40 00 00 00 00 00 00 -01 00 60 00 e8 2a a0 20 40 00 00 00 00 00 00 00 -01 00 80 00 e8 2a c0 20 40 00 00 00 00 00 00 00 -01 10 60 00 c8 56 80 20 00 00 00 00 00 00 00 00 -01 10 60 02 28 02 00 22 20 02 8a 00 00 00 00 00 -01 00 60 00 48 36 40 24 00 00 00 30 10 32 54 76 -01 00 60 00 08 0e 00 21 00 00 00 08 30 00 00 00 -01 00 80 00 08 0e 00 21 00 00 00 08 00 00 00 00 -01 00 60 00 48 3b e0 40 44 00 00 00 00 00 00 00 -01 00 00 00 2c 0a a0 20 60 80 00 00 00 00 00 00 -01 00 08 00 2c 0e 40 20 00 00 00 08 ff ff ff ff -01 00 60 00 0c 0e 20 21 00 00 00 08 00 00 00 00 -01 00 60 00 48 3a 40 40 20 01 8d 00 00 00 00 00 -01 00 60 00 48 12 60 20 40 00 ae 00 00 00 00 00 -01 00 60 00 4c 12 80 21 00 01 ae 00 00 00 00 00 -01 00 80 80 e8 3e a0 21 00 00 00 38 00 00 80 3f -01 00 80 00 48 3a 60 42 20 02 8d 00 00 00 00 00 -01 00 80 00 4c 12 80 20 a0 01 ae 00 00 00 00 00 -01 00 60 02 20 06 00 20 00 00 00 00 00 00 00 00 -01 00 80 02 20 06 00 20 00 00 00 00 00 00 00 00 -01 00 40 00 0c 00 60 20 00 18 69 00 00 00 00 00 -01 00 0b 00 2c 0e 20 20 00 00 00 08 ff ff ff ff -01 00 60 00 e8 22 20 21 40 00 00 00 00 00 00 00 -01 00 80 00 e8 22 c0 20 40 00 00 00 00 00 00 00 -01 00 80 00 48 3b 40 41 80 00 8d 00 00 00 00 00 -01 00 60 01 00 02 00 20 40 00 8d 00 00 00 00 00 -01 00 60 80 e8 02 a0 2f 20 01 8d 00 00 00 00 00 -01 00 80 01 08 02 20 20 1c 00 00 00 00 00 00 00 -01 00 60 01 28 3a 40 22 20 02 8d 00 00 00 00 00 -01 00 80 00 e8 1a 60 24 e0 01 ae 00 00 00 00 00 -01 10 60 00 28 4b e0 22 40 03 69 00 00 00 00 00 -01 00 60 00 28 06 40 20 00 00 00 00 00 00 00 00 -01 00 80 00 28 06 40 20 00 00 00 00 00 00 00 00 -01 00 09 00 2c 0e e0 20 00 00 00 08 ff ff ff ff -01 00 60 00 8c 22 e0 2f 40 00 00 00 00 00 00 00 -01 00 60 01 20 3a 00 20 00 03 8d 00 00 00 00 00 -01 00 80 01 20 3a 00 20 80 09 8d 00 00 00 00 00 -01 00 80 00 28 2a e0 20 40 00 ae 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/mul.asm b/src/intel/compiler/elk/tests/gen9/mul.asm deleted file mode 100644 index 36f4a1bcf57..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mul.asm +++ /dev/null @@ -1,31 +0,0 @@ -mul(8) g22<1>F g4<8,8,1>F g2<0,1,0>F { align1 1Q }; -mul(16) g26<1>F g2<0,1,0>F g2<0,1,0>F { align1 1H }; -mul(8) g36<1>DF g8<0,1,0>DF g8<0,1,0>DF { align1 1Q }; -mul(8) g9<1>UD g86<8,8,1>UD 0x00000004UD { align1 1Q }; -mul(8) acc0<1>UD g17<8,8,1>UD 0xaaabUW { align1 1Q }; -mul(8) acc0<1>D g17<8,8,1>D 0x5556UW { align1 1Q }; -mul(8) g21<1>D g20<8,8,1>D 3D { align1 1Q }; -mul(8) acc0<1>UD g39<8,8,1>UD 0xaaabUW { align1 2Q }; -mul(16) g45<1>D g43<8,8,1>D 3D { align1 1H }; -mul(8) acc0<1>D g39<8,8,1>D 0x5556UW { align1 2Q }; -mul.z.f0.0(8) g10<1>F g5<0,1,0>F g9<8,8,1>F { align1 1Q }; -mul(8) g39<1>DF g3.3<0,1,0>DF g3.3<0,1,0>DF { align1 2Q }; -mul.z.f0.0(16) g6<1>F g2<0,1,0>F g4<8,8,1>F { align1 1H }; -mul.sat(8) g17<1>F g4<8,8,1>F g16<8,8,1>F { align1 1Q }; -mul.sat(16) g9<1>F g3<8,8,1>F g7<8,8,1>F { align1 1H }; -mul.l.f0.0(8) null<1>F g6<0,1,0>F g5.7<0,1,0>F { align1 1Q }; -mul.sat(8) g8<1>DF g34<4,4,1>DF g5<4,4,1>DF { align1 1Q }; -mul(8) g4<1>UQ g8<4,4,1>UD g12<4,4,1>UD { align1 1Q }; -mul(8) g20<1>UQ g5<4,4,1>UD g13<4,4,1>UD { align1 2Q }; -mul(8) g5<1>Q g9<4,4,1>D g13<4,4,1>D { align1 1Q }; -mul.sat(8) g10<1>DF g10<4,4,1>DF g16<4,4,1>DF { align1 2Q }; -mul.l.f0.0(8) g20<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1Q }; -mul.l.f0.0(16) g32<1>F g2<8,8,1>F 0x42700000F /* 60F */ { align1 1H }; -mul(1) g6<1>UD g12<0,1,0>UD 0x00000101UD { align1 WE_all 1N }; -mul(8) g21<1>Q g6<4,4,1>D g14<4,4,1>D { align1 2Q }; -mul.l.f0.0(16) null<1>F g2.2<0,1,0>F g2.1<0,1,0>F { align1 1H }; -mul(8) g6<1>UW g6<8,8,1>UW 0x0808UW { align1 1Q }; -mul(16) g15<1>UW g14<16,16,1>UW 0x0808UW { align1 1H }; -mul.nz.f0.0(8) g6<1>F g12<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 1Q }; -mul.nz.f0.0(16) g9<1>F g7<8,8,1>F 0x3f808000F /* 1.00391F */ { align1 1H }; -mul(1) g4<1>UD g4<0,1,0>UD 0x00000101UD { align1 WE_all 3N }; diff --git a/src/intel/compiler/elk/tests/gen9/mul.expected b/src/intel/compiler/elk/tests/gen9/mul.expected deleted file mode 100644 index 1a1a79c6467..00000000000 --- a/src/intel/compiler/elk/tests/gen9/mul.expected +++ /dev/null @@ -1,31 +0,0 @@ -41 00 60 00 e8 3a c0 22 80 00 8d 3a 40 00 00 00 -41 00 80 00 e8 3a 40 23 40 00 00 3a 40 00 00 00 -41 00 60 00 c8 32 80 24 00 01 00 32 00 01 00 00 -41 00 60 00 08 02 20 21 c0 0a 8d 06 04 00 00 00 -41 00 60 00 00 02 00 24 20 02 8d 16 ab aa ab aa -41 00 60 00 20 0a 00 24 20 02 8d 16 56 55 56 55 -41 00 60 00 28 0a a0 22 80 02 8d 0e 03 00 00 00 -41 10 60 00 00 02 00 24 e0 04 8d 16 ab aa ab aa -41 00 80 00 28 0a a0 25 60 05 8d 0e 03 00 00 00 -41 10 60 00 20 0a 00 24 e0 04 8d 16 56 55 56 55 -41 00 60 01 e8 3a 40 21 a0 00 00 3a 20 01 8d 00 -41 10 60 00 c8 32 e0 24 78 00 00 32 78 00 00 00 -41 00 80 01 e8 3a c0 20 40 00 00 3a 80 00 8d 00 -41 00 60 80 e8 3a 20 22 80 00 8d 3a 00 02 8d 00 -41 00 80 80 e8 3a 20 21 60 00 8d 3a e0 00 8d 00 -41 00 60 05 e0 3a 00 20 c0 00 00 3a bc 00 00 00 -41 00 60 80 c8 32 00 21 40 04 69 32 a0 00 69 00 -41 00 60 00 08 03 80 20 00 01 69 02 80 01 69 00 -41 10 60 00 08 03 80 22 a0 00 69 02 a0 01 69 00 -41 00 60 00 28 0b a0 20 20 01 69 0a a0 01 69 00 -41 10 60 80 c8 32 40 21 40 01 69 32 00 02 69 00 -41 00 60 05 e8 3a 80 22 40 00 8d 3e 00 00 70 42 -41 00 80 05 e8 3a 00 24 40 00 8d 3e 00 00 70 42 -41 00 00 00 0c 02 c0 20 80 01 00 06 01 01 00 00 -41 10 60 00 28 0b a0 22 c0 00 69 0a c0 01 69 00 -41 00 80 05 e0 3a 00 20 48 00 00 3a 44 00 00 00 -41 00 60 00 48 12 c0 20 c0 00 8d 16 08 08 08 08 -41 00 80 00 48 12 e0 21 c0 01 b1 16 08 08 08 08 -41 00 60 02 e8 3a c0 20 80 01 8d 3e 00 80 80 3f -41 00 80 02 e8 3a 20 21 e0 00 8d 3e 00 80 80 3f -41 10 00 00 0c 02 80 20 80 00 00 06 01 01 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/nop.asm b/src/intel/compiler/elk/tests/gen9/nop.asm deleted file mode 100644 index 0b66395094f..00000000000 --- a/src/intel/compiler/elk/tests/gen9/nop.asm +++ /dev/null @@ -1 +0,0 @@ -nop ; diff --git a/src/intel/compiler/elk/tests/gen9/nop.expected b/src/intel/compiler/elk/tests/gen9/nop.expected deleted file mode 100644 index 9a3dcf265b5..00000000000 --- a/src/intel/compiler/elk/tests/gen9/nop.expected +++ /dev/null @@ -1 +0,0 @@ -7e 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/not.asm b/src/intel/compiler/elk/tests/gen9/not.asm deleted file mode 100644 index ce4592bd74f..00000000000 --- a/src/intel/compiler/elk/tests/gen9/not.asm +++ /dev/null @@ -1,2 +0,0 @@ -not(16) g3<1>D g1.2<0,1,0>D { align1 1H }; -not(8) g4<1>D g8<8,8,1>D { align1 1Q }; diff --git a/src/intel/compiler/elk/tests/gen9/not.expected b/src/intel/compiler/elk/tests/gen9/not.expected deleted file mode 100644 index 3a66a221c46..00000000000 --- a/src/intel/compiler/elk/tests/gen9/not.expected +++ /dev/null @@ -1,2 +0,0 @@ -04 00 80 00 28 0a 60 20 28 00 00 00 00 00 00 00 -04 00 60 00 28 0a 80 20 00 01 8d 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/or.asm b/src/intel/compiler/elk/tests/gen9/or.asm deleted file mode 100644 index 3bfcc980749..00000000000 --- a/src/intel/compiler/elk/tests/gen9/or.asm +++ /dev/null @@ -1,23 +0,0 @@ -or(8) g53<1>UD g49<8,8,1>UD g21<8,8,1>UD { align1 1Q }; -or.nz.f0.0(8) null<1>UD g21<8,8,1>UD g2<8,8,1>UD { align1 1Q }; -or.nz.f0.0(8) g5<1>UD g62<8,8,1>UD g67<8,8,1>UD { align1 1Q }; -or(8) g5<1>UD g106.1<8,4,2>UD 0x7ff00000UD { align1 2Q }; -or.nz.f0.0(16) null<1>UD g35<8,8,1>UD g32<8,8,1>UD { align1 1H }; -or(16) g36<1>UD g34<8,8,1>UD g20<8,8,1>UD { align1 1H }; -or.nz.f0.0(16) g53<1>UD g51<8,8,1>UD g49<8,8,1>UD { align1 1H }; -or(1) g8<1>UD g8<0,1,0>UD g4<0,1,0>UD { align1 WE_all 1N }; -or(1) a0<1>UD g8<0,1,0>UD 0x060ba000UD { align1 WE_all 1N }; -(+f0.0) or(8) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1Q }; -(+f0.0) or(16) g3<1>UD g3<8,8,1>UD 0x3f800000UD { align1 1H }; -or(1) a0<1>UD a0<0,1,0>UD 0x02280300UD { align1 WE_all 1N }; -or(1) a0<1>UD g4<0,1,0>UD 0x04036000UD { align1 WE_all 3N }; -(+f0.0) or(8) g17.1<2>UD g17.1<8,4,2>UD 0x3ff00000UD { align1 2Q }; -or(8) g4<1>UW g4<8,8,1>UW g6<8,8,1>UW { align1 1Q }; -or(16) g16<1>UW g14<16,16,1>UW g15<16,16,1>UW { align1 1H }; -or(8) g22<1>UD ~g2.2<0,1,0>D g21<8,8,1>UD { align1 1Q }; -or(16) g37<1>UD ~g2.2<0,1,0>D g35<8,8,1>UD { align1 1H }; -or(8) g9<1>D ~g8<8,8,1>D ~g7<8,8,1>D { align1 1Q }; -or(16) g13<1>D ~g11<8,8,1>D ~g9<8,8,1>D { align1 1H }; -or(1) g14<1>UD g14<0,1,0>UD g19<0,1,0>UD { align1 WE_all 3N }; -or.z.f0.0(8) null<1>UD g5<8,8,1>UD g6<8,8,1>UD { align1 1Q }; -or.z.f0.0(16) null<1>UD g17<8,8,1>UD g19<8,8,1>UD { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/or.expected b/src/intel/compiler/elk/tests/gen9/or.expected deleted file mode 100644 index 61e2fccc15c..00000000000 --- a/src/intel/compiler/elk/tests/gen9/or.expected +++ /dev/null @@ -1,23 +0,0 @@ -06 00 60 00 08 02 a0 26 20 06 8d 02 a0 02 8d 00 -06 00 60 02 00 02 00 20 a0 02 8d 02 40 00 8d 00 -06 00 60 02 08 02 a0 20 c0 07 8d 02 60 08 8d 00 -06 10 60 00 08 02 a0 20 44 0d 8a 06 00 00 f0 7f -06 00 80 02 00 02 00 20 60 04 8d 02 00 04 8d 00 -06 00 80 00 08 02 80 24 40 04 8d 02 80 02 8d 00 -06 00 80 02 08 02 a0 26 60 06 8d 02 20 06 8d 00 -06 00 00 00 0c 02 00 21 00 01 00 02 80 00 00 00 -06 00 00 00 04 02 00 22 00 01 00 06 00 a0 0b 06 -06 00 61 00 08 02 60 20 60 00 8d 06 00 00 80 3f -06 00 81 00 08 02 60 20 60 00 8d 06 00 00 80 3f -06 00 00 00 04 00 00 22 00 02 00 06 00 03 28 02 -06 10 00 00 04 02 00 22 80 00 00 06 00 60 03 04 -06 10 61 00 08 02 24 42 24 02 8a 06 00 00 f0 3f -06 00 60 00 48 12 80 20 80 00 8d 12 c0 00 8d 00 -06 00 80 00 48 12 00 22 c0 01 b1 12 e0 01 b1 00 -06 00 60 00 08 0a c0 22 48 40 00 02 a0 02 8d 00 -06 00 80 00 08 0a a0 24 48 40 00 02 60 04 8d 00 -06 00 60 00 28 0a 20 21 00 41 8d 0a e0 40 8d 00 -06 00 80 00 28 0a a0 21 60 41 8d 0a 20 41 8d 00 -06 10 00 00 0c 02 c0 21 c0 01 00 02 60 02 00 00 -06 00 60 01 00 02 00 20 a0 00 8d 02 c0 00 8d 00 -06 00 80 01 00 02 00 20 20 02 8d 02 60 02 8d 00 diff --git a/src/intel/compiler/elk/tests/gen9/pln.asm b/src/intel/compiler/elk/tests/gen9/pln.asm deleted file mode 100644 index 5b0adcf28cd..00000000000 --- a/src/intel/compiler/elk/tests/gen9/pln.asm +++ /dev/null @@ -1,10 +0,0 @@ -pln(8) g124<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; -pln(16) g120<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; -pln.sat(8) g9<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q }; -pln.sat(16) g12<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H }; -pln.g.f0.0(8) g7<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; -pln.g.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; -pln.l.f0.0(8) g8<1>F g4<0,1,0>F g2<8,8,1>F { align1 1Q }; -pln.l.f0.0(16) g11<1>F g6<0,1,0>F g2<8,8,1>F { align1 1H }; -pln.nz.f0.0(8) g18<1>F g5<0,1,0>F g2<8,8,1>F { align1 1Q }; -pln.nz.f0.0(16) g14<1>F g7<0,1,0>F g2<8,8,1>F { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/pln.expected b/src/intel/compiler/elk/tests/gen9/pln.expected deleted file mode 100644 index eb77b2a434f..00000000000 --- a/src/intel/compiler/elk/tests/gen9/pln.expected +++ /dev/null @@ -1,10 +0,0 @@ -5a 00 60 00 e8 3a 80 2f 80 00 00 3a 40 00 8d 00 -5a 00 80 00 e8 3a 00 2f c0 00 00 3a 40 00 8d 00 -5a 00 60 80 e8 3a 20 21 a0 00 00 3a 40 00 8d 00 -5a 00 80 80 e8 3a 80 21 e0 00 00 3a 40 00 8d 00 -5a 00 60 03 e8 3a e0 20 80 00 00 3a 40 00 8d 00 -5a 00 80 03 e8 3a 60 21 c0 00 00 3a 40 00 8d 00 -5a 00 60 05 e8 3a 00 21 80 00 00 3a 40 00 8d 00 -5a 00 80 05 e8 3a 60 21 c0 00 00 3a 40 00 8d 00 -5a 00 60 02 e8 3a 40 22 a0 00 00 3a 40 00 8d 00 -5a 00 80 02 e8 3a c0 21 e0 00 00 3a 40 00 8d 00 diff --git a/src/intel/compiler/elk/tests/gen9/rndd.asm b/src/intel/compiler/elk/tests/gen9/rndd.asm deleted file mode 100644 index 463ef808ca9..00000000000 --- a/src/intel/compiler/elk/tests/gen9/rndd.asm +++ /dev/null @@ -1,5 +0,0 @@ -rndd(8) g22<1>F g17<0,1,0>F { align1 1Q }; -rndd(16) g7<1>F g5<8,8,1>F { align1 1H }; -rndd.z.f0.0(8) null<1>F g17<8,8,1>F { align1 1Q }; -rndd.z.f0.0(16) null<1>F g39<8,8,1>F { align1 1H }; -rndd.sat(8) g124<1>F g10<8,8,1>F { align1 1Q }; diff --git a/src/intel/compiler/elk/tests/gen9/rndd.expected b/src/intel/compiler/elk/tests/gen9/rndd.expected deleted file mode 100644 index ff7ca82d09f..00000000000 --- a/src/intel/compiler/elk/tests/gen9/rndd.expected +++ /dev/null @@ -1,5 +0,0 @@ -45 00 60 00 e8 3a c0 22 20 02 00 00 00 00 00 00 -45 00 80 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00 -45 00 60 01 e0 3a 00 20 20 02 8d 00 00 00 00 00 -45 00 80 01 e0 3a 00 20 e0 04 8d 00 00 00 00 00 -45 00 60 80 e8 3a 80 2f 40 01 8d 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/rnde.asm b/src/intel/compiler/elk/tests/gen9/rnde.asm deleted file mode 100644 index bc65bbcc02d..00000000000 --- a/src/intel/compiler/elk/tests/gen9/rnde.asm +++ /dev/null @@ -1,2 +0,0 @@ -rnde(8) g7<1>F g5<8,8,1>F { align1 1Q }; -rnde(16) g11<1>F g7<8,8,1>F { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/rnde.expected b/src/intel/compiler/elk/tests/gen9/rnde.expected deleted file mode 100644 index edac496ec93..00000000000 --- a/src/intel/compiler/elk/tests/gen9/rnde.expected +++ /dev/null @@ -1,2 +0,0 @@ -46 00 60 00 e8 3a e0 20 a0 00 8d 00 00 00 00 00 -46 00 80 00 e8 3a 60 21 e0 00 8d 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/rndz.asm b/src/intel/compiler/elk/tests/gen9/rndz.asm deleted file mode 100644 index 4b082d0539b..00000000000 --- a/src/intel/compiler/elk/tests/gen9/rndz.asm +++ /dev/null @@ -1,2 +0,0 @@ -rndz(8) g7<1>F g2<0,1,0>F { align1 1Q }; -rndz(16) g102<1>F g99<8,8,1>F { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/rndz.expected b/src/intel/compiler/elk/tests/gen9/rndz.expected deleted file mode 100644 index 2a79a2372d9..00000000000 --- a/src/intel/compiler/elk/tests/gen9/rndz.expected +++ /dev/null @@ -1,2 +0,0 @@ -47 00 60 00 e8 3a e0 20 40 00 00 00 00 00 00 00 -47 00 80 00 e8 3a c0 2c 60 0c 8d 00 00 00 00 00 diff --git a/src/intel/compiler/elk/tests/gen9/sel.asm b/src/intel/compiler/elk/tests/gen9/sel.asm deleted file mode 100644 index 6047c31b517..00000000000 --- a/src/intel/compiler/elk/tests/gen9/sel.asm +++ /dev/null @@ -1,33 +0,0 @@ -(-f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x3f800000UD { align1 1Q }; -(+f0.0) sel(8) g124<1>UD g124<8,8,1>UD 0x00000000UD { align1 1Q }; -(+f0.0) sel(8) g24<1>UQ g66<4,4,1>UQ g40<4,4,1>UQ { align1 1Q }; -(+f0.0) sel(8) g36<1>UQ g50<4,4,1>UQ g31<4,4,1>UQ { align1 2Q }; -sel.ge(8) g17<1>F (abs)g16<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; -sel.ge(16) g37<1>F (abs)g35<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; -(+f0.0) sel(16) g26<1>UD g31<8,8,1>UD g33<8,8,1>UD { align1 1H }; -(-f0.0) sel(16) g1<1>UD g55<8,8,1>UD 0x00000000UD { align1 1H }; -sel.l(8) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1Q }; -sel.l(16) g3<1>UD g2.1<0,1,0>UD 0x00000001UD { align1 1H }; -sel.ge(8) g3<1>D g2<0,1,0>D -1D { align1 1Q }; -sel.l(8) g4<1>D g3<8,8,1>D 1D { align1 1Q }; -sel.ge(16) g3<1>D g2<0,1,0>D -1D { align1 1H }; -sel.l(16) g5<1>D g3<8,8,1>D 1D { align1 1H }; -sel.l(8) g8<1>F g7<8,8,1>F 0x43000000F /* 128F */ { align1 1Q }; -(-f0.0) sel.sat(8) g126<1>F g11<8,8,1>F 0x0F /* 0F */ { align1 1Q }; -sel.l(8) g18<1>DF g5<0,1,0>DF g5.1<0,1,0>DF { align1 1Q }; -sel.ge(16) g37<1>UD g9<8,8,1>UD g13<8,8,1>UD { align1 1H }; -sel.ge(8) g19<1>UD g5<0,1,0>UD g5.4<0,1,0>UD { align1 1Q }; -sel.sat.l(8) g124<1>F g6<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1Q }; -(+f0.0) sel(8) g26<1>F g5<0,1,0>F (abs)g5.3<0,1,0>F { align1 1Q }; -(-f0.0) sel(8) g44<1>F (abs)g41<8,8,1>F 0x3f800000F /* 1F */ { align1 1Q }; -sel.l(16) g120<1>F g2.3<0,1,0>F g2.2<0,1,0>F { align1 1H }; -(+f0.0) sel(8) g9<1>DF g2<0,1,0>DF -g2<0,1,0>DF { align1 1Q }; -(+f0.0) sel(8) g12<1>DF g2<0,1,0>DF -g2<0,1,0>DF { align1 2Q }; -sel.ge(8) g5<1>DF g2<0,1,0>DF g2.2<0,1,0>DF { align1 1Q }; -sel.ge(8) g35<1>DF g2<0,1,0>DF g2.2<0,1,0>DF { align1 2Q }; -sel.l(8) g11<1>DF g35<4,4,1>DF g3<0,1,0>DF { align1 2Q }; -(+f0.0) sel.sat(8) g126<1>F g11<8,8,1>F 0x0F /* 0F */ { align1 1Q }; -(-f0.0) sel(16) g27<1>F (abs)g25<8,8,1>F 0x3f800000F /* 1F */ { align1 1H }; -(+f0.0) sel(16) g36<1>F g2<0,1,0>F (abs)g2.4<0,1,0>F { align1 1H }; -(+f0.0) sel(16) g116<1>UD g112<8,8,1>UD g114<8,8,1>UD { align1 2H }; -sel.sat.l(16) g8<1>F g83<8,8,1>F 0x3f000000F /* 0.5F */ { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/sel.expected b/src/intel/compiler/elk/tests/gen9/sel.expected deleted file mode 100644 index aba34ca3d75..00000000000 --- a/src/intel/compiler/elk/tests/gen9/sel.expected +++ /dev/null @@ -1,33 +0,0 @@ -02 00 71 00 08 02 80 2f 80 0f 8d 06 00 00 80 3f -02 00 61 00 08 02 80 2f 80 0f 8d 06 00 00 00 00 -02 00 61 00 08 43 00 23 40 08 69 42 00 05 69 00 -02 10 61 00 08 43 80 24 40 06 69 42 e0 03 69 00 -02 00 60 04 e8 3a 20 22 00 22 8d 3e 00 00 80 3f -02 00 80 04 e8 3a a0 24 60 24 8d 3e 00 00 80 3f -02 00 81 00 08 02 40 23 e0 03 8d 02 20 04 8d 00 -02 00 91 00 08 02 20 20 e0 06 8d 06 00 00 00 00 -02 00 60 05 08 02 60 20 44 00 00 06 01 00 00 00 -02 00 80 05 08 02 60 20 44 00 00 06 01 00 00 00 -02 00 60 04 28 0a 60 20 40 00 00 0e ff ff ff ff -02 00 60 05 28 0a 80 20 60 00 8d 0e 01 00 00 00 -02 00 80 04 28 0a 60 20 40 00 00 0e ff ff ff ff -02 00 80 05 28 0a a0 20 60 00 8d 0e 01 00 00 00 -02 00 60 05 e8 3a 00 21 e0 00 8d 3e 00 00 00 43 -02 00 71 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00 -02 00 60 05 c8 32 40 22 a0 00 00 32 a8 00 00 00 -02 00 80 04 08 02 a0 24 20 01 8d 02 a0 01 8d 00 -02 00 60 04 08 02 60 22 a0 00 00 02 b0 00 00 00 -02 00 60 85 e8 3a 80 2f c0 00 8d 3e 00 00 00 3f -02 00 61 00 e8 3a 40 23 a0 00 00 3a ac 20 00 00 -02 00 71 00 e8 3a 80 25 20 25 8d 3e 00 00 80 3f -02 00 80 05 e8 3a 00 2f 4c 00 00 3a 48 00 00 00 -02 00 61 00 c8 32 20 21 40 00 00 32 40 40 00 00 -02 10 61 00 c8 32 80 21 40 00 00 32 40 40 00 00 -02 00 60 04 c8 32 a0 20 40 00 00 32 50 00 00 00 -02 10 60 04 c8 32 60 24 40 00 00 32 50 00 00 00 -02 10 60 05 c8 32 60 21 60 04 69 32 60 00 00 00 -02 00 61 80 e8 3a c0 2f 60 01 8d 3e 00 00 00 00 -02 00 91 00 e8 3a 60 23 20 23 8d 3e 00 00 80 3f -02 00 81 00 e8 3a 80 24 40 00 00 3a 50 20 00 00 -02 20 81 00 08 02 80 2e 00 0e 8d 02 40 0e 8d 00 -02 00 80 85 e8 3a 00 21 60 0a 8d 3e 00 00 00 3f diff --git a/src/intel/compiler/elk/tests/gen9/send.asm b/src/intel/compiler/elk/tests/gen9/send.asm deleted file mode 100644 index 918859e7d52..00000000000 --- a/src/intel/compiler/elk/tests/gen9/send.asm +++ /dev/null @@ -1,3606 +0,0 @@ -send(8) null<1>F g123<8,8,1>F 0x8a080017 - urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g13<8,8,1>F 0x12080007 - urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080027 - urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(16) g9<1>UD g2<0,1,0>UD 0x02280300 - const MsgDesc: (0, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; -send(8) null<1>F g119<8,8,1>F 0x92080017 - urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(16) null<1>UW g127<8,8,1>UW 0x82000010 - thread_spawner MsgDesc: mlen 1 rlen 0 { align1 WE_all 1H EOT }; -send(8) g124<1>UW g13<8,8,1>UD 0x0643a001 - sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) g120<1>UW g23<8,8,1>UD 0x0c85a001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(8) g10<1>UD g2<8,8,1>UD 0x02480028 - urb MsgDesc: 2 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g8<8,8,1>F 0x140a0017 - urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0017 - urb MsgDesc: 1 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; -send(8) g2<1>UW g10<8,8,1>UD 0x08427001 - sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(16) g2<1>UW g18<8,8,1>UD 0x10847001 - sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; -send(8) null<1>F g11<8,8,1>UD 0x0c0a0037 - urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a080027 - urb MsgDesc: 2 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c088017 - urb MsgDesc: 1 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a088017 - urb MsgDesc: 1 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x08088017 - urb MsgDesc: 1 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>UD 0x06088017 - urb MsgDesc: 1 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c088007 - urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a088007 - urb MsgDesc: 0 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g125<8,8,1>UD 0x86088007 - urb MsgDesc: 0 SIMD8 write masked mlen 3 rlen 0 { align1 1Q EOT }; -send(8) g7<1>UW g7<8,8,1>UD 0x0443a000 - sampler MsgDesc: ld_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g10<1>UW g6<8,8,1>UD 0x0222a001 - sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1Q }; -send(8) g2<1>UW g19<8,8,1>UD 0x084a8001 - sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(16) g25<1>UW g16<8,8,1>UD 0x0444a001 - sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H }; -send(16) g14<1>UW g7<8,8,1>UD 0x0e8c8001 - sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H }; -send(8) null<1>F g11<8,8,1>F 0x12080017 - urb MsgDesc: 1 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>F 0x12080037 - urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080057 - urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g9<1>UW g6<8,8,1>UD 0x0613d001 - sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; -send(16) g12<1>UW g14<8,8,1>UD 0x0c25d001 - sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; -send(8) g2<1>UW g14<8,8,1>UD 0x0643d001 - sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g8<1>UW g17<8,8,1>UD 0x0a43e001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(16) g26<1>UW g10<8,8,1>UD 0x0c85d001 - sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(16) g34<1>UW g16<8,8,1>UD 0x1485e001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; -send(8) g5<1>UW g2<8,8,1>UD 0x04320001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 3 { align1 1Q }; -send(16) g7<1>UW g2<8,8,1>UD 0x08640001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 6 { align1 1H }; -send(8) g12<1>UW g10<8,8,1>UD 0x0a33e001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 3 { align1 1Q }; -send(16) g2<1>UW g18<8,8,1>UD 0x1465e001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 6 { align1 1H }; -send(8) g5<1>UW g2<8,8,1>UD 0x04420001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(16) g7<1>UW g2<8,8,1>UD 0x08840001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(8) g11<1>UW g9<8,8,1>UD 0x0222a000 - sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 2 { align1 1Q }; -send(8) g124<1>UW g13<8,8,1>UD 0x064a8000 - sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g12<1>UW g5<8,8,1>UD 0x02427000 - sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080037 - urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g6<1>UW g11<8,8,1>UD 0x144a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1Q }; -(+f1.0) send(8) g125<1>UW g3<8,8,1>UD 0x0210b501 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 1Q }; -(+f1.0) send(16) g122<1>UW g4<8,8,1>UD 0x0420a501 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 2 { align1 1H }; -send(8) g6<1>UW g12<8,8,1>UD 0x084a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) g98<1>UW g17<8,8,1>UD 0x0c43c001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(8) g124<1>UW g8<8,8,1>UD 0x064a8001 - sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) g120<1>UW g12<8,8,1>UD 0x0a8c8001 - sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H }; -send(8) g6<1>UW g7<8,8,1>UD 0x0a1a6001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(8) g7<1>UW g12<8,8,1>UD 0x0a1a6102 - sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; -send(16) g10<1>UW g12<8,8,1>UD 0x122c6001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 2 { align1 1H }; -send(16) g12<1>UW g21<8,8,1>UD 0x122c6102 - sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 2 { align1 1H }; -send(8) g124<1>UW g3<8,8,1>UD 0x0a43e000 - sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080027 - urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g2<1>UW g3<8,8,1>UD 0x0643d000 - sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) null<1>F g7<8,8,1>UD 0x0a080037 - urb MsgDesc: 3 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0a080047 - urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>F 0x0c0a0017 - urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0017 - urb MsgDesc: 1 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g13<1>UW g10<8,8,1>UD 0x02320001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; -send(16) g22<1>UW g18<8,8,1>UD 0x04640001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 6 { align1 1H }; -send(8) g124<1>UW g2<8,8,1>UD 0x0232a000 - sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x0c4b1001 - sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(16) g18<1>UW g7<8,8,1>UD 0x168d1001 - sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; -send(8) null<1>F g6<8,8,1>UD 0x0a088027 - urb MsgDesc: 2 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g7<8,8,1>UD 0x0a088037 - urb MsgDesc: 3 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0a088047 - urb MsgDesc: 4 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g9<8,8,1>UD 0x0a088057 - urb MsgDesc: 5 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) g124<1>UW g3<8,8,1>UD 0x06427000 - sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x06427001 - sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) g2<1>UW g18<8,8,1>UD 0x0c847001 - sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(8) g6<1>UW g10<8,8,1>UD 0x0c424001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(8) g2<1>UW g7<8,8,1>UD 0x0c4b1000 - sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(8) g2<1>UW g4<8,8,1>UD 0x0242a000 - sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x0242a101 - sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 4 { align1 1Q }; -send(8) g10<1>UW g10<8,8,1>UD 0x0242a202 - sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 4 { align1 1Q }; -send(8) g14<1>UW g14<8,8,1>UD 0x0242a303 - sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 4 { align1 1Q }; -send(8) g18<1>UW g18<8,8,1>UD 0x0242a404 - sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UW g22<8,8,1>UD 0x0242a505 - sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UW g26<8,8,1>UD 0x0242a606 - sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 6 mlen 1 rlen 4 { align1 1Q }; -send(8) g6<1>UD g15<8,8,1>UD 0x042a0318 - urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g8<1>UD g15<8,8,1>UD 0x042a0518 - urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g10<1>UD g15<8,8,1>UD 0x042a0718 - urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g12<1>UD g15<8,8,1>UD 0x042a0918 - urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g14<1>UD g15<8,8,1>UD 0x042a0128 - urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g16<1>UD g14<8,8,1>UD 0x042a0218 - urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g18<1>UD g14<8,8,1>UD 0x042a0418 - urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g20<1>UD g14<8,8,1>UD 0x042a0618 - urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g22<1>UD g14<8,8,1>UD 0x042a0818 - urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g13<1>UD g14<8,8,1>UD 0x042a0028 - urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g30<8,8,1>UD 0x02480208 - urb MsgDesc: 32 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g14<1>UD g30<8,8,1>UD 0x02480408 - urb MsgDesc: 64 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g18<1>UD g30<8,8,1>UD 0x02480608 - urb MsgDesc: 96 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g30<8,8,1>UD 0x02480808 - urb MsgDesc: 128 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a0a8217 - urb MsgDesc: 33 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0a0a8227 - urb MsgDesc: 34 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0a0a8237 - urb MsgDesc: 35 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0a0a8247 - urb MsgDesc: 36 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0a0a8257 - urb MsgDesc: 37 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0a0a8267 - urb MsgDesc: 38 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a0a8277 - urb MsgDesc: 39 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a0a8287 - urb MsgDesc: 40 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a0a8297 - urb MsgDesc: 41 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a0a82a7 - urb MsgDesc: 42 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0a82b7 - urb MsgDesc: 43 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0a82c7 - urb MsgDesc: 44 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0a82d7 - urb MsgDesc: 45 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0a82e7 - urb MsgDesc: 46 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0a82f7 - urb MsgDesc: 47 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0a8307 - urb MsgDesc: 48 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a0a8317 - urb MsgDesc: 49 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a0a8327 - urb MsgDesc: 50 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a0a8337 - urb MsgDesc: 51 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a0a8347 - urb MsgDesc: 52 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a0a8357 - urb MsgDesc: 53 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a0a8367 - urb MsgDesc: 54 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a0a8377 - urb MsgDesc: 55 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a0a8387 - urb MsgDesc: 56 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a0a8397 - urb MsgDesc: 57 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a0a83a7 - urb MsgDesc: 58 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0a83b7 - urb MsgDesc: 59 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0a83c7 - urb MsgDesc: 60 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0a83d7 - urb MsgDesc: 61 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0a83e7 - urb MsgDesc: 62 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0a0a83f7 - urb MsgDesc: 63 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x08088027 - urb MsgDesc: 2 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x08088037 - urb MsgDesc: 3 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x08088047 - urb MsgDesc: 4 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x08088057 - urb MsgDesc: 5 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x08088067 - urb MsgDesc: 6 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x08088077 - urb MsgDesc: 7 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x08088087 - urb MsgDesc: 8 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x08088097 - urb MsgDesc: 9 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080880a7 - urb MsgDesc: 10 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x080880b7 - urb MsgDesc: 11 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x080880c7 - urb MsgDesc: 12 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x080880d7 - urb MsgDesc: 13 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x080880e7 - urb MsgDesc: 14 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x080880f7 - urb MsgDesc: 15 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x08088107 - urb MsgDesc: 16 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x08088117 - urb MsgDesc: 17 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x08088127 - urb MsgDesc: 18 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x08088137 - urb MsgDesc: 19 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x08088147 - urb MsgDesc: 20 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x08088157 - urb MsgDesc: 21 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x08088167 - urb MsgDesc: 22 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x08088177 - urb MsgDesc: 23 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x08088187 - urb MsgDesc: 24 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x08088197 - urb MsgDesc: 25 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x080881a7 - urb MsgDesc: 26 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x080881b7 - urb MsgDesc: 27 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x080881c7 - urb MsgDesc: 28 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x080881d7 - urb MsgDesc: 29 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x080881e7 - urb MsgDesc: 30 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x080881f7 - urb MsgDesc: 31 SIMD8 write masked mlen 4 rlen 0 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x02480018 - urb MsgDesc: 1 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0c0a0207 - urb MsgDesc: 32 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080057 - urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g10<1>UW g18<8,8,1>UD 0x084a8000 - sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) g124<1>UW g2<8,8,1>UD 0x04229001 - sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1Q }; -send(16) g120<1>UW g2<8,8,1>UD 0x08449001 - sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H }; -send(16) g32<1>UW g44<8,8,1>UD 0x0865a001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 6 { align1 1H }; -send(16) null<1>UW g5<8,8,1>UD 0x04008502 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(8) g5<1>UW g3<8,8,1>UD 0x02427001 - sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(16) g8<1>UW g5<8,8,1>UD 0x04847001 - sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; -send(8) null<1>F g119<8,8,1>F 0x92080007 - urb MsgDesc: 0 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g126<8,8,1>UD 0x84080017 - urb MsgDesc: 1 SIMD8 write mlen 2 rlen 0 { align1 1Q EOT }; -send(8) g2<1>UW g13<8,8,1>UD 0x0a4b1001 - sampler MsgDesc: gather4_po SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(16) g16<1>UW g7<8,8,1>UD 0x128d1001 - sampler MsgDesc: gather4_po SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H }; -send(8) g38<1>UD g1<8,8,1>UD 0x02180028 - urb MsgDesc: 2 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g40<1>UD g1<8,8,1>UD 0x02180038 - urb MsgDesc: 3 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g42<1>UD g1<8,8,1>UD 0x02180048 - urb MsgDesc: 4 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g44<1>UD g1<8,8,1>UD 0x02180058 - urb MsgDesc: 5 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g46<1>UD g1<8,8,1>UD 0x02180068 - urb MsgDesc: 6 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g48<1>UD g1<8,8,1>UD 0x02180078 - urb MsgDesc: 7 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g50<1>UD g1<8,8,1>UD 0x02180088 - urb MsgDesc: 8 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g52<1>UD g1<8,8,1>UD 0x02180098 - urb MsgDesc: 9 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g54<1>UD g1<8,8,1>UD 0x021800a8 - urb MsgDesc: 10 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g56<1>UD g1<8,8,1>UD 0x021800b8 - urb MsgDesc: 11 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g58<1>UD g1<8,8,1>UD 0x021800c8 - urb MsgDesc: 12 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g60<1>UD g1<8,8,1>UD 0x021800d8 - urb MsgDesc: 13 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g62<1>UD g1<8,8,1>UD 0x021800e8 - urb MsgDesc: 14 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g64<1>UD g1<8,8,1>UD 0x021800f8 - urb MsgDesc: 15 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g66<1>UD g1<8,8,1>UD 0x02180108 - urb MsgDesc: 16 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g68<1>UD g1<8,8,1>UD 0x02180118 - urb MsgDesc: 17 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g70<1>UD g1<8,8,1>UD 0x02180128 - urb MsgDesc: 18 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g72<1>UD g1<8,8,1>UD 0x02180138 - urb MsgDesc: 19 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g74<1>UD g1<8,8,1>UD 0x02180148 - urb MsgDesc: 20 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g76<1>UD g1<8,8,1>UD 0x02180158 - urb MsgDesc: 21 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g78<1>UD g1<8,8,1>UD 0x02180168 - urb MsgDesc: 22 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g80<1>UD g1<8,8,1>UD 0x02180178 - urb MsgDesc: 23 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g82<1>UD g1<8,8,1>UD 0x02180188 - urb MsgDesc: 24 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g84<1>UD g1<8,8,1>UD 0x02180198 - urb MsgDesc: 25 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g86<1>UD g1<8,8,1>UD 0x021801a8 - urb MsgDesc: 26 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g88<1>UD g1<8,8,1>UD 0x021801b8 - urb MsgDesc: 27 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g90<1>UD g1<8,8,1>UD 0x021801c8 - urb MsgDesc: 28 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g92<1>UD g1<8,8,1>UD 0x021801d8 - urb MsgDesc: 29 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g94<1>UD g1<8,8,1>UD 0x021801e8 - urb MsgDesc: 30 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g96<1>UD g1<8,8,1>UD 0x021801f8 - urb MsgDesc: 31 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g98<1>UD g1<8,8,1>UD 0x02180208 - urb MsgDesc: 32 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a0027 - urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>UW g126<0,1,0>UD 0x040a02fd - data MsgDesc: ( DC OWORD block write, 253, 2) mlen 2 rlen 0 { align1 1Q }; -send(8) g115<1>UW g115<0,1,0>UD 0x021802fd - data MsgDesc: ( DC OWORD block read, 253, 2) mlen 1 rlen 1 { align1 WE_all 1Q }; -send(8) null<1>F g25<8,8,1>F 0x12080057 - urb MsgDesc: 5 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>F 0x12080077 - urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g43<8,8,1>F 0x12080097 - urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g52<8,8,1>F 0x120800b7 - urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g61<8,8,1>F 0x120800d7 - urb MsgDesc: 13 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g70<8,8,1>F 0x120800f7 - urb MsgDesc: 15 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>F 0x12080117 - urb MsgDesc: 17 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>F 0x12080137 - urb MsgDesc: 19 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g2<8,8,1>F 0x12080157 - urb MsgDesc: 21 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g79<8,8,1>F 0x12080177 - urb MsgDesc: 23 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g88<8,8,1>F 0x12080197 - urb MsgDesc: 25 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g97<8,8,1>F 0x120801b7 - urb MsgDesc: 27 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g106<8,8,1>F 0x120801d7 - urb MsgDesc: 29 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g117<8,8,1>F 0x920801f7 - urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g124<1>UW g11<8,8,1>UD 0x02229001 - sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1Q }; -send(16) g120<1>UW g11<8,8,1>UD 0x04449001 - sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1H }; -send(8) g124<1>UW g3<8,8,1>UD 0x08427000 - sampler MsgDesc: ld SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(16) null<1>UW g40<8,8,1>UD 0x04008501 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(8) null<1>F g127<8,8,1>UD 0x82080007 - urb MsgDesc: 0 SIMD8 write mlen 1 rlen 0 { align1 1Q EOT }; -send(8) g124<1>UW g9<8,8,1>UD 0x0a4a8000 - sampler MsgDesc: gather4 SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(8) g2<1>UW g23<8,8,1>UD 0x0633a001 - sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; -send(16) g4<1>UW g12<8,8,1>UD 0x0c65a001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; -send(8) g2<1>UW g16<8,8,1>UD 0x0e434001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 2Q }; -(+f1.0) send(8) null<1>UW g4<8,8,1>UD 0x02009501 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, inc) mlen 1 rlen 0 { align1 1Q }; -send(8) g6<1>UW g9<8,8,1>UD 0x08434001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) null<1>F g102<8,8,1>F 0x120801f7 - urb MsgDesc: 31 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g121<8,8,1>F 0x8a080217 - urb MsgDesc: 33 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(16) null<1>UW g3<0,1,0>UD 0x02008004 - gateway MsgDesc: (barrier msg) mlen 1 rlen 0 { align1 WE_all 1H }; -send(16) g3<1>UW g14<8,8,1>UD 0x04205efe - dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(8) null<1>F g30<8,8,1>F 0x140a0027 - urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>F 0x0c0a0047 - urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g126<8,8,1>UD 0x84080007 - urb MsgDesc: 0 SIMD8 write mlen 2 rlen 0 { align1 1Q EOT }; -send(8) g5<1>UW g11<8,8,1>UD 0x04415001 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g3<8,8,1>UD 0x04416001 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q }; -send(8) g13<1>UD g3<8,8,1>UD 0x02480038 - urb MsgDesc: 3 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g7<8,8,1>F 0x140a0037 - urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) g15<1>UD g2<8,8,1>UD 0x02280038 - urb MsgDesc: 3 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080037 - urb MsgDesc: 3 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g8<8,8,1>F 0x140a0007 - urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0007 - urb MsgDesc: 0 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; -send(8) g124<1>UW g12<8,8,1>UD a0<0,1,0>UD 0x00000200 - sampler MsgDesc: indirect { align1 1Q }; -send(8) g10<1>UD g2<8,8,1>UD 0x02480048 - urb MsgDesc: 4 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g6<1>UD g2<8,8,1>UD 0x02480088 - urb MsgDesc: 8 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g14<1>UD g2<8,8,1>UD 0x02480058 - urb MsgDesc: 5 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g11<1>UD g2<8,8,1>UD 0x024800a8 - urb MsgDesc: 10 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g18<1>UD g2<8,8,1>UD 0x02480068 - urb MsgDesc: 6 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g16<1>UD g2<8,8,1>UD 0x023800c8 - urb MsgDesc: 12 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g2<8,8,1>UD 0x02480078 - urb MsgDesc: 7 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x024800b8 - urb MsgDesc: 11 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g7<1>UD g2<8,8,1>UD 0x02480098 - urb MsgDesc: 9 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x920800b7 - urb MsgDesc: 11 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g6<1>UW g8<8,8,1>UD 0x084b0000 - sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) g7<1>UW g0<8,8,1>UD 0x02200008 - pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 2 { align1 1Q }; -send(16) g9<1>UW g0<8,8,1>UD 0x02410008 - pixel interp MsgDesc: (persp, per_message_offset, 0x08) mlen 1 rlen 4 { align1 1H }; -send(8) g2<1>UW g11<8,8,1>UD 0x0443d001 - sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g9<8,8,1>UD 0x0843e001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(16) g2<1>UW g15<8,8,1>UD 0x0885d001 - sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(16) g43<1>UW g11<8,8,1>UD 0x1085e001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; -send(8) g2<1>UW g6<8,8,1>UD 0x0a4b1000 - sampler MsgDesc: gather4_po SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(8) g74<1>UD g2<8,8,1>UD 0x02280028 - urb MsgDesc: 2 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g7<1>UD g2<8,8,1>UD 0x02380028 - urb MsgDesc: 2 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g15<1>UD g2<8,8,1>UD 0x02380038 - urb MsgDesc: 3 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g124<1>UW g3<8,8,1>UD 0x0843e000 - sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) g2<1>UW g3<8,8,1>UD 0x0443d000 - sampler MsgDesc: ld_mcs SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g19<8,8,1>UD 0x0a4a8001 - sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(16) g7<1>UW g16<8,8,1>UD 0x128c8001 - sampler MsgDesc: gather4 SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H }; -send(8) null<1>F g2<8,8,1>F 0x0c0a0057 - urb MsgDesc: 5 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g9<8,8,1>UD 0x04080027 - urb MsgDesc: 2 SIMD8 write mlen 2 rlen 0 { align1 1Q }; -send(8) g6<1>UW g7<8,8,1>UD 0x08134001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(8) g7<1>UW g11<8,8,1>UD 0x08134102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; -send(8) g13<1>UW g17<8,8,1>UD 0x021ab000 - sampler MsgDesc: sampleinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g50<8,8,1>F 0x140a0057 - urb MsgDesc: 5 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g60<8,8,1>F 0x140a0077 - urb MsgDesc: 7 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g70<8,8,1>F 0x0c0a0097 - urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0097 - urb MsgDesc: 9 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g124<1>UW g6<8,8,1>UD 0x0a4b0000 - sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(8) g5<1>UW g6<8,8,1>UD 0x061a3001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; -send(8) g6<1>UW g9<8,8,1>UD 0x061a3102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; -send(16) g9<1>UW g11<8,8,1>UD 0x0a2c3001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 2 { align1 1H }; -send(16) g11<1>UW g2<8,8,1>UD 0x0a2c3102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 2 { align1 1H }; -send(8) null<1>F g123<8,8,1>F 0x8a080077 - urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a0067 - urb MsgDesc: 6 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a0077 - urb MsgDesc: 7 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g42<8,8,1>UD 0x0c0a0087 - urb MsgDesc: 8 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x06420102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; -send(16) g10<1>UW g18<8,8,1>UD 0x0c840102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; -send(8) g2<1>UW g2<8,8,1>UD 0x04420102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x06420304 - sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; -send(16) g2<1>UW g10<8,8,1>UD 0x08840102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H }; -send(16) g10<1>UW g18<8,8,1>UD 0x0c840304 - sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 6 rlen 8 { align1 1H }; -send(8) g2<1>UW g2<8,8,1>UD 0x04420304 - sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x06420708 - sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 3 rlen 4 { align1 1Q }; -send(16) g2<1>UW g10<8,8,1>UD 0x08840304 - sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 8 { align1 1H }; -send(16) g10<1>UW g18<8,8,1>UD 0x0c840708 - sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 6 rlen 8 { align1 1H }; -send(8) g3<1>UW g11<8,8,1>UD 0x0a43c001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(16) g16<1>UW g5<8,8,1>UD 0x1485c001 - sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 8 { align1 1H }; -send(16) g4<1>UD g13<0,1,0>UD 0x02280301 - const MsgDesc: (1, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; -send(8) g2<1>UW g2<8,8,1>UD 0x0443a001 - sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(16) g2<1>UW g10<8,8,1>UD 0x0885a001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(8) g12<1>UW g12<8,8,1>UD 0x06125001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; -send(8) g13<1>UW g15<8,8,1>UD 0x06125102 - sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; -send(16) g20<1>UW g22<8,8,1>UD 0x0c245001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; -send(16) g22<1>UW g28<8,8,1>UD 0x0c245102 - sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H }; -send(8) g38<1>UD g2<8,8,1>UD 0x024800c8 - urb MsgDesc: 12 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g39<1>UD g2<8,8,1>UD 0x024800d8 - urb MsgDesc: 13 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g40<1>UD g2<8,8,1>UD 0x024800e8 - urb MsgDesc: 14 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g41<1>UD g2<8,8,1>UD 0x024800f8 - urb MsgDesc: 15 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g42<1>UD g2<8,8,1>UD 0x02480108 - urb MsgDesc: 16 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g43<1>UD g2<8,8,1>UD 0x02480118 - urb MsgDesc: 17 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g44<1>UD g2<8,8,1>UD 0x02480128 - urb MsgDesc: 18 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g45<1>UD g2<8,8,1>UD 0x02480138 - urb MsgDesc: 19 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g46<1>UD g2<8,8,1>UD 0x02480148 - urb MsgDesc: 20 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g47<1>UD g2<8,8,1>UD 0x02480158 - urb MsgDesc: 21 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g48<1>UD g2<8,8,1>UD 0x02480168 - urb MsgDesc: 22 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g49<1>UD g2<8,8,1>UD 0x02480178 - urb MsgDesc: 23 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g50<1>UD g2<8,8,1>UD 0x02480188 - urb MsgDesc: 24 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g51<1>UD g2<8,8,1>UD 0x02480198 - urb MsgDesc: 25 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g52<1>UD g2<8,8,1>UD 0x024801a8 - urb MsgDesc: 26 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g53<1>UD g2<8,8,1>UD 0x024801b8 - urb MsgDesc: 27 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g54<1>UD g2<8,8,1>UD 0x024801c8 - urb MsgDesc: 28 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g55<1>UD g2<8,8,1>UD 0x024801d8 - urb MsgDesc: 29 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g56<1>UD g2<8,8,1>UD 0x024801e8 - urb MsgDesc: 30 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g57<1>UD g2<8,8,1>UD 0x024801f8 - urb MsgDesc: 31 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080a8027 - urb MsgDesc: 2 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0a0a8027 - urb MsgDesc: 2 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) g6<1>UW g11<8,8,1>UD 0x0e424001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; -send(8) g124<1>UW g7<8,8,1>UD 0x0212a000 - sampler MsgDesc: resinfo SIMD8 Surface = 0 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; -send(8) g8<1>UD g14<8,8,1>UD 0x044a0128 - urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g22<1>UD g16<8,8,1>UD 0x044a0028 - urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x0a080017 - urb MsgDesc: 1 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g7<8,8,1>F 0x0a080057 - urb MsgDesc: 5 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) g4<1>UW g2<8,8,1>UD 0x02406001 - dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; -send(16) g5<1>UW g2<8,8,1>UD 0x04805001 - dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 2 rlen 8 { align1 1H }; -send(8) g124<1>UW g13<8,8,1>UD 0x084b0001 - sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(16) g120<1>UW g7<8,8,1>UD 0x0e8d0001 - sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 8 { align1 1H }; -send(8) g10<1>UW g10<8,8,1>UD 0x0e134001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 1 { align1 1Q }; -send(8) g11<1>UW g17<8,8,1>UD 0x0e134102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 1 { align1 1Q }; -send(8) g14<1>UW g10<8,8,1>UD 0x064a8202 - sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x084a8101 - sampler MsgDesc: gather4 SIMD8 Surface = 1 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; -send(8) g5<1>UW g6<8,8,1>UD 0x021ab001 - sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; -send(16) g6<1>UW g3<8,8,1>UD 0x022cb001 - sampler MsgDesc: sampleinfo SIMD16 Surface = 1 Sampler = 0 mlen 1 rlen 2 { align1 1H }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0037 - urb MsgDesc: 3 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g10<8,8,1>F 0x12080027 - urb MsgDesc: 2 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080047 - urb MsgDesc: 4 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g14<1>UW g2<8,8,1>UD 0x04438000 - sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g61<1>UD g107<8,8,1>UD 0x02380048 - urb MsgDesc: 4 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g64<1>UD g113<8,8,1>UD 0x02380058 - urb MsgDesc: 5 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080047 - urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g5<1>UW g4<8,8,1>UD 0x06415001 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x06416001 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 3 rlen 4 { align1 2Q }; -send(8) null<1>F g119<8,8,1>F 0x92080077 - urb MsgDesc: 7 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g12<1>UD g8<4,4,1>UD 0x044a0038 - urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g21<1>UD g8<4,4,1>UD 0x044a0048 - urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a00a7 - urb MsgDesc: 10 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(16) g1<1>UW g9<8,8,1>UD 0x08858001 - sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(8) null<1>F g56<8,8,1>F 0x140a0097 - urb MsgDesc: 9 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g76<8,8,1>F 0x0c0a00b7 - urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a00b7 - urb MsgDesc: 11 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g4<1>UW g3<8,8,1>UD 0x0232a001 - sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 3 { align1 1Q }; -send(16) g8<1>UW g3<8,8,1>UD 0x0464a001 - sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 6 { align1 1H }; -send(8) null<1>F g6<8,8,1>UD 0x0a080007 - urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) g126<1>UW g10<8,8,1>UD 0x08123001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(16) g124<1>UW g8<8,8,1>UD 0x10243001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; -send(8) g12<1>UW g12<8,8,1>UD 0x06126001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; -send(8) g13<1>UW g15<8,8,1>UD 0x06126102 - sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; -send(16) g20<1>UW g22<8,8,1>UD 0x0c246001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; -send(16) g22<1>UW g28<8,8,1>UD 0x0c246102 - sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H }; -send(8) g4<1>UW g0<8,8,1>UD 0x02201000 - pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 2 { align1 1Q }; -send(16) g6<1>UW g0<8,8,1>UD 0x02411000 - pixel interp MsgDesc: (persp, sample_position, 0x00) mlen 1 rlen 4 { align1 1H }; -send(8) g124<1>UW g19<8,8,1>UD 0x0a4b0001 - sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(16) g120<1>UW g7<8,8,1>UD 0x128d0001 - sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 8 { align1 1H }; -send(8) g2<1>UW g15<8,8,1>UD 0x06422001 - sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) g14<1>UW g8<8,8,1>UD 0x0c842001 - sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(8) null<1>F g118<8,8,1>F 0x940a0037 - urb MsgDesc: 3 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; -send(8) g4<1>UW g5<8,8,1>UD 0x0212a001 - sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 1 { align1 1Q }; -send(16) g4<1>UW g6<8,8,1>UD 0x0424a001 - sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1H }; -send(8) g8<1>UD g15<8,8,1>UD 0x042a0138 - urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g10<1>UD g15<8,8,1>UD 0x042a0338 - urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g12<1>UD g15<8,8,1>UD 0x042a0538 - urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g14<1>UD g15<8,8,1>UD 0x042a0738 - urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g8<1>UD g15<8,8,1>UD 0x042a0038 - urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g10<1>UD g15<8,8,1>UD 0x042a0238 - urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g12<1>UD g15<8,8,1>UD 0x042a0438 - urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g14<1>UD g15<8,8,1>UD 0x042a0638 - urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g35<8,8,1>UD 0x02480228 - urb MsgDesc: 34 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g35<8,8,1>UD 0x02480428 - urb MsgDesc: 66 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g35<8,8,1>UD 0x02480628 - urb MsgDesc: 98 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0a0a8037 - urb MsgDesc: 3 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0a0a8047 - urb MsgDesc: 4 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0a0a8057 - urb MsgDesc: 5 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0a0a8067 - urb MsgDesc: 6 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0a0a8077 - urb MsgDesc: 7 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0a0a8087 - urb MsgDesc: 8 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a0a8097 - urb MsgDesc: 9 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a0a80a7 - urb MsgDesc: 10 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a0a80b7 - urb MsgDesc: 11 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a0a80c7 - urb MsgDesc: 12 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0a80d7 - urb MsgDesc: 13 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0a80e7 - urb MsgDesc: 14 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0a80f7 - urb MsgDesc: 15 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0a8107 - urb MsgDesc: 16 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0a8117 - urb MsgDesc: 17 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0a8127 - urb MsgDesc: 18 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a0a8137 - urb MsgDesc: 19 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a0a8147 - urb MsgDesc: 20 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a0a8157 - urb MsgDesc: 21 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a0a8167 - urb MsgDesc: 22 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a0a8177 - urb MsgDesc: 23 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a0a8187 - urb MsgDesc: 24 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a0a8197 - urb MsgDesc: 25 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a0a81a7 - urb MsgDesc: 26 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a0a81b7 - urb MsgDesc: 27 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a0a81c7 - urb MsgDesc: 28 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0a81d7 - urb MsgDesc: 29 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0a81e7 - urb MsgDesc: 30 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0a81f7 - urb MsgDesc: 31 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0a8207 - urb MsgDesc: 32 SIMD8 write per-slot masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0027 - urb MsgDesc: 2 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g124<1>UW g2<8,8,1>UD 0x06424001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g124<1>UW g2<8,8,1>UD 0x06229001 - sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; -send(16) g120<1>UW g12<8,8,1>UD 0x0c449001 - sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; -send(8) g5<1>UW g19<8,8,1>UD 0x0443a102 - sampler MsgDesc: ld_lz SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; -send(16) g15<1>UW g11<8,8,1>UD 0x0885a102 - sampler MsgDesc: ld_lz SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H }; -send(8) g124<1>UW g12<8,8,1>UD 0x0a43c000 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(8) g4<1>UW g5<8,8,1>UD 0x04120001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; -send(16) g4<1>UW g7<8,8,1>UD 0x08240001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; -send(8) null<1>F g118<8,8,1>F 0x940a0027 - urb MsgDesc: 2 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g2<8,8,1>F 0x12080067 - urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080087 - urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g21<1>UD g2<8,8,1>UD 0x02380068 - urb MsgDesc: 6 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g35<1>UD g2<8,8,1>UD 0x02380088 - urb MsgDesc: 8 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g5<8,8,1>F 0x140a0067 - urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0067 - urb MsgDesc: 6 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; -send(8) g2<1>UW g8<8,8,1>UD 0x04220001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 2 { align1 1Q }; -send(16) g2<1>UW g14<8,8,1>UD 0x08440001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1H }; -send(8) null<1>F g123<8,8,1>F 0x8a0800d7 - urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g22<1>UW g14<8,8,1>UD 0x064a8405 - sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 3 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x084a8102 - sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; -send(8) g14<1>UW g10<8,8,1>UD 0x084a8203 - sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; -send(8) g18<1>UW g26<8,8,1>UD 0x0a4a8304 - sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 5 rlen 4 { align1 1Q }; -send(16) g18<1>UW g43<8,8,1>UD 0x0a8c8405 - sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 5 rlen 8 { align1 1H }; -send(16) g43<1>UW g7<8,8,1>UD 0x0e8c8102 - sampler MsgDesc: gather4 SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 8 { align1 1H }; -send(16) g2<1>UW g51<8,8,1>UD 0x0e8c8203 - sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 7 rlen 8 { align1 1H }; -send(16) g10<1>UW g26<8,8,1>UD 0x128c8304 - sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 9 rlen 8 { align1 1H }; -send(8) g6<1>UW g15<8,8,1>UD 0x0e4a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; -send(16) null<1>UW g2<8,8,1>UD 0x04008601 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 0 { align1 1H }; -send(8) g124<1>UW g2<8,8,1>UD 0x08422001 - sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(16) g120<1>UW g2<8,8,1>UD 0x10842001 - sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; -send(8) g6<1>UW g7<8,8,1>UD 0x08126001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(8) g7<1>UW g11<8,8,1>UD 0x08126102 - sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; -send(16) g10<1>UW g12<8,8,1>UD 0x10246001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; -send(16) g12<1>UW g20<8,8,1>UD 0x10246102 - sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H }; -send(8) null<1>F g18<8,8,1>UD 0x0e0a8047 - urb MsgDesc: 4 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; -send(8) g9<1>UD g34<8,8,1>UD 0x02480218 - urb MsgDesc: 33 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g17<1>UD g34<8,8,1>UD 0x02480238 - urb MsgDesc: 35 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g2<1>UD g6<8,8,1>UD 0x041a0128 - urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g22<1>UD g8<8,8,1>UD 0x041a0028 - urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) null<1>F g2<8,8,1>UD 0x06088027 - urb MsgDesc: 2 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x06088037 - urb MsgDesc: 3 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x06088047 - urb MsgDesc: 4 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x06088057 - urb MsgDesc: 5 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x06088067 - urb MsgDesc: 6 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x06088077 - urb MsgDesc: 7 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x06088087 - urb MsgDesc: 8 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x06088097 - urb MsgDesc: 9 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x060880a7 - urb MsgDesc: 10 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x060880b7 - urb MsgDesc: 11 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x060880c7 - urb MsgDesc: 12 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x060880d7 - urb MsgDesc: 13 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x060880e7 - urb MsgDesc: 14 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x060880f7 - urb MsgDesc: 15 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x06088107 - urb MsgDesc: 16 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x06088117 - urb MsgDesc: 17 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x06088127 - urb MsgDesc: 18 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x06088137 - urb MsgDesc: 19 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x06088147 - urb MsgDesc: 20 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x06088157 - urb MsgDesc: 21 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x06088167 - urb MsgDesc: 22 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x06088177 - urb MsgDesc: 23 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x06088187 - urb MsgDesc: 24 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x06088197 - urb MsgDesc: 25 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x060881a7 - urb MsgDesc: 26 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x060881b7 - urb MsgDesc: 27 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x060881c7 - urb MsgDesc: 28 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x060881d7 - urb MsgDesc: 29 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x060881e7 - urb MsgDesc: 30 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x060881f7 - urb MsgDesc: 31 SIMD8 write masked mlen 3 rlen 0 { align1 1Q }; -send(8) g3<1>UW g10<8,8,1>UD 0x0242a001 - sampler MsgDesc: resinfo SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(16) g3<1>UW g11<8,8,1>UD 0x0484a001 - sampler MsgDesc: resinfo SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; -send(8) g124<1>UW g6<8,8,1>UD 0x06320001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; -send(16) g120<1>UW g8<8,8,1>UD 0x0c640001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; -send(8) g124<1>UW g2<8,8,1>UD 0x02406000 - dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; -send(8) g127<1>UW g6<8,8,1>UD 0x06120001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; -send(16) g126<1>UW g8<8,8,1>UD 0x0c240001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; -send(8) g23<1>UW g2<8,8,1>UD 0x04115e01 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q }; -send(8) g39<1>UW g45<8,8,1>UD 0x04116e01 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 2 rlen 1 { align1 2Q }; -(+f1.0) send(8) null<1>UW g2<8,8,1>UD 0x04018501 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 2 rlen 0 { align1 1Q }; -(+f1.0) send(8) null<1>UW g42<8,8,1>UD 0x04019501 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 2 rlen 0 { align1 2Q }; -send(8) g2<1>UW g6<8,8,1>UD 0x04423001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g6<1>UW g8<8,8,1>UD 0x04423102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; -send(16) g2<1>UW g10<8,8,1>UD 0x08843001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(16) g10<1>UW g18<8,8,1>UD 0x08843102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 8 { align1 1H }; -send(8) g6<1>UD g22<8,8,1>UD 0x044a0318 - urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g10<1>UD g22<8,8,1>UD 0x044a0518 - urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g14<1>UD g22<8,8,1>UD 0x044a0718 - urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g18<1>UD g22<8,8,1>UD 0x044a0918 - urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g13<1>UD g29<8,8,1>UD 0x044a0218 - urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g17<1>UD g29<8,8,1>UD 0x044a0418 - urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g21<1>UD g29<8,8,1>UD 0x044a0618 - urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g25<1>UD g29<8,8,1>UD 0x044a0818 - urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c0a0217 - urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a0227 - urb MsgDesc: 34 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0c0a0237 - urb MsgDesc: 35 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a0247 - urb MsgDesc: 36 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a0257 - urb MsgDesc: 37 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a0267 - urb MsgDesc: 38 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0c0a0277 - urb MsgDesc: 39 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0c0a0287 - urb MsgDesc: 40 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0c0a0297 - urb MsgDesc: 41 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a02a7 - urb MsgDesc: 42 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a02b7 - urb MsgDesc: 43 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a02c7 - urb MsgDesc: 44 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a02d7 - urb MsgDesc: 45 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a02e7 - urb MsgDesc: 46 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a02f7 - urb MsgDesc: 47 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0c0a0307 - urb MsgDesc: 48 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a0317 - urb MsgDesc: 49 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a0327 - urb MsgDesc: 50 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a0337 - urb MsgDesc: 51 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a0347 - urb MsgDesc: 52 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a0357 - urb MsgDesc: 53 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a0367 - urb MsgDesc: 54 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0c0a0377 - urb MsgDesc: 55 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a0387 - urb MsgDesc: 56 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a0397 - urb MsgDesc: 57 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a03a7 - urb MsgDesc: 58 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a03b7 - urb MsgDesc: 59 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a03c7 - urb MsgDesc: 60 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a03d7 - urb MsgDesc: 61 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0c0a03e7 - urb MsgDesc: 62 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0c0a03f7 - urb MsgDesc: 63 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a080067 - urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a080077 - urb MsgDesc: 7 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a080087 - urb MsgDesc: 8 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a080097 - urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0800a7 - urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0800b7 - urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0800c7 - urb MsgDesc: 12 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0800d7 - urb MsgDesc: 13 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0800e7 - urb MsgDesc: 14 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0800f7 - urb MsgDesc: 15 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a080107 - urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a080117 - urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a080127 - urb MsgDesc: 18 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a080137 - urb MsgDesc: 19 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a080147 - urb MsgDesc: 20 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a080157 - urb MsgDesc: 21 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a080167 - urb MsgDesc: 22 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a080177 - urb MsgDesc: 23 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a080187 - urb MsgDesc: 24 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a080197 - urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0801a7 - urb MsgDesc: 26 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0801b7 - urb MsgDesc: 27 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0801c7 - urb MsgDesc: 28 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0801d7 - urb MsgDesc: 29 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0a0801e7 - urb MsgDesc: 30 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0a0801f7 - urb MsgDesc: 31 SIMD8 write mlen 5 rlen 0 { align1 1Q }; -send(8) g13<1>UW g2<8,8,1>UD 0x06123001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 1 { align1 1Q }; -send(8) g14<1>UW g5<8,8,1>UD 0x06123102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 1 { align1 1Q }; -send(16) g22<1>UW g2<8,8,1>UD 0x0c243001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 2 { align1 1H }; -send(16) g24<1>UW g16<8,8,1>UD 0x0c243102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 2 { align1 1H }; -send(8) g5<1>UW g15<8,8,1>UD 0x04420203 - sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; -send(16) g7<1>UW g27<8,8,1>UD 0x08840203 - sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 8 { align1 1H }; -send(16) g4<1>UW g17<8,8,1>UD 0x0420a503 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g18<8,8,1>UD 0x04008504 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 4, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(16) g11<1>UW g19<8,8,1>UD 0x0420a602 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, dec) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g20<8,8,1>UD 0x04008505 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 5, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(16) g16<1>UW g21<8,8,1>UD 0x04205e01 - dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g22<8,8,1>UD 0x04008506 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 6, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(8) g26<1>UW g26<8,8,1>UD 0x0242a203 - sampler MsgDesc: resinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UW g30<8,8,1>UD 0x0242a304 - sampler MsgDesc: resinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 4 { align1 1Q }; -send(8) g34<1>UW g34<8,8,1>UD 0x0242a405 - sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 4 { align1 1Q }; -send(8) g38<1>UW g38<8,8,1>UD 0x0242a506 - sampler MsgDesc: resinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UW g25<8,8,1>UD 0x0242a102 - sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 4 { align1 1Q }; -send(8) g42<1>UW g42<8,8,1>UD 0x0242a607 - sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 6 mlen 1 rlen 4 { align1 1Q }; -send(8) g46<1>UW g46<8,8,1>UD 0x0242a708 - sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 7 mlen 1 rlen 4 { align1 1Q }; -send(8) g50<1>UW g50<8,8,1>UD 0x0242a809 - sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 8 mlen 1 rlen 4 { align1 1Q }; -send(8) g2<1>UW g54<8,8,1>UD 0x0242a90a - sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 9 mlen 1 rlen 4 { align1 1Q }; -send(8) g6<1>UW g55<8,8,1>UD 0x0242aa0b - sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 10 mlen 1 rlen 4 { align1 1Q }; -send(8) g10<1>UW g56<8,8,1>UD 0x0242ab0c - sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 11 mlen 1 rlen 4 { align1 1Q }; -send(8) g14<1>UW g57<8,8,1>UD 0x0242ac0d - sampler MsgDesc: resinfo SIMD8 Surface = 13 Sampler = 12 mlen 1 rlen 4 { align1 1Q }; -send(16) g10<1>UW g18<8,8,1>UD 0x0484a102 - sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 8 { align1 1H }; -send(16) g82<1>UW g110<8,8,1>UD 0x0484aa0b - sampler MsgDesc: resinfo SIMD16 Surface = 11 Sampler = 10 mlen 2 rlen 8 { align1 1H }; -send(16) g18<1>UW g26<8,8,1>UD 0x0484a203 - sampler MsgDesc: resinfo SIMD16 Surface = 3 Sampler = 2 mlen 2 rlen 8 { align1 1H }; -send(16) g90<1>UW g112<8,8,1>UD 0x0484ab0c - sampler MsgDesc: resinfo SIMD16 Surface = 12 Sampler = 11 mlen 2 rlen 8 { align1 1H }; -send(16) g98<1>UW g106<8,8,1>UD 0x0484ac0d - sampler MsgDesc: resinfo SIMD16 Surface = 13 Sampler = 12 mlen 2 rlen 8 { align1 1H }; -send(16) g26<1>UW g34<8,8,1>UD 0x0484a304 - sampler MsgDesc: resinfo SIMD16 Surface = 4 Sampler = 3 mlen 2 rlen 8 { align1 1H }; -send(16) g34<1>UW g42<8,8,1>UD 0x0484a405 - sampler MsgDesc: resinfo SIMD16 Surface = 5 Sampler = 4 mlen 2 rlen 8 { align1 1H }; -send(16) g42<1>UW g50<8,8,1>UD 0x0484a506 - sampler MsgDesc: resinfo SIMD16 Surface = 6 Sampler = 5 mlen 2 rlen 8 { align1 1H }; -send(16) g50<1>UW g58<8,8,1>UD 0x0484a607 - sampler MsgDesc: resinfo SIMD16 Surface = 7 Sampler = 6 mlen 2 rlen 8 { align1 1H }; -send(16) g58<1>UW g66<8,8,1>UD 0x0484a708 - sampler MsgDesc: resinfo SIMD16 Surface = 8 Sampler = 7 mlen 2 rlen 8 { align1 1H }; -send(16) g66<1>UW g74<8,8,1>UD 0x0484a809 - sampler MsgDesc: resinfo SIMD16 Surface = 9 Sampler = 8 mlen 2 rlen 8 { align1 1H }; -send(16) g74<1>UW g108<8,8,1>UD 0x0484a90a - sampler MsgDesc: resinfo SIMD16 Surface = 10 Sampler = 9 mlen 2 rlen 8 { align1 1H }; -send(16) null<1>UW g3<8,8,1>UD 0x040085fe - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(8) null<1>F g119<8,8,1>F 0x92080067 - urb MsgDesc: 6 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g6<1>UW g20<8,8,1>UD 0x12424001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 4 { align1 1Q }; -send(8) g17<1>UW g2<8,8,1>UD 0x0413a001 - sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; -send(16) g2<1>UW g7<8,8,1>UD 0x0825a001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; -send(8) g9<1>UW g17<8,8,1>UD 0x06422000 - sampler MsgDesc: sample_l SIMD8 Surface = 0 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) null<1>UW g123<0,1,0>UD 0x060a03fd - data MsgDesc: ( DC OWORD block write, 253, 3) mlen 3 rlen 0 { align1 1H }; -send(16) g114<1>UW g114<0,1,0>UD 0x022803fd - data MsgDesc: ( DC OWORD block read, 253, 3) mlen 1 rlen 2 { align1 WE_all 1H }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a0127 - urb MsgDesc: 18 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) g2<1>UW g11<8,8,1>UD 0x04420405 - sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g12<8,8,1>UD 0x04420506 - sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x04420607 - sampler MsgDesc: sample SIMD8 Surface = 7 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g14<8,8,1>UD 0x04420708 - sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g15<8,8,1>UD 0x04420809 - sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 8 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g16<8,8,1>UD 0x0442090a - sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 9 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g17<8,8,1>UD 0x04420a0b - sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 10 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g18<8,8,1>UD 0x04420b0c - sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 11 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g19<8,8,1>UD 0x04420c0d - sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g20<8,8,1>UD 0x04420d0e - sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 13 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g21<8,8,1>UD 0x04420e0f - sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 14 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g22<8,8,1>UD 0x04420f10 - sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0011 - sampler MsgDesc: sample SIMD8 Surface = 17 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a0112 - sampler MsgDesc: sample SIMD8 Surface = 18 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0213 - sampler MsgDesc: sample SIMD8 Surface = 19 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a0314 - sampler MsgDesc: sample SIMD8 Surface = 20 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0415 - sampler MsgDesc: sample SIMD8 Surface = 21 Sampler = 4 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a0516 - sampler MsgDesc: sample SIMD8 Surface = 22 Sampler = 5 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0617 - sampler MsgDesc: sample SIMD8 Surface = 23 Sampler = 6 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a0718 - sampler MsgDesc: sample SIMD8 Surface = 24 Sampler = 7 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0819 - sampler MsgDesc: sample SIMD8 Surface = 25 Sampler = 8 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a091a - sampler MsgDesc: sample SIMD8 Surface = 26 Sampler = 9 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0a1b - sampler MsgDesc: sample SIMD8 Surface = 27 Sampler = 10 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a0b1c - sampler MsgDesc: sample SIMD8 Surface = 28 Sampler = 11 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0c1d - sampler MsgDesc: sample SIMD8 Surface = 29 Sampler = 12 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a0d1e - sampler MsgDesc: sample SIMD8 Surface = 30 Sampler = 13 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g10<8,8,1>UD 0x064a0e1f - sampler MsgDesc: sample SIMD8 Surface = 31 Sampler = 14 mlen 3 rlen 4 { align1 1Q }; -send(8) g2<1>UW g13<8,8,1>UD 0x064a0f20 - sampler MsgDesc: sample SIMD8 Surface = 32 Sampler = 15 mlen 3 rlen 4 { align1 1Q }; -send(16) g2<1>UW g28<8,8,1>UD 0x08840405 - sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g29<8,8,1>UD 0x08840506 - sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g30<8,8,1>UD 0x08840607 - sampler MsgDesc: sample SIMD16 Surface = 7 Sampler = 6 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g31<8,8,1>UD 0x08840708 - sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 7 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g32<8,8,1>UD 0x08840809 - sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 8 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g33<8,8,1>UD 0x0884090a - sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 9 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g34<8,8,1>UD 0x08840a0b - sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 10 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g35<8,8,1>UD 0x08840b0c - sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 11 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g36<8,8,1>UD 0x08840c0d - sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 12 mlen 4 rlen 8 { align1 1H }; -send(16) g2<1>UW g37<8,8,1>UD 0x08840d0e - sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 13 mlen 4 rlen 8 { align1 1H }; -send(16) g7<1>UW g38<8,8,1>UD 0x08840e0f - sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 14 mlen 4 rlen 8 { align1 1H }; -send(16) g23<1>UW g39<8,8,1>UD 0x08840f10 - sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 4 rlen 8 { align1 1H }; -send(16) g17<1>UW g2<8,8,1>UD 0x0a8c0011 - sampler MsgDesc: sample SIMD16 Surface = 17 Sampler = 0 mlen 5 rlen 8 { align1 1H }; -send(16) g29<1>UW g7<8,8,1>UD 0x0a8c0112 - sampler MsgDesc: sample SIMD16 Surface = 18 Sampler = 1 mlen 5 rlen 8 { align1 1H }; -send(16) g27<1>UW g12<8,8,1>UD 0x0a8c0213 - sampler MsgDesc: sample SIMD16 Surface = 19 Sampler = 2 mlen 5 rlen 8 { align1 1H }; -send(16) g32<1>UW g17<8,8,1>UD 0x0a8c0314 - sampler MsgDesc: sample SIMD16 Surface = 20 Sampler = 3 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g22<8,8,1>UD 0x0a8c0415 - sampler MsgDesc: sample SIMD16 Surface = 21 Sampler = 4 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g27<8,8,1>UD 0x0a8c0516 - sampler MsgDesc: sample SIMD16 Surface = 22 Sampler = 5 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g32<8,8,1>UD 0x0a8c0617 - sampler MsgDesc: sample SIMD16 Surface = 23 Sampler = 6 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g37<8,8,1>UD 0x0a8c0718 - sampler MsgDesc: sample SIMD16 Surface = 24 Sampler = 7 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g42<8,8,1>UD 0x0a8c0819 - sampler MsgDesc: sample SIMD16 Surface = 25 Sampler = 8 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g47<8,8,1>UD 0x0a8c091a - sampler MsgDesc: sample SIMD16 Surface = 26 Sampler = 9 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g52<8,8,1>UD 0x0a8c0a1b - sampler MsgDesc: sample SIMD16 Surface = 27 Sampler = 10 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g57<8,8,1>UD 0x0a8c0b1c - sampler MsgDesc: sample SIMD16 Surface = 28 Sampler = 11 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g62<8,8,1>UD 0x0a8c0c1d - sampler MsgDesc: sample SIMD16 Surface = 29 Sampler = 12 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g67<8,8,1>UD 0x0a8c0d1e - sampler MsgDesc: sample SIMD16 Surface = 30 Sampler = 13 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g72<8,8,1>UD 0x0a8c0e1f - sampler MsgDesc: sample SIMD16 Surface = 31 Sampler = 14 mlen 5 rlen 8 { align1 1H }; -send(16) g2<1>UW g77<8,8,1>UD 0x0a8c0f20 - sampler MsgDesc: sample SIMD16 Surface = 32 Sampler = 15 mlen 5 rlen 8 { align1 1H }; -send(8) g124<1>UW g2<8,8,1>UD 0x02120102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; -send(8) g6<1>UW g3<8,8,1>UD 0x02220102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UW g4<8,8,1>UD 0x02320102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 3 { align1 1Q }; -send(16) g120<1>UW g2<8,8,1>UD 0x04240102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1H }; -send(16) g10<1>UW g4<8,8,1>UD 0x04440102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 4 { align1 1H }; -send(16) g14<1>UW g6<8,8,1>UD 0x04640102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 6 { align1 1H }; -send(8) null<1>F g8<8,8,1>UD 0x0c0a8027 - urb MsgDesc: 2 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>F 0x12080047 - urb MsgDesc: 4 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080087 - urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g5<1>UW g10<8,8,1>UD 0x06420001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) g7<1>UW g19<8,8,1>UD 0x0c840001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(8) g1<1>UW g125<8,8,1>UD 0x02106e02 - dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) g8<1>UW g22<8,8,1>UD 0x02106efe - dp data 1 MsgDesc: ( untyped surface read, Surface = 254, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080097 - urb MsgDesc: 9 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g29<1>UW g5<8,8,1>UD 0x0e4b2001 - sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; -send(8) g68<1>UW g72<8,8,1>UD 0x0212a102 - sampler MsgDesc: resinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; -send(8) g67<1>UW g5<8,8,1>UD 0x0a126001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(8) g69<1>UW g10<8,8,1>UD 0x0a126102 - sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; -send(16) g36<1>UW g40<8,8,1>UD 0x0424a102 - sampler MsgDesc: resinfo SIMD16 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1H }; -send(16) g2<1>UW g7<8,8,1>UD 0x14246001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; -send(16) g37<1>UW g17<8,8,1>UD 0x14246102 - sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H }; -send(8) g125<1>UW g5<8,8,1>UD 0x04220102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 2 { align1 1Q }; -send(16) g122<1>UW g7<8,8,1>UD 0x08440102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1H }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a8037 - urb MsgDesc: 3 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a8047 - urb MsgDesc: 4 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a8057 - urb MsgDesc: 5 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) g6<1>UW g7<8,8,1>UD 0x081a5001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(8) g7<1>UW g11<8,8,1>UD 0x081a5102 - sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; -send(16) g10<1>UW g12<8,8,1>UD 0x0e2c5001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H }; -send(16) g12<1>UW g19<8,8,1>UD 0x0e2c5102 - sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H }; -send(8) g5<1>UW g6<8,8,1>UD 0x081a3001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(8) g6<1>UW g10<8,8,1>UD 0x081a3102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; -send(16) g9<1>UW g11<8,8,1>UD 0x0e2c3001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H }; -send(16) g11<1>UW g18<8,8,1>UD 0x0e2c3102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H }; -send(8) g5<1>UW g7<8,8,1>UD 0x04320102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 3 { align1 1Q }; -send(16) g8<1>UW g14<8,8,1>UD 0x08640102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 6 { align1 1H }; -send(8) g19<1>UW g12<8,8,1>UD 0x04320003 - sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 3 { align1 1Q }; -send(16) g34<1>UW g41<8,8,1>UD 0x08640003 - sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 6 { align1 1H }; -send(8) g11<1>UW g2<8,8,1>UD 0x0443a008 - sampler MsgDesc: ld_lz SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g15<1>UW g2<8,8,1>UD 0x0443a109 - sampler MsgDesc: ld_lz SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; -send(8) g19<1>UW g2<8,8,1>UD 0x0443a20a - sampler MsgDesc: ld_lz SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; -send(8) g23<1>UW g2<8,8,1>UD 0x0443a30b - sampler MsgDesc: ld_lz SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; -send(8) g27<1>UW g2<8,8,1>UD 0x0443a40c - sampler MsgDesc: ld_lz SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; -send(8) g31<1>UW g2<8,8,1>UD 0x0443a50d - sampler MsgDesc: ld_lz SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; -send(8) g35<1>UW g2<8,8,1>UD 0x0443a60e - sampler MsgDesc: ld_lz SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; -send(8) g39<1>UW g2<8,8,1>UD 0x0443a70f - sampler MsgDesc: ld_lz SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; -send(16) g93<1>UW g2<8,8,1>UD 0x0885a008 - sampler MsgDesc: ld_lz SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(16) g27<1>UW g2<8,8,1>UD 0x0885a109 - sampler MsgDesc: ld_lz SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H }; -send(16) g37<1>UW g2<8,8,1>UD 0x0885a20a - sampler MsgDesc: ld_lz SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H }; -send(16) g47<1>UW g2<8,8,1>UD 0x0885a30b - sampler MsgDesc: ld_lz SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H }; -send(16) g57<1>UW g2<8,8,1>UD 0x0885a40c - sampler MsgDesc: ld_lz SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H }; -send(16) g67<1>UW g2<8,8,1>UD 0x0885a50d - sampler MsgDesc: ld_lz SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H }; -send(16) g85<1>UW g2<8,8,1>UD 0x0885a60e - sampler MsgDesc: ld_lz SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H }; -send(16) g77<1>UW g2<8,8,1>UD 0x0885a70f - sampler MsgDesc: ld_lz SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H }; -send(16) g83<1>UW g86<8,8,1>UD 0x04205e00 - dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(8) null<1>F g122<8,8,1>F 0x8c0a0047 - urb MsgDesc: 4 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g14<1>UW g11<8,8,1>UD 0x084b0202 - sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x0a4b0101 - sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; -send(8) null<1>F g3<8,8,1>F 0x12080087 - urb MsgDesc: 8 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a0800a7 - urb MsgDesc: 10 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g6<1>UW g7<8,8,1>UD 0x081a6001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(8) g7<1>UW g11<8,8,1>UD 0x081a6102 - sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; -send(16) g10<1>UW g12<8,8,1>UD 0x0e2c6001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 2 { align1 1H }; -send(16) g12<1>UW g19<8,8,1>UD 0x0e2c6102 - sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 7 rlen 2 { align1 1H }; -send(8) g31<1>UD g28<8,8,1>UD 0x02380238 - urb MsgDesc: 35 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g34<1>UD g28<8,8,1>UD 0x02380438 - urb MsgDesc: 67 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g37<1>UD g28<8,8,1>UD 0x02380638 - urb MsgDesc: 99 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g28<8,8,1>UD 0x02380248 - urb MsgDesc: 36 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g28<8,8,1>UD 0x02380448 - urb MsgDesc: 68 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g28<1>UD g28<8,8,1>UD 0x02380648 - urb MsgDesc: 100 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g29<8,8,1>UD 0x02380258 - urb MsgDesc: 37 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g29<8,8,1>UD 0x02380458 - urb MsgDesc: 69 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g28<1>UD g29<8,8,1>UD 0x02380658 - urb MsgDesc: 101 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g30<8,8,1>UD 0x02380268 - urb MsgDesc: 38 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g30<8,8,1>UD 0x02380468 - urb MsgDesc: 70 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g28<1>UD g30<8,8,1>UD 0x02380668 - urb MsgDesc: 102 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g31<8,8,1>UD 0x02380278 - urb MsgDesc: 39 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g31<8,8,1>UD 0x02380478 - urb MsgDesc: 71 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g28<1>UD g31<8,8,1>UD 0x02380678 - urb MsgDesc: 103 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g32<8,8,1>UD 0x02380488 - urb MsgDesc: 72 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g32<8,8,1>UD 0x02380288 - urb MsgDesc: 40 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g28<1>UD g32<8,8,1>UD 0x02380688 - urb MsgDesc: 104 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g33<8,8,1>UD 0x02380498 - urb MsgDesc: 73 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g33<8,8,1>UD 0x02380298 - urb MsgDesc: 41 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g28<1>UD g33<8,8,1>UD 0x02380698 - urb MsgDesc: 105 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g34<8,8,1>UD 0x023806a8 - urb MsgDesc: 106 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g34<8,8,1>UD 0x023802a8 - urb MsgDesc: 42 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g34<8,8,1>UD 0x023804a8 - urb MsgDesc: 74 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g35<8,8,1>UD 0x023802b8 - urb MsgDesc: 43 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g35<8,8,1>UD 0x023804b8 - urb MsgDesc: 75 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g35<8,8,1>UD 0x023806b8 - urb MsgDesc: 107 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g36<8,8,1>UD 0x023802c8 - urb MsgDesc: 44 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g36<8,8,1>UD 0x023804c8 - urb MsgDesc: 76 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g36<8,8,1>UD 0x023806c8 - urb MsgDesc: 108 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g37<8,8,1>UD 0x023802d8 - urb MsgDesc: 45 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g37<8,8,1>UD 0x023804d8 - urb MsgDesc: 77 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g37<8,8,1>UD 0x023806d8 - urb MsgDesc: 109 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g38<8,8,1>UD 0x023802e8 - urb MsgDesc: 46 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g38<8,8,1>UD 0x023804e8 - urb MsgDesc: 78 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g38<8,8,1>UD 0x023806e8 - urb MsgDesc: 110 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g39<8,8,1>UD 0x023802f8 - urb MsgDesc: 47 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g39<8,8,1>UD 0x023804f8 - urb MsgDesc: 79 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g25<1>UD g39<8,8,1>UD 0x023806f8 - urb MsgDesc: 111 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g40<8,8,1>UD 0x02380308 - urb MsgDesc: 48 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g40<8,8,1>UD 0x02380508 - urb MsgDesc: 80 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g40<8,8,1>UD 0x02380708 - urb MsgDesc: 112 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g41<8,8,1>UD 0x02380318 - urb MsgDesc: 49 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g41<8,8,1>UD 0x02380518 - urb MsgDesc: 81 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g41<8,8,1>UD 0x02380718 - urb MsgDesc: 113 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g3<8,8,1>UD 0x02380328 - urb MsgDesc: 50 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g3<8,8,1>UD 0x02380528 - urb MsgDesc: 82 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g3<8,8,1>UD 0x02380728 - urb MsgDesc: 114 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g43<8,8,1>UD 0x02380338 - urb MsgDesc: 51 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g43<8,8,1>UD 0x02380538 - urb MsgDesc: 83 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g43<8,8,1>UD 0x02380738 - urb MsgDesc: 115 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g44<8,8,1>UD 0x02380348 - urb MsgDesc: 52 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g44<8,8,1>UD 0x02380548 - urb MsgDesc: 84 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g44<8,8,1>UD 0x02380748 - urb MsgDesc: 116 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g45<8,8,1>UD 0x02380358 - urb MsgDesc: 53 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g45<8,8,1>UD 0x02380558 - urb MsgDesc: 85 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g22<1>UD g45<8,8,1>UD 0x02380758 - urb MsgDesc: 117 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g46<8,8,1>UD 0x02380368 - urb MsgDesc: 54 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g46<8,8,1>UD 0x02380568 - urb MsgDesc: 86 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g46<8,8,1>UD 0x02380768 - urb MsgDesc: 118 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g47<8,8,1>UD 0x02380378 - urb MsgDesc: 55 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g47<8,8,1>UD 0x02380578 - urb MsgDesc: 87 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g47<8,8,1>UD 0x02380778 - urb MsgDesc: 119 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g48<8,8,1>UD 0x02380388 - urb MsgDesc: 56 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g48<8,8,1>UD 0x02380588 - urb MsgDesc: 88 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g48<8,8,1>UD 0x02380788 - urb MsgDesc: 120 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g49<8,8,1>UD 0x02380398 - urb MsgDesc: 57 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g49<8,8,1>UD 0x02380598 - urb MsgDesc: 89 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g49<8,8,1>UD 0x02380798 - urb MsgDesc: 121 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g50<8,8,1>UD 0x023803a8 - urb MsgDesc: 58 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g50<8,8,1>UD 0x023805a8 - urb MsgDesc: 90 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g50<8,8,1>UD 0x023807a8 - urb MsgDesc: 122 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g54<8,8,1>UD 0x023803b8 - urb MsgDesc: 59 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g54<8,8,1>UD 0x023805b8 - urb MsgDesc: 91 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g54<8,8,1>UD 0x023807b8 - urb MsgDesc: 123 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g55<8,8,1>UD 0x023803c8 - urb MsgDesc: 60 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g55<8,8,1>UD 0x023805c8 - urb MsgDesc: 92 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g55<8,8,1>UD 0x023807c8 - urb MsgDesc: 124 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g56<8,8,1>UD 0x023803d8 - urb MsgDesc: 61 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g56<8,8,1>UD 0x023805d8 - urb MsgDesc: 93 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g56<8,8,1>UD 0x023807d8 - urb MsgDesc: 125 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g57<8,8,1>UD 0x023803e8 - urb MsgDesc: 62 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g57<8,8,1>UD 0x023805e8 - urb MsgDesc: 94 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g57<8,8,1>UD 0x023807e8 - urb MsgDesc: 126 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g58<8,8,1>UD 0x023803f8 - urb MsgDesc: 63 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g58<8,8,1>UD 0x023805f8 - urb MsgDesc: 95 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g58<8,8,1>UD 0x023807f8 - urb MsgDesc: 127 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g59<8,8,1>UD 0x02380208 - urb MsgDesc: 32 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g59<8,8,1>UD 0x02380408 - urb MsgDesc: 64 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g59<8,8,1>UD 0x02380608 - urb MsgDesc: 96 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g17<1>UD g59<8,8,1>UD 0x02380808 - urb MsgDesc: 128 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g8<1>UD g60<8,8,1>UD 0x02380218 - urb MsgDesc: 33 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g60<8,8,1>UD 0x02380418 - urb MsgDesc: 65 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UD g60<8,8,1>UD 0x02380618 - urb MsgDesc: 97 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g17<1>UD g60<8,8,1>UD 0x02380818 - urb MsgDesc: 129 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a8067 - urb MsgDesc: 6 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a8077 - urb MsgDesc: 7 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a8087 - urb MsgDesc: 8 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0c0a8097 - urb MsgDesc: 9 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0c0a80a7 - urb MsgDesc: 10 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0c0a80b7 - urb MsgDesc: 11 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a80c7 - urb MsgDesc: 12 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a80d7 - urb MsgDesc: 13 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a80e7 - urb MsgDesc: 14 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a80f7 - urb MsgDesc: 15 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a8107 - urb MsgDesc: 16 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a8117 - urb MsgDesc: 17 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0c0a8127 - urb MsgDesc: 18 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a8137 - urb MsgDesc: 19 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a8147 - urb MsgDesc: 20 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a8157 - urb MsgDesc: 21 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a8167 - urb MsgDesc: 22 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a8177 - urb MsgDesc: 23 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a8187 - urb MsgDesc: 24 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0c0a8197 - urb MsgDesc: 25 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a81a7 - urb MsgDesc: 26 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a81b7 - urb MsgDesc: 27 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a81c7 - urb MsgDesc: 28 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a81d7 - urb MsgDesc: 29 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a81e7 - urb MsgDesc: 30 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a81f7 - urb MsgDesc: 31 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0c0a8207 - urb MsgDesc: 32 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0c0a8217 - urb MsgDesc: 33 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) g124<1>UW g2<8,8,1>UD 0x02106e01 - dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(16) g11<1>UW g19<8,8,1>UD 0x0420a601 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, dec) mlen 2 rlen 2 { align1 1H }; -send(16) null<1>UW g20<8,8,1>UD 0x04008503 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 3, SIMD16, inc) mlen 2 rlen 0 { align1 1H }; -send(8) g17<1>UW g11<8,8,1>UD 0x0813e001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(16) g22<1>UW g2<8,8,1>UD 0x1025e001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; -send(8) null<1>F g122<8,8,1>UD 0x8c088007 - urb MsgDesc: 0 SIMD8 write masked mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g2<1>UW g2<8,8,1>UD 0x06423001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x06423102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; -send(16) g2<1>UW g20<8,8,1>UD 0x0c843001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(16) g10<1>UW g26<8,8,1>UD 0x0c843102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; -send(8) g14<1>UW g14<8,8,1>UD 0x0a1a5001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(8) g15<1>UW g19<8,8,1>UD 0x0a1a5102 - sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; -send(16) g39<1>UW g7<8,8,1>UD 0x122c5001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 2 { align1 1H }; -send(16) g41<1>UW g16<8,8,1>UD 0x122c5102 - sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 2 { align1 1H }; -send(8) g2<1>UW g13<8,8,1>UD 0x0c4b2001 - sampler MsgDesc: gather4_po_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(16) g43<1>UW g7<8,8,1>UD 0x168d2001 - sampler MsgDesc: gather4_po_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; -send(8) g54<1>UD g7<8,8,1>UD 0x02280048 - urb MsgDesc: 4 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g2<1>UW g8<8,8,1>UD 0x02420001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(16) g2<1>UW g15<8,8,1>UD 0x04840001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 2 rlen 8 { align1 1H }; -send(8) g7<1>UW g44<8,8,1>UD 0x02106e00 - dp data 1 MsgDesc: ( untyped surface read, Surface = 0, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>UW g44<8,8,1>UD 0x02009500 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 0 { align1 1Q }; -send(8) g7<1>UD g37<8,8,1>UD 0x02480438 - urb MsgDesc: 67 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g11<1>UD g37<8,8,1>UD 0x02480638 - urb MsgDesc: 99 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g13<1>UD g14<8,8,1>UD 0x042a0148 - urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g14<8,8,1>UD 0x042a0048 - urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g124<1>UW g13<8,8,1>UD 0x0c43c000 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(8) g22<1>UW g14<8,8,1>UD 0x064a8404 - sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 3 rlen 4 { align1 1Q }; -send(8) g14<1>UW g10<8,8,1>UD 0x084a8202 - sampler MsgDesc: gather4 SIMD8 Surface = 2 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; -send(8) g18<1>UW g26<8,8,1>UD 0x0a4a8303 - sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 5 rlen 4 { align1 1Q }; -send(8) g6<1>UW g14<8,8,1>UD 0x0e434102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 7 rlen 4 { align1 1Q }; -send(8) g8<1>UW g7<8,8,1>UD 0x121b4001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 9 rlen 1 { align1 1Q }; -send(8) g9<1>UW g16<8,8,1>UD 0x121b4102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 9 rlen 1 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x02380078 - urb MsgDesc: 7 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g14<1>UW g10<8,8,1>UD 0x064a8203 - sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; -send(16) g26<1>UW g34<8,8,1>UD 0x0a8c8203 - sampler MsgDesc: gather4 SIMD16 Surface = 3 Sampler = 2 mlen 5 rlen 8 { align1 1H }; -send(8) g50<1>UD g51<8,8,1>UD 0x02180018 - urb MsgDesc: 1 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g59<1>UW g64<8,8,1>UD 0x02427002 - sampler MsgDesc: ld SIMD8 Surface = 2 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g2<1>UW g64<8,8,1>UD 0x02427003 - sampler MsgDesc: ld SIMD8 Surface = 3 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g6<1>UW g64<8,8,1>UD 0x02427004 - sampler MsgDesc: ld SIMD8 Surface = 4 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g10<1>UW g64<8,8,1>UD 0x02427005 - sampler MsgDesc: ld SIMD8 Surface = 5 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g14<1>UW g64<8,8,1>UD 0x02427006 - sampler MsgDesc: ld SIMD8 Surface = 6 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g18<1>UW g64<8,8,1>UD 0x02427007 - sampler MsgDesc: ld SIMD8 Surface = 7 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UW g64<8,8,1>UD 0x02427008 - sampler MsgDesc: ld SIMD8 Surface = 8 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UW g64<8,8,1>UD 0x02427009 - sampler MsgDesc: ld SIMD8 Surface = 9 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UW g64<8,8,1>UD 0x0242700a - sampler MsgDesc: ld SIMD8 Surface = 10 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g34<1>UW g64<8,8,1>UD 0x0242700b - sampler MsgDesc: ld SIMD8 Surface = 11 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g38<1>UW g64<8,8,1>UD 0x0242700c - sampler MsgDesc: ld SIMD8 Surface = 12 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g42<1>UW g64<8,8,1>UD 0x0242700d - sampler MsgDesc: ld SIMD8 Surface = 13 Sampler = 0 mlen 1 rlen 4 { align1 1Q }; -send(8) g124<1>UW g6<8,8,1>UD 0x04438505 - sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0a088067 - urb MsgDesc: 6 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0a088077 - urb MsgDesc: 7 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0a088087 - urb MsgDesc: 8 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0a088097 - urb MsgDesc: 9 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0a0880a7 - urb MsgDesc: 10 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0a0880b7 - urb MsgDesc: 11 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0a0880c7 - urb MsgDesc: 12 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0a0880d7 - urb MsgDesc: 13 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0a0880e7 - urb MsgDesc: 14 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0a0880f7 - urb MsgDesc: 15 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0a088107 - urb MsgDesc: 16 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0a088117 - urb MsgDesc: 17 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0a088127 - urb MsgDesc: 18 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0a088137 - urb MsgDesc: 19 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0a088147 - urb MsgDesc: 20 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0a088157 - urb MsgDesc: 21 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0a088167 - urb MsgDesc: 22 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0a088177 - urb MsgDesc: 23 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0a088187 - urb MsgDesc: 24 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0a088197 - urb MsgDesc: 25 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0a0881a7 - urb MsgDesc: 26 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0a0881b7 - urb MsgDesc: 27 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0a0881c7 - urb MsgDesc: 28 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0a0881d7 - urb MsgDesc: 29 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0a0881e7 - urb MsgDesc: 30 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0a0881f7 - urb MsgDesc: 31 SIMD8 write masked mlen 5 rlen 0 { align1 1Q }; -send(8) null<1>F g4<8,8,1>UD 0x0e0a8027 - urb MsgDesc: 2 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; -send(8) g5<1>UW g6<8,8,1>UD 0x04123001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; -send(8) g6<1>UW g2<8,8,1>UD 0x04123102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 1 { align1 1Q }; -send(16) g9<1>UW g11<8,8,1>UD 0x08243001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; -send(16) g11<1>UW g2<8,8,1>UD 0x08243102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 2 { align1 1H }; -send(8) g2<1>UW g2<8,8,1>UD 0x0443d002 - sampler MsgDesc: ld_mcs SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g3<1>UW g14<8,8,1>UD 0x0a43c102 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; -send(16) g2<1>UW g10<8,8,1>UD 0x0885d002 - sampler MsgDesc: ld_mcs SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(16) g3<1>UW g25<8,8,1>UD 0x1485c102 - sampler MsgDesc: ld2dms_w SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 8 { align1 1H }; -send(8) g10<1>UW g11<8,8,1>UD 0x0a123001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(8) g11<1>UW g16<8,8,1>UD 0x0a123102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; -send(16) g34<1>UW g9<8,8,1>UD 0x14243001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; -send(16) g36<1>UW g19<8,8,1>UD 0x14243102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H }; -send(8) g2<1>UW g7<8,8,1>UD 0x08426001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) g6<1>UW g11<8,8,1>UD 0x08426102 - sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; -send(16) g2<1>UW g11<8,8,1>UD 0x10846001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; -send(16) g10<1>UW g19<8,8,1>UD 0x10846102 - sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H }; -(+f1.0) send(8) g4<1>UW g10<8,8,1>UD 0x0210b502 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, inc) mlen 1 rlen 1 { align1 1Q }; -(+f1.0) send(16) g5<1>UW g13<8,8,1>UD 0x0420a502 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, inc) mlen 2 rlen 2 { align1 1H }; -send(8) g8<1>UW g9<8,8,1>UD 0x06321001 - sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; -send(16) g2<1>UW g14<8,8,1>UD 0x0c641001 - sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; -send(8) g124<1>UW g6<8,8,1>UD 0x04338000 - sampler MsgDesc: sample_lz SIMD8 Surface = 0 Sampler = 0 mlen 2 rlen 3 { align1 1Q }; -send(8) g12<1>UD g1<8,8,1>UD 0x02280058 - urb MsgDesc: 5 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0e0a8067 - urb MsgDesc: 6 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; -send(8) g12<1>UD g1<8,8,1>UD 0x02280078 - urb MsgDesc: 7 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0e0a8087 - urb MsgDesc: 8 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; -send(8) g12<1>UD g1<8,8,1>UD 0x02280098 - urb MsgDesc: 9 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0e0a80a7 - urb MsgDesc: 10 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; -send(16) g9<1>UW g17<8,8,1>UD 0x04847002 - sampler MsgDesc: ld SIMD16 Surface = 2 Sampler = 0 mlen 2 rlen 8 { align1 1H }; -send(16) g23<1>UW g32<8,8,1>UD 0x04205e02 - dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280068 - urb MsgDesc: 6 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280088 - urb MsgDesc: 8 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022800a8 - urb MsgDesc: 10 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022800b8 - urb MsgDesc: 11 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022800c8 - urb MsgDesc: 12 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022800d8 - urb MsgDesc: 13 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022800e8 - urb MsgDesc: 14 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022800f8 - urb MsgDesc: 15 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280108 - urb MsgDesc: 16 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280118 - urb MsgDesc: 17 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280128 - urb MsgDesc: 18 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280138 - urb MsgDesc: 19 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280148 - urb MsgDesc: 20 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280158 - urb MsgDesc: 21 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280168 - urb MsgDesc: 22 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280178 - urb MsgDesc: 23 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280188 - urb MsgDesc: 24 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280198 - urb MsgDesc: 25 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022801a8 - urb MsgDesc: 26 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022801b8 - urb MsgDesc: 27 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022801c8 - urb MsgDesc: 28 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022801d8 - urb MsgDesc: 29 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022801e8 - urb MsgDesc: 30 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x022801f8 - urb MsgDesc: 31 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g1<8,8,1>UD 0x02280208 - urb MsgDesc: 32 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g2<1>UW g3<8,8,1>UD 0x04203000 - pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 2 rlen 2 { align1 1Q }; -send(16) g2<1>UW g11<8,8,1>UD 0x08413000 - pixel interp MsgDesc: (persp, per_slot_offset, 0x00) mlen 4 rlen 4 { align1 1H }; -send(8) g2<1>UW g0<8,8,1>UD 0x02201010 - pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 2 { align1 1Q }; -send(16) g2<1>UW g0<8,8,1>UD 0x02411010 - pixel interp MsgDesc: (persp, sample_position, 0x10) mlen 1 rlen 4 { align1 1H }; -send(8) g2<1>UW g0<8,8,1>UD 0x02201020 - pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 2 { align1 1Q }; -send(16) g2<1>UW g0<8,8,1>UD 0x02411020 - pixel interp MsgDesc: (persp, sample_position, 0x20) mlen 1 rlen 4 { align1 1H }; -send(8) g2<1>UW g0<8,8,1>UD 0x02201030 - pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 2 { align1 1Q }; -send(16) g2<1>UW g0<8,8,1>UD 0x02411030 - pixel interp MsgDesc: (persp, sample_position, 0x30) mlen 1 rlen 4 { align1 1H }; -send(8) g20<1>UW g15<8,8,1>UD 0x04320203 - sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 3 { align1 1Q }; -send(8) g11<1>UW g26<8,8,1>UD 0x04320405 - sampler MsgDesc: sample SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 3 { align1 1Q }; -send(8) g8<1>UW g24<8,8,1>UD 0x04320304 - sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 2 rlen 3 { align1 1Q }; -send(16) g26<1>UW g21<8,8,1>UD 0x08640203 - sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 6 { align1 1H }; -send(16) g12<1>UW g48<8,8,1>UD 0x08640405 - sampler MsgDesc: sample SIMD16 Surface = 5 Sampler = 4 mlen 4 rlen 6 { align1 1H }; -send(16) g38<1>UW g44<8,8,1>UD 0x08640304 - sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 4 rlen 6 { align1 1H }; -(+f1.0) send(8) null<1>UW g94<8,8,1>UD 0x02009601 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 0 { align1 1Q }; -(+f1.0) send(8) g47<1>UW g94<8,8,1>UD 0x0210b601 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, dec) mlen 1 rlen 1 { align1 1Q }; -send(16) g4<1>UW g1<8,8,1>UD 0x04405c02 - dp data 1 MsgDesc: ( untyped surface read, Surface = 2, SIMD16, Mask = 0xc) mlen 2 rlen 4 { align1 1H }; -send(8) null<1>UW g100<8,8,1>UD 0x02009600 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 0 { align1 1Q }; -send(8) g51<1>UW g100<8,8,1>UD 0x0210b600 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, dec) mlen 1 rlen 1 { align1 1Q }; -send(8) g5<1>UW g11<8,8,1>UD 0x064a0001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(16) g7<1>UW g19<8,8,1>UD 0x0a8c0001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 8 { align1 1H }; -send(8) null<1>F g123<8,8,1>F 0x8a080117 - urb MsgDesc: 17 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g3<1>UW g3<8,8,1>UD 0x02415002 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; -send(8) g5<1>UW g4<8,8,1>UD 0x02416002 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 2Q }; -send(8) g6<1>UW g16<8,8,1>UD 0x0210b500 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, inc) mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080097 - urb MsgDesc: 9 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g4<8,8,1>F 0x120800c7 - urb MsgDesc: 12 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g5<8,8,1>F 0x120800e7 - urb MsgDesc: 14 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080107 - urb MsgDesc: 16 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g6<1>UW g11<8,8,1>UD 0x08434102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; -send(8) g67<1>UW g36<8,8,1>UD 0x0823e000 - sampler MsgDesc: ld2dms SIMD8 Surface = 0 Sampler = 0 mlen 4 rlen 2 { align1 1Q }; -send(8) g2<1>UW g2<8,8,1>UD 0x0a23c000 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 0 Sampler = 0 mlen 5 rlen 2 { align1 1Q }; -send(8) g9<1>UW g15<8,8,1>UD 0x021ab101 - sampler MsgDesc: sampleinfo SIMD8 Surface = 1 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; -send(8) g10<1>UW g16<8,8,1>UD 0x021ab202 - sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 2 mlen 1 rlen 1 { align1 1Q }; -send(8) g11<1>UW g17<8,8,1>UD 0x021ab303 - sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 3 mlen 1 rlen 1 { align1 1Q }; -send(8) g12<1>UW g18<8,8,1>UD 0x021ab404 - sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 4 mlen 1 rlen 1 { align1 1Q }; -send(8) g13<1>UW g19<8,8,1>UD 0x021ab505 - sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 5 mlen 1 rlen 1 { align1 1Q }; -send(8) g14<1>UW g18<8,8,1>UD 0x08123102 - sampler MsgDesc: sample_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; -send(16) g24<1>UW g32<8,8,1>UD 0x10243102 - sampler MsgDesc: sample_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H }; -send(8) g5<1>UW g5<8,8,1>UD 0x04415000 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UD g9<8,8,1>UD 0x043a0028 - urb MsgDesc: 2 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x02380098 - urb MsgDesc: 9 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x023800a8 - urb MsgDesc: 10 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x023800b8 - urb MsgDesc: 11 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x023800d8 - urb MsgDesc: 13 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x023800e8 - urb MsgDesc: 14 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x023800f8 - urb MsgDesc: 15 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x02380108 - urb MsgDesc: 16 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g13<1>UD g1<8,8,1>UD 0x02380118 - urb MsgDesc: 17 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) null<1>F g60<8,8,1>F 0x120800a7 - urb MsgDesc: 10 SIMD8 write mlen 9 rlen 0 { align1 1Q }; -send(8) null<1>F g119<8,8,1>F 0x92080107 - urb MsgDesc: 16 SIMD8 write mlen 9 rlen 0 { align1 1Q EOT }; -send(8) g3<1>UW g7<8,8,1>UD 0x02115e01 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) g5<1>UW g11<8,8,1>UD 0x02116e01 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 2Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080067 - urb MsgDesc: 6 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g80<8,8,1>F 0x140a00b7 - urb MsgDesc: 11 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a00d7 - urb MsgDesc: 13 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a00f7 - urb MsgDesc: 15 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a0117 - urb MsgDesc: 17 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a0137 - urb MsgDesc: 19 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g90<8,8,1>F 0x140a0157 - urb MsgDesc: 21 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g100<8,8,1>F 0x140a0177 - urb MsgDesc: 23 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g110<8,8,1>F 0x0c0a0197 - urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g120<8,8,1>F 0x8c0a0197 - urb MsgDesc: 25 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) null<1>F g123<8,8,1>F 0x8a0800b7 - urb MsgDesc: 11 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g22<1>UD g53<8,8,1>UD 0x02180238 - urb MsgDesc: 35 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g54<1>UD g53<8,8,1>UD 0x02180438 - urb MsgDesc: 67 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g67<1>UD g53<8,8,1>UD 0x02180638 - urb MsgDesc: 99 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g61<1>UD g53<8,8,1>UD 0x02180248 - urb MsgDesc: 36 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g66<1>UD g53<8,8,1>UD 0x02180448 - urb MsgDesc: 68 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g63<1>UD g53<8,8,1>UD 0x02180648 - urb MsgDesc: 100 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g68<1>UD g65<8,8,1>UD 0x02180258 - urb MsgDesc: 37 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g69<1>UD g65<8,8,1>UD 0x02180458 - urb MsgDesc: 69 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g70<1>UD g65<8,8,1>UD 0x02180658 - urb MsgDesc: 101 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g75<1>UD g24<8,8,1>UD 0x02180268 - urb MsgDesc: 38 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g76<1>UD g24<8,8,1>UD 0x02180468 - urb MsgDesc: 70 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g77<1>UD g24<8,8,1>UD 0x02180668 - urb MsgDesc: 102 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g82<1>UD g25<8,8,1>UD 0x02180278 - urb MsgDesc: 39 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g83<1>UD g25<8,8,1>UD 0x02180478 - urb MsgDesc: 71 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g84<1>UD g25<8,8,1>UD 0x02180678 - urb MsgDesc: 103 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g89<1>UD g26<8,8,1>UD 0x02180288 - urb MsgDesc: 40 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g90<1>UD g26<8,8,1>UD 0x02180488 - urb MsgDesc: 72 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g91<1>UD g26<8,8,1>UD 0x02180688 - urb MsgDesc: 104 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g96<1>UD g27<8,8,1>UD 0x02180298 - urb MsgDesc: 41 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g97<1>UD g27<8,8,1>UD 0x02180498 - urb MsgDesc: 73 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g98<1>UD g27<8,8,1>UD 0x02180698 - urb MsgDesc: 105 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g103<1>UD g28<8,8,1>UD 0x021802a8 - urb MsgDesc: 42 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g104<1>UD g28<8,8,1>UD 0x021804a8 - urb MsgDesc: 74 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g105<1>UD g28<8,8,1>UD 0x021806a8 - urb MsgDesc: 106 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g110<1>UD g29<8,8,1>UD 0x021802b8 - urb MsgDesc: 43 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g111<1>UD g29<8,8,1>UD 0x021804b8 - urb MsgDesc: 75 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g112<1>UD g29<8,8,1>UD 0x021806b8 - urb MsgDesc: 107 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g117<1>UD g30<8,8,1>UD 0x021802c8 - urb MsgDesc: 44 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g118<1>UD g30<8,8,1>UD 0x021804c8 - urb MsgDesc: 76 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g119<1>UD g30<8,8,1>UD 0x021806c8 - urb MsgDesc: 108 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g124<1>UD g31<8,8,1>UD 0x021802d8 - urb MsgDesc: 45 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g125<1>UD g31<8,8,1>UD 0x021804d8 - urb MsgDesc: 77 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g126<1>UD g31<8,8,1>UD 0x021806d8 - urb MsgDesc: 109 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g10<1>UD g32<8,8,1>UD 0x021802e8 - urb MsgDesc: 46 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g11<1>UD g32<8,8,1>UD 0x021804e8 - urb MsgDesc: 78 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g12<1>UD g32<8,8,1>UD 0x021806e8 - urb MsgDesc: 110 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g26<1>UD g33<8,8,1>UD 0x021802f8 - urb MsgDesc: 47 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g27<1>UD g33<8,8,1>UD 0x021804f8 - urb MsgDesc: 79 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g28<1>UD g33<8,8,1>UD 0x021806f8 - urb MsgDesc: 111 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g33<1>UD g35<8,8,1>UD 0x02180308 - urb MsgDesc: 48 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g34<1>UD g35<8,8,1>UD 0x02180508 - urb MsgDesc: 80 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g35<1>UD g35<8,8,1>UD 0x02180708 - urb MsgDesc: 112 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g64<1>UD g36<8,8,1>UD 0x02180318 - urb MsgDesc: 49 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g41<1>UD g36<8,8,1>UD 0x02180518 - urb MsgDesc: 81 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g42<1>UD g36<8,8,1>UD 0x02180718 - urb MsgDesc: 113 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g6<1>UD g37<8,8,1>UD 0x02180328 - urb MsgDesc: 50 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g48<1>UD g37<8,8,1>UD 0x02180528 - urb MsgDesc: 82 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g49<1>UD g37<8,8,1>UD 0x02180728 - urb MsgDesc: 114 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g67<1>UD g38<8,8,1>UD 0x02180338 - urb MsgDesc: 51 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g56<1>UD g38<8,8,1>UD 0x02180538 - urb MsgDesc: 83 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g57<1>UD g38<8,8,1>UD 0x02180738 - urb MsgDesc: 115 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g66<1>UD g39<8,8,1>UD 0x02180348 - urb MsgDesc: 52 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g63<1>UD g39<8,8,1>UD 0x02180548 - urb MsgDesc: 84 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g40<1>UD g39<8,8,1>UD 0x02180748 - urb MsgDesc: 116 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g69<1>UD g64<8,8,1>UD 0x02180358 - urb MsgDesc: 53 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g70<1>UD g64<8,8,1>UD 0x02180558 - urb MsgDesc: 85 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g71<1>UD g64<8,8,1>UD 0x02180758 - urb MsgDesc: 117 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g76<1>UD g41<8,8,1>UD 0x02180368 - urb MsgDesc: 54 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g77<1>UD g41<8,8,1>UD 0x02180568 - urb MsgDesc: 86 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g78<1>UD g41<8,8,1>UD 0x02180768 - urb MsgDesc: 118 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g83<1>UD g42<8,8,1>UD 0x02180378 - urb MsgDesc: 55 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g84<1>UD g42<8,8,1>UD 0x02180578 - urb MsgDesc: 87 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g85<1>UD g42<8,8,1>UD 0x02180778 - urb MsgDesc: 119 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g90<1>UD g43<8,8,1>UD 0x02180388 - urb MsgDesc: 56 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g91<1>UD g43<8,8,1>UD 0x02180588 - urb MsgDesc: 88 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g92<1>UD g43<8,8,1>UD 0x02180788 - urb MsgDesc: 120 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g97<1>UD g44<8,8,1>UD 0x02180398 - urb MsgDesc: 57 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g98<1>UD g44<8,8,1>UD 0x02180598 - urb MsgDesc: 89 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g99<1>UD g44<8,8,1>UD 0x02180798 - urb MsgDesc: 121 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g104<1>UD g45<8,8,1>UD 0x021803a8 - urb MsgDesc: 58 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g105<1>UD g45<8,8,1>UD 0x021805a8 - urb MsgDesc: 90 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g106<1>UD g45<8,8,1>UD 0x021807a8 - urb MsgDesc: 122 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g111<1>UD g46<8,8,1>UD 0x021803b8 - urb MsgDesc: 59 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g112<1>UD g46<8,8,1>UD 0x021805b8 - urb MsgDesc: 91 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g113<1>UD g46<8,8,1>UD 0x021807b8 - urb MsgDesc: 123 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g118<1>UD g6<8,8,1>UD 0x021803c8 - urb MsgDesc: 60 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g119<1>UD g6<8,8,1>UD 0x021805c8 - urb MsgDesc: 92 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g120<1>UD g6<8,8,1>UD 0x021807c8 - urb MsgDesc: 124 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g125<1>UD g48<8,8,1>UD 0x021803d8 - urb MsgDesc: 61 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g126<1>UD g48<8,8,1>UD 0x021805d8 - urb MsgDesc: 93 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g2<1>UD g48<8,8,1>UD 0x021807d8 - urb MsgDesc: 125 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g12<1>UD g49<8,8,1>UD 0x021803e8 - urb MsgDesc: 62 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g13<1>UD g49<8,8,1>UD 0x021805e8 - urb MsgDesc: 94 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g14<1>UD g49<8,8,1>UD 0x021807e8 - urb MsgDesc: 126 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g19<1>UD g50<8,8,1>UD 0x021803f8 - urb MsgDesc: 63 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g20<1>UD g50<8,8,1>UD 0x021805f8 - urb MsgDesc: 95 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g53<1>UD g50<8,8,1>UD 0x021807f8 - urb MsgDesc: 127 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g28<1>UD g51<8,8,1>UD 0x02180408 - urb MsgDesc: 64 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g29<1>UD g51<8,8,1>UD 0x02180608 - urb MsgDesc: 96 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g30<1>UD g51<8,8,1>UD 0x02180808 - urb MsgDesc: 128 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g35<1>UD g22<8,8,1>UD 0x02180218 - urb MsgDesc: 33 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g36<1>UD g22<8,8,1>UD 0x02180418 - urb MsgDesc: 65 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g37<1>UD g22<8,8,1>UD 0x02180618 - urb MsgDesc: 97 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) g38<1>UD g22<8,8,1>UD 0x02180818 - urb MsgDesc: 129 SIMD8 read mlen 1 rlen 1 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x080a8037 - urb MsgDesc: 3 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g10<8,8,1>UD 0x080a8047 - urb MsgDesc: 4 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x080a8057 - urb MsgDesc: 5 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x080a8067 - urb MsgDesc: 6 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x080a8077 - urb MsgDesc: 7 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x080a8087 - urb MsgDesc: 8 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x080a8097 - urb MsgDesc: 9 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x080a80a7 - urb MsgDesc: 10 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x080a80b7 - urb MsgDesc: 11 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x080a80c7 - urb MsgDesc: 12 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080a80d7 - urb MsgDesc: 13 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x080a80e7 - urb MsgDesc: 14 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x080a80f7 - urb MsgDesc: 15 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x080a8107 - urb MsgDesc: 16 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x080a8117 - urb MsgDesc: 17 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x080a8127 - urb MsgDesc: 18 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x080a8137 - urb MsgDesc: 19 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x080a8147 - urb MsgDesc: 20 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x080a8157 - urb MsgDesc: 21 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x080a8167 - urb MsgDesc: 22 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x080a8177 - urb MsgDesc: 23 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x080a8187 - urb MsgDesc: 24 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x080a8197 - urb MsgDesc: 25 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x080a81a7 - urb MsgDesc: 26 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x080a81b7 - urb MsgDesc: 27 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x080a81c7 - urb MsgDesc: 28 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x080a81d7 - urb MsgDesc: 29 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x080a81e7 - urb MsgDesc: 30 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x080a81f7 - urb MsgDesc: 31 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x080a8207 - urb MsgDesc: 32 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x080a8217 - urb MsgDesc: 33 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) g18<1>UW g19<8,8,1>UD 0x04115e00 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 2 rlen 1 { align1 1Q }; -send(8) g2<1>UW g6<8,8,1>UD 0x0623d001 - sampler MsgDesc: ld_mcs SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; -send(16) g2<1>UW g8<8,8,1>UD 0x0c45d001 - sampler MsgDesc: ld_mcs SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; -send(8) g101<1>UW g10<8,8,1>UD 0x0c33c001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 3 { align1 1Q }; -send(8) g14<1>UW g11<8,8,1>UD 0x084b0203 - sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x0a4b0102 - sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 4 { align1 1Q }; -send(16) g26<1>UW g2<8,8,1>UD 0x0e8d0203 - sampler MsgDesc: gather4_c SIMD16 Surface = 3 Sampler = 2 mlen 7 rlen 8 { align1 1H }; -send(16) g10<1>UW g34<8,8,1>UD 0x128d0102 - sampler MsgDesc: gather4_c SIMD16 Surface = 2 Sampler = 1 mlen 9 rlen 8 { align1 1H }; -send(8) g6<1>UW g7<8,8,1>UD 0x0a1b4001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(8) g7<1>UW g12<8,8,1>UD 0x0a1b4102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; -send(8) g34<1>UD g42<8,8,1>UD 0x02480248 - urb MsgDesc: 36 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g38<1>UD g42<8,8,1>UD 0x02480448 - urb MsgDesc: 68 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g42<1>UD g42<8,8,1>UD 0x02480648 - urb MsgDesc: 100 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g43<8,8,1>UD 0x02480258 - urb MsgDesc: 37 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g43<8,8,1>UD 0x02480458 - urb MsgDesc: 69 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UD g43<8,8,1>UD 0x02480658 - urb MsgDesc: 101 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g44<8,8,1>UD 0x02480268 - urb MsgDesc: 38 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g44<8,8,1>UD 0x02480468 - urb MsgDesc: 70 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UD g44<8,8,1>UD 0x02480668 - urb MsgDesc: 102 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g45<8,8,1>UD 0x02480278 - urb MsgDesc: 39 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g45<8,8,1>UD 0x02480478 - urb MsgDesc: 71 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UD g45<8,8,1>UD 0x02480678 - urb MsgDesc: 103 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g55<8,8,1>UD 0x02480288 - urb MsgDesc: 40 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g55<8,8,1>UD 0x02480488 - urb MsgDesc: 72 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UD g55<8,8,1>UD 0x02480688 - urb MsgDesc: 104 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g56<8,8,1>UD 0x02480498 - urb MsgDesc: 73 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g56<8,8,1>UD 0x02480298 - urb MsgDesc: 41 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UD g56<8,8,1>UD 0x02480698 - urb MsgDesc: 105 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g82<8,8,1>UD 0x024804a8 - urb MsgDesc: 74 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g82<8,8,1>UD 0x024802a8 - urb MsgDesc: 42 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UD g82<8,8,1>UD 0x024806a8 - urb MsgDesc: 106 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g83<8,8,1>UD 0x024804b8 - urb MsgDesc: 75 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g83<8,8,1>UD 0x024802b8 - urb MsgDesc: 43 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g30<1>UD g83<8,8,1>UD 0x024806b8 - urb MsgDesc: 107 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g84<8,8,1>UD 0x024806c8 - urb MsgDesc: 108 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g84<8,8,1>UD 0x024802c8 - urb MsgDesc: 44 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g84<8,8,1>UD 0x024804c8 - urb MsgDesc: 76 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g85<8,8,1>UD 0x024802d8 - urb MsgDesc: 45 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g85<8,8,1>UD 0x024804d8 - urb MsgDesc: 77 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g85<8,8,1>UD 0x024806d8 - urb MsgDesc: 109 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g6<8,8,1>UD 0x024802e8 - urb MsgDesc: 46 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g6<8,8,1>UD 0x024804e8 - urb MsgDesc: 78 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g6<8,8,1>UD 0x024806e8 - urb MsgDesc: 110 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g3<8,8,1>UD 0x024802f8 - urb MsgDesc: 47 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g3<8,8,1>UD 0x024804f8 - urb MsgDesc: 79 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g3<8,8,1>UD 0x024806f8 - urb MsgDesc: 111 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g46<8,8,1>UD 0x02480308 - urb MsgDesc: 48 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g46<8,8,1>UD 0x02480508 - urb MsgDesc: 80 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g46<8,8,1>UD 0x02480708 - urb MsgDesc: 112 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g47<8,8,1>UD 0x02480318 - urb MsgDesc: 49 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g47<8,8,1>UD 0x02480518 - urb MsgDesc: 81 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g47<8,8,1>UD 0x02480718 - urb MsgDesc: 113 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g57<8,8,1>UD 0x02480328 - urb MsgDesc: 50 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g57<8,8,1>UD 0x02480528 - urb MsgDesc: 82 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g57<8,8,1>UD 0x02480728 - urb MsgDesc: 114 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g58<8,8,1>UD 0x02480338 - urb MsgDesc: 51 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g58<8,8,1>UD 0x02480538 - urb MsgDesc: 83 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g26<1>UD g58<8,8,1>UD 0x02480738 - urb MsgDesc: 115 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g59<8,8,1>UD 0x02480348 - urb MsgDesc: 52 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g59<8,8,1>UD 0x02480548 - urb MsgDesc: 84 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g59<8,8,1>UD 0x02480748 - urb MsgDesc: 116 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g60<8,8,1>UD 0x02480358 - urb MsgDesc: 53 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g60<8,8,1>UD 0x02480558 - urb MsgDesc: 85 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g60<8,8,1>UD 0x02480758 - urb MsgDesc: 117 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g61<8,8,1>UD 0x02480368 - urb MsgDesc: 54 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g61<8,8,1>UD 0x02480568 - urb MsgDesc: 86 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g61<8,8,1>UD 0x02480768 - urb MsgDesc: 118 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g62<8,8,1>UD 0x02480378 - urb MsgDesc: 55 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g62<8,8,1>UD 0x02480578 - urb MsgDesc: 87 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g62<8,8,1>UD 0x02480778 - urb MsgDesc: 119 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g63<8,8,1>UD 0x02480388 - urb MsgDesc: 56 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g63<8,8,1>UD 0x02480588 - urb MsgDesc: 88 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g63<8,8,1>UD 0x02480788 - urb MsgDesc: 120 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g64<8,8,1>UD 0x02480398 - urb MsgDesc: 57 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g64<8,8,1>UD 0x02480598 - urb MsgDesc: 89 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g64<8,8,1>UD 0x02480798 - urb MsgDesc: 121 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g68<8,8,1>UD 0x024803a8 - urb MsgDesc: 58 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g68<8,8,1>UD 0x024805a8 - urb MsgDesc: 90 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g68<8,8,1>UD 0x024807a8 - urb MsgDesc: 122 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g69<8,8,1>UD 0x024803b8 - urb MsgDesc: 59 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g69<8,8,1>UD 0x024805b8 - urb MsgDesc: 91 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UD g69<8,8,1>UD 0x024807b8 - urb MsgDesc: 123 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g70<8,8,1>UD 0x024803c8 - urb MsgDesc: 60 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g70<8,8,1>UD 0x024805c8 - urb MsgDesc: 92 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g16<1>UD g70<8,8,1>UD 0x024807c8 - urb MsgDesc: 124 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g71<8,8,1>UD 0x024803d8 - urb MsgDesc: 61 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g71<8,8,1>UD 0x024805d8 - urb MsgDesc: 93 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g16<1>UD g71<8,8,1>UD 0x024807d8 - urb MsgDesc: 125 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g72<8,8,1>UD 0x024803e8 - urb MsgDesc: 62 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g72<8,8,1>UD 0x024805e8 - urb MsgDesc: 94 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g16<1>UD g72<8,8,1>UD 0x024807e8 - urb MsgDesc: 126 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g8<1>UD g73<8,8,1>UD 0x024803f8 - urb MsgDesc: 63 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g73<8,8,1>UD 0x024805f8 - urb MsgDesc: 95 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g16<1>UD g73<8,8,1>UD 0x024807f8 - urb MsgDesc: 127 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g12<1>UD g75<8,8,1>UD 0x02480418 - urb MsgDesc: 65 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g16<1>UD g75<8,8,1>UD 0x02480618 - urb MsgDesc: 97 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) g20<1>UD g75<8,8,1>UD 0x02480818 - urb MsgDesc: 129 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a00c7 - urb MsgDesc: 12 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a00d7 - urb MsgDesc: 13 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a00e7 - urb MsgDesc: 14 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a00f7 - urb MsgDesc: 15 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a0107 - urb MsgDesc: 16 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a0117 - urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a0137 - urb MsgDesc: 19 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a0147 - urb MsgDesc: 20 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a0157 - urb MsgDesc: 21 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a0167 - urb MsgDesc: 22 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a0177 - urb MsgDesc: 23 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a0187 - urb MsgDesc: 24 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a01a7 - urb MsgDesc: 26 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a01b7 - urb MsgDesc: 27 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a01c7 - urb MsgDesc: 28 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a01d7 - urb MsgDesc: 29 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a01e7 - urb MsgDesc: 30 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a01f7 - urb MsgDesc: 31 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q }; -send(16) g46<1>UD g12<0,1,0>UD 0x02280302 - const MsgDesc: (2, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; -send(16) g50<1>UD g15<0,1,0>UD 0x02280304 - const MsgDesc: (4, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; -send(16) g34<1>UD g20<0,1,0>UD 0x02280303 - const MsgDesc: (3, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; -send(16) g16<1>UD g21<0,1,0>UD 0x02280306 - const MsgDesc: (6, 3, 0, 0) mlen 1 rlen 2 { align1 WE_all 1H }; -send(8) g5<1>UW g19<8,8,1>UD 0x02106e03 - dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) g8<1>UW g21<8,8,1>UD 0x02106e04 - dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(16) g8<1>UW g34<8,8,1>UD 0x04205e03 - dp data 1 MsgDesc: ( untyped surface read, Surface = 3, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(16) g14<1>UW g37<8,8,1>UD 0x04205e04 - dp data 1 MsgDesc: ( untyped surface read, Surface = 4, SIMD16, Mask = 0xe) mlen 2 rlen 2 { align1 1H }; -send(8) g15<1>UD g12<8,8,1>UD 0x041a0038 - urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g2<1>UW g54<8,8,1>UD 0x0242a707 - sampler MsgDesc: resinfo SIMD8 Surface = 7 Sampler = 7 mlen 1 rlen 4 { align1 1Q }; -send(8) g6<1>UW g55<8,8,1>UD 0x0242a808 - sampler MsgDesc: resinfo SIMD8 Surface = 8 Sampler = 8 mlen 1 rlen 4 { align1 1Q }; -send(8) g10<1>UW g56<8,8,1>UD 0x0242a909 - sampler MsgDesc: resinfo SIMD8 Surface = 9 Sampler = 9 mlen 1 rlen 4 { align1 1Q }; -send(8) g14<1>UW g57<8,8,1>UD 0x0242aa0a - sampler MsgDesc: resinfo SIMD8 Surface = 10 Sampler = 10 mlen 1 rlen 4 { align1 1Q }; -send(8) g18<1>UW g58<8,8,1>UD 0x0242ab0b - sampler MsgDesc: resinfo SIMD8 Surface = 11 Sampler = 11 mlen 1 rlen 4 { align1 1Q }; -send(8) g22<1>UW g59<8,8,1>UD 0x0242ac0c - sampler MsgDesc: resinfo SIMD8 Surface = 12 Sampler = 12 mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g9<8,8,1>UD 0x0c088027 - urb MsgDesc: 2 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g10<8,8,1>UD 0x0c088047 - urb MsgDesc: 4 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x0c088067 - urb MsgDesc: 6 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>UD 0x0c088037 - urb MsgDesc: 3 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g7<8,8,1>UD 0x0c088057 - urb MsgDesc: 5 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g8<8,8,1>UD 0x0c088077 - urb MsgDesc: 7 SIMD8 write masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a0197 - urb MsgDesc: 25 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a01b7 - urb MsgDesc: 27 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a01d7 - urb MsgDesc: 29 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g6<8,8,1>F 0x140a01f7 - urb MsgDesc: 31 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g120<8,8,1>F 0x8c0a0217 - urb MsgDesc: 33 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g8<1>UD g6<8,8,1>UD 0x041a0318 - urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g9<1>UD g6<8,8,1>UD 0x041a0518 - urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g10<1>UD g6<8,8,1>UD 0x041a0718 - urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g11<1>UD g6<8,8,1>UD 0x041a0918 - urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g7<1>UD g11<8,8,1>UD 0x041a0218 - urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g8<1>UD g11<8,8,1>UD 0x041a0418 - urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g9<1>UD g11<8,8,1>UD 0x041a0618 - urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g10<1>UD g11<8,8,1>UD 0x041a0818 - urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) null<1>F g10<8,8,1>UD 0x080a8227 - urb MsgDesc: 34 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g11<8,8,1>UD 0x080a8237 - urb MsgDesc: 35 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x080a8247 - urb MsgDesc: 36 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x080a8257 - urb MsgDesc: 37 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x080a8267 - urb MsgDesc: 38 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x080a8277 - urb MsgDesc: 39 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x080a8287 - urb MsgDesc: 40 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x080a8297 - urb MsgDesc: 41 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x080a82a7 - urb MsgDesc: 42 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x080a82b7 - urb MsgDesc: 43 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x080a82c7 - urb MsgDesc: 44 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x080a82d7 - urb MsgDesc: 45 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x080a82e7 - urb MsgDesc: 46 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x080a82f7 - urb MsgDesc: 47 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x080a8307 - urb MsgDesc: 48 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x080a8317 - urb MsgDesc: 49 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x080a8327 - urb MsgDesc: 50 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x080a8337 - urb MsgDesc: 51 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x080a8347 - urb MsgDesc: 52 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x080a8357 - urb MsgDesc: 53 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x080a8367 - urb MsgDesc: 54 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x080a8377 - urb MsgDesc: 55 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x080a8387 - urb MsgDesc: 56 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x080a8397 - urb MsgDesc: 57 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x080a83a7 - urb MsgDesc: 58 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x080a83b7 - urb MsgDesc: 59 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x080a83c7 - urb MsgDesc: 60 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x080a83d7 - urb MsgDesc: 61 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x080a83e7 - urb MsgDesc: 62 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x080a83f7 - urb MsgDesc: 63 SIMD8 write per-slot masked mlen 4 rlen 0 { align1 1Q }; -send(8) g8<1>UD g9<8,8,1>UD 0x02480008 - urb MsgDesc: 0 SIMD8 read mlen 1 rlen 4 { align1 1Q }; -send(8) null<1>F g123<8,8,1>F 0x8a080007 - urb MsgDesc: 0 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g4<1>UW g2<8,8,1>UD 0x04215c01 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0xc) mlen 2 rlen 2 { align1 1Q }; -send(8) g40<1>UW g38<8,8,1>UD 0x04216c01 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0xc) mlen 2 rlen 2 { align1 2Q }; -send(8) g6<1>UW g11<8,8,1>UD 0x104a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1Q }; -send(8) g124<1>UW g2<8,8,1>UD 0x04422001 - sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(16) g120<1>UW g2<8,8,1>UD 0x08842001 - sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(8) g2<1>UW g7<8,8,1>UD 0x06425001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g6<1>UW g10<8,8,1>UD 0x06425102 - sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; -send(16) g2<1>UW g11<8,8,1>UD 0x0c845001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(16) g10<1>UW g18<8,8,1>UD 0x0c845102 - sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; -send(8) null<1>F g121<8,8,1>F 0x8a080197 - urb MsgDesc: 25 SIMD8 write mlen 5 rlen 0 { align1 1Q EOT }; -send(8) g124<1>UW g6<8,8,1>UD 0x02415000 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; -send(8) g124<1>UW g6<8,8,1>UD 0x06415000 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0x0) mlen 3 rlen 4 { align1 1Q }; -send(8) g124<1>UW g6<8,8,1>UD 0x02215c00 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xc) mlen 1 rlen 2 { align1 1Q }; -send(8) g17<1>UW g27<8,8,1>UD 0x02115e00 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 0, SIMD16, Mask = 0xe) mlen 1 rlen 1 { align1 1Q }; -send(8) g124<1>UW g2<8,8,1>UD 0x02415001 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD16, Mask = 0x0) mlen 1 rlen 4 { align1 1Q }; -send(8) g2<1>UW g29<8,8,1>UD 0x02416001 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 1, SIMD8, Mask = 0x0) mlen 1 rlen 4 { align1 2Q }; -send(8) g9<1>UW g19<8,8,1>UD 0x0843e102 - sampler MsgDesc: ld2dms SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; -send(16) g23<1>UW g7<8,8,1>UD 0x1085e102 - sampler MsgDesc: ld2dms SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H }; -send(8) g124<1>UW g5<8,8,1>UD 0x0c4b0001 - sampler MsgDesc: gather4_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(16) g120<1>UW g7<8,8,1>UD 0x168d0001 - sampler MsgDesc: gather4_c SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 8 { align1 1H }; -send(8) g6<1>UW g7<8,8,1>UD 0x0a134001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(8) g7<1>UW g12<8,8,1>UD 0x0a134102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; -send(8) g22<1>UD g10<8,8,1>UD 0x041a0138 - urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g21<1>UD g10<8,8,1>UD 0x041a0338 - urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g65<1>UD g10<8,8,1>UD 0x041a0538 - urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g10<1>UD g10<8,8,1>UD 0x041a0738 - urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g65<1>UD g11<8,8,1>UD 0x041a0238 - urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g10<1>UD g11<8,8,1>UD 0x041a0438 - urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g11<1>UD g11<8,8,1>UD 0x041a0638 - urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g8<1>UD g7<8,8,1>UD 0x041a0048 - urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g6<1>UW g10<8,8,1>UD 0x0a4a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 4 { align1 1Q }; -send(8) g2<1>UW g7<8,8,1>UD 0x06426001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q }; -send(8) g6<1>UW g10<8,8,1>UD 0x06426102 - sampler MsgDesc: sample_l_c SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q }; -send(16) g2<1>UW g11<8,8,1>UD 0x0c846001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H }; -send(16) g10<1>UW g18<8,8,1>UD 0x0c846102 - sampler MsgDesc: sample_l_c SIMD16 Surface = 2 Sampler = 1 mlen 6 rlen 8 { align1 1H }; -send(8) g124<1>UW g2<8,8,1>UD 0x08320001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 3 { align1 1Q }; -send(16) g120<1>UW g2<8,8,1>UD 0x10640001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 6 { align1 1H }; -send(8) g6<1>UW g7<8,8,1>UD 0x0c1b4001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 1 { align1 1Q }; -send(8) g7<1>UW g13<8,8,1>UD 0x0c1b4102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 6 rlen 1 { align1 1Q }; -send(8) g2<1>UW g7<8,8,1>UD 0x08425001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) g6<1>UW g11<8,8,1>UD 0x08425102 - sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q }; -send(16) g2<1>UW g11<8,8,1>UD 0x10845001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 8 { align1 1H }; -send(16) g10<1>UW g19<8,8,1>UD 0x10845102 - sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 8 { align1 1H }; -send(8) g124<1>UW g2<8,8,1>UD 0x02306801 - dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD8, Mask = 0x8) mlen 1 rlen 3 { align1 1Q }; -send(16) g120<1>UW g2<8,8,1>UD 0x04605801 - dp data 1 MsgDesc: ( untyped surface read, Surface = 1, SIMD16, Mask = 0x8) mlen 2 rlen 6 { align1 1H }; -send(8) g8<1>UD g7<8,8,1>UD 0x043a0128 - urb MsgDesc: 18 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g12<1>UW g5<8,8,1>UD 0x0833e001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 3 { align1 1Q }; -send(8) g15<1>UW g17<8,8,1>UD 0x0823e001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1Q }; -send(16) g7<1>UW g13<8,8,1>UD 0x1065e001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 6 { align1 1H }; -send(16) g33<1>UW g21<8,8,1>UD 0x1045e001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 4 { align1 1H }; -send(8) g14<1>UW g14<8,8,1>UD 0x101b4001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 1 { align1 1Q }; -send(8) g15<1>UW g22<8,8,1>UD 0x101b4102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 1 { align1 1Q }; -send(8) g8<1>UD g20<8,8,1>UD 0x044a0138 - urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g20<8,8,1>UD 0x044a0338 - urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g16<1>UD g20<8,8,1>UD 0x044a0538 - urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g20<1>UD g20<8,8,1>UD 0x044a0738 - urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g14<1>UD g22<8,8,1>UD 0x044a0238 - urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g18<1>UD g22<8,8,1>UD 0x044a0438 - urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g22<1>UD g22<8,8,1>UD 0x044a0638 - urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g11<1>UW g5<8,8,1>UD 0x04120003 - sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; -send(8) g12<1>UW g5<8,8,1>UD 0x04120004 - sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; -send(16) g8<1>UW g12<8,8,1>UD 0x08240003 - sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 2 { align1 1H }; -send(16) g10<1>UW g12<8,8,1>UD 0x08240004 - sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 2 { align1 1H }; -send(8) g6<1>UW g7<8,8,1>UD 0x08125001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 1 { align1 1Q }; -send(8) g7<1>UW g11<8,8,1>UD 0x08125102 - sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 1 { align1 1Q }; -send(16) g10<1>UW g12<8,8,1>UD 0x10245001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 8 rlen 2 { align1 1H }; -send(16) g12<1>UW g20<8,8,1>UD 0x10245102 - sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 8 rlen 2 { align1 1H }; -send(8) g2<1>UW g13<8,8,1>UD 0x0623a001 - sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; -send(16) g6<1>UW g23<8,8,1>UD 0x0c45a001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; -send(8) g124<1>UW g7<8,8,1>UD 0x0c4b2000 - sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; -send(8) g13<1>UD g39<8,8,1>UD 0x041a0058 - urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g4<1>UD g10<8,8,1>UD 0x041a0068 - urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g4<1>UD g3<8,8,1>UD 0x041a0078 - urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g4<1>UD g3<8,8,1>UD 0x041a0088 - urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g4<1>UD g3<8,8,1>UD 0x041a0098 - urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g4<1>UD g3<8,8,1>UD 0x041a00a8 - urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g4<1>UD g3<8,8,1>UD 0x041a00b8 - urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g4<1>UD g3<8,8,1>UD 0x041a00c8 - urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a00d8 - urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a00e8 - urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a00f8 - urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0108 - urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0118 - urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0148 - urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0158 - urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0168 - urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0178 - urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0188 - urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0198 - urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a01a8 - urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a01b8 - urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a01c8 - urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a01d8 - urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a01e8 - urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a01f8 - urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g3<1>UD g2<8,8,1>UD 0x041a0208 - urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 1 { align1 1Q }; -send(8) g38<1>UW g38<8,8,1>UD 0x084a8405 - sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; -send(8) g46<1>UW g23<8,8,1>UD 0x064a8304 - sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; -send(8) g28<1>UW g28<8,8,1>UD 0x064a8506 - sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 4 { align1 1Q }; -send(8) g12<1>UW g23<8,8,1>UD 0x064a8607 - sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 6 mlen 3 rlen 4 { align1 1Q }; -send(8) g12<1>UW g32<8,8,1>UD 0x084a8708 - sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 7 mlen 4 rlen 4 { align1 1Q }; -send(8) g26<1>UW g13<8,8,1>UD 0x064a8809 - sampler MsgDesc: gather4 SIMD8 Surface = 9 Sampler = 8 mlen 3 rlen 4 { align1 1Q }; -send(8) g26<1>UW g26<8,8,1>UD 0x084b090a - sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 9 mlen 4 rlen 4 { align1 1Q }; -send(8) g2<1>UW g2<8,8,1>UD 0x0a4b0a0b - sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 10 mlen 5 rlen 4 { align1 1Q }; -send(8) g6<1>UW g6<8,8,1>UD 0x084b0b0c - sampler MsgDesc: gather4_c SIMD8 Surface = 12 Sampler = 11 mlen 4 rlen 4 { align1 1Q }; -send(16) g30<1>UW g73<8,8,1>UD 0x0a8c8304 - sampler MsgDesc: gather4 SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 8 { align1 1H }; -send(16) g40<1>UW g2<8,8,1>UD 0x0e8c8405 - sampler MsgDesc: gather4 SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H }; -send(16) g5<1>UW g33<8,8,1>UD 0x0a8c8506 - sampler MsgDesc: gather4 SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 8 { align1 1H }; -send(16) g32<1>UW g55<8,8,1>UD 0x0a8c8607 - sampler MsgDesc: gather4 SIMD16 Surface = 7 Sampler = 6 mlen 5 rlen 8 { align1 1H }; -send(16) g30<1>UW g23<8,8,1>UD 0x0e8c8708 - sampler MsgDesc: gather4 SIMD16 Surface = 8 Sampler = 7 mlen 7 rlen 8 { align1 1H }; -send(16) g5<1>UW g40<8,8,1>UD 0x0a8c8809 - sampler MsgDesc: gather4 SIMD16 Surface = 9 Sampler = 8 mlen 5 rlen 8 { align1 1H }; -send(16) g38<1>UW g67<8,8,1>UD 0x0e8d090a - sampler MsgDesc: gather4_c SIMD16 Surface = 10 Sampler = 9 mlen 7 rlen 8 { align1 1H }; -send(16) g38<1>UW g2<8,8,1>UD 0x128d0a0b - sampler MsgDesc: gather4_c SIMD16 Surface = 11 Sampler = 10 mlen 9 rlen 8 { align1 1H }; -send(16) g10<1>UW g39<8,8,1>UD 0x0e8d0b0c - sampler MsgDesc: gather4_c SIMD16 Surface = 12 Sampler = 11 mlen 7 rlen 8 { align1 1H }; -send(8) g2<1>UW g6<8,8,1>UD 0x0e4b2000 - sampler MsgDesc: gather4_po_c SIMD8 Surface = 0 Sampler = 0 mlen 7 rlen 4 { align1 1Q }; -send(8) g11<1>UW g7<8,8,1>UD 0x04120102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 1 { align1 1Q }; -send(8) g12<1>UW g7<8,8,1>UD 0x04120203 - sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 2 mlen 2 rlen 1 { align1 1Q }; -send(16) g6<1>UW g11<8,8,1>UD 0x08240102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 4 rlen 2 { align1 1H }; -send(16) g8<1>UW g11<8,8,1>UD 0x08240203 - sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 2 mlen 4 rlen 2 { align1 1H }; -send(8) g5<1>UW g6<8,8,1>UD 0x04220003 - sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 2 { align1 1Q }; -send(16) g8<1>UW g12<8,8,1>UD 0x08440003 - sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 4 { align1 1H }; -send(8) g5<1>UW g2<8,8,1>UD 0x04129001 - sampler MsgDesc: lod SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 1 { align1 1Q }; -send(16) g6<1>UW g2<8,8,1>UD 0x08249001 - sampler MsgDesc: lod SIMD16 Surface = 1 Sampler = 0 mlen 4 rlen 2 { align1 1H }; -send(8) g11<1>UW g4<8,8,1>UD 0x04415002 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD16, Mask = 0x0) mlen 2 rlen 4 { align1 1Q }; -send(8) g7<1>UW g5<8,8,1>UD 0x04416002 - dp data 1 MsgDesc: ( DC typed surface read, Surface = 2, SIMD8, Mask = 0x0) mlen 2 rlen 4 { align1 2Q }; -send(8) null<1>F g16<8,8,1>UD 0x0e0a8057 - urb MsgDesc: 5 SIMD8 write per-slot masked mlen 7 rlen 0 { align1 1Q }; -send(8) g6<1>UD g18<8,8,1>UD 0x043a0318 - urb MsgDesc: 49 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g9<1>UD g18<8,8,1>UD 0x043a0518 - urb MsgDesc: 81 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g12<1>UD g18<8,8,1>UD 0x043a0718 - urb MsgDesc: 113 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g15<1>UD g18<8,8,1>UD 0x043a0918 - urb MsgDesc: 145 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g11<1>UD g23<8,8,1>UD 0x043a0218 - urb MsgDesc: 33 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g14<1>UD g23<8,8,1>UD 0x043a0418 - urb MsgDesc: 65 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g17<1>UD g23<8,8,1>UD 0x043a0618 - urb MsgDesc: 97 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g20<1>UD g23<8,8,1>UD 0x043a0818 - urb MsgDesc: 129 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) null<1>F g12<8,8,1>UD 0x0c0a8227 - urb MsgDesc: 34 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g13<8,8,1>UD 0x0c0a8237 - urb MsgDesc: 35 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g14<8,8,1>UD 0x0c0a8247 - urb MsgDesc: 36 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g15<8,8,1>UD 0x0c0a8257 - urb MsgDesc: 37 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g16<8,8,1>UD 0x0c0a8267 - urb MsgDesc: 38 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g17<8,8,1>UD 0x0c0a8277 - urb MsgDesc: 39 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g18<8,8,1>UD 0x0c0a8287 - urb MsgDesc: 40 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g19<8,8,1>UD 0x0c0a8297 - urb MsgDesc: 41 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g20<8,8,1>UD 0x0c0a82a7 - urb MsgDesc: 42 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g21<8,8,1>UD 0x0c0a82b7 - urb MsgDesc: 43 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g22<8,8,1>UD 0x0c0a82c7 - urb MsgDesc: 44 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g23<8,8,1>UD 0x0c0a82d7 - urb MsgDesc: 45 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g24<8,8,1>UD 0x0c0a82e7 - urb MsgDesc: 46 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g25<8,8,1>UD 0x0c0a82f7 - urb MsgDesc: 47 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g26<8,8,1>UD 0x0c0a8307 - urb MsgDesc: 48 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g27<8,8,1>UD 0x0c0a8317 - urb MsgDesc: 49 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g28<8,8,1>UD 0x0c0a8327 - urb MsgDesc: 50 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g29<8,8,1>UD 0x0c0a8337 - urb MsgDesc: 51 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g30<8,8,1>UD 0x0c0a8347 - urb MsgDesc: 52 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>UD 0x0c0a8357 - urb MsgDesc: 53 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g32<8,8,1>UD 0x0c0a8367 - urb MsgDesc: 54 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g33<8,8,1>UD 0x0c0a8377 - urb MsgDesc: 55 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g34<8,8,1>UD 0x0c0a8387 - urb MsgDesc: 56 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g35<8,8,1>UD 0x0c0a8397 - urb MsgDesc: 57 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g36<8,8,1>UD 0x0c0a83a7 - urb MsgDesc: 58 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g37<8,8,1>UD 0x0c0a83b7 - urb MsgDesc: 59 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g38<8,8,1>UD 0x0c0a83c7 - urb MsgDesc: 60 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g39<8,8,1>UD 0x0c0a83d7 - urb MsgDesc: 61 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g40<8,8,1>UD 0x0c0a83e7 - urb MsgDesc: 62 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) null<1>F g41<8,8,1>UD 0x0c0a83f7 - urb MsgDesc: 63 SIMD8 write per-slot masked mlen 6 rlen 0 { align1 1Q }; -send(8) g8<1>UW g7<8,8,1>UD 0x10134001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 1 { align1 1Q }; -send(8) g9<1>UW g15<8,8,1>UD 0x10134102 - sampler MsgDesc: sample_d_c SIMD8 Surface = 2 Sampler = 1 mlen 8 rlen 1 { align1 1Q }; -send(8) g16<1>UD g16<8,8,1>UD 0x044a0148 - urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g38<1>UW g38<8,8,1>UD 0x084a8404 - sampler MsgDesc: gather4 SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; -send(8) g46<1>UW g23<8,8,1>UD 0x064a8303 - sampler MsgDesc: gather4 SIMD8 Surface = 3 Sampler = 3 mlen 3 rlen 4 { align1 1Q }; -send(8) g28<1>UW g28<8,8,1>UD 0x064a8505 - sampler MsgDesc: gather4 SIMD8 Surface = 5 Sampler = 5 mlen 3 rlen 4 { align1 1Q }; -send(8) g12<1>UW g23<8,8,1>UD 0x064a8606 - sampler MsgDesc: gather4 SIMD8 Surface = 6 Sampler = 6 mlen 3 rlen 4 { align1 1Q }; -send(8) g12<1>UW g32<8,8,1>UD 0x084a8707 - sampler MsgDesc: gather4 SIMD8 Surface = 7 Sampler = 7 mlen 4 rlen 4 { align1 1Q }; -send(8) g26<1>UW g13<8,8,1>UD 0x064a8808 - sampler MsgDesc: gather4 SIMD8 Surface = 8 Sampler = 8 mlen 3 rlen 4 { align1 1Q }; -send(8) g26<1>UW g26<8,8,1>UD 0x084b0909 - sampler MsgDesc: gather4_c SIMD8 Surface = 9 Sampler = 9 mlen 4 rlen 4 { align1 1Q }; -send(8) g2<1>UW g2<8,8,1>UD 0x0a4b0a0a - sampler MsgDesc: gather4_c SIMD8 Surface = 10 Sampler = 10 mlen 5 rlen 4 { align1 1Q }; -send(8) g10<1>UW g10<8,8,1>UD 0x084b0b0b - sampler MsgDesc: gather4_c SIMD8 Surface = 11 Sampler = 11 mlen 4 rlen 4 { align1 1Q }; -send(8) g2<1>UD g15<8,8,1>UD 0x043a0048 - urb MsgDesc: 4 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g12<1>UD g15<8,8,1>UD 0x043a0058 - urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0068 - urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0078 - urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0088 - urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0098 - urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a00a8 - urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a00b8 - urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a00c8 - urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a00d8 - urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a00e8 - urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a00f8 - urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0108 - urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0118 - urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0138 - urb MsgDesc: 19 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0148 - urb MsgDesc: 20 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0158 - urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0168 - urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0178 - urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0188 - urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0198 - urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a01a8 - urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a01b8 - urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a01c8 - urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a01d8 - urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a01e8 - urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a01f8 - urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g2<1>UD g2<8,8,1>UD 0x043a0208 - urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) null<1>F g11<8,8,1>F 0x140a0047 - urb MsgDesc: 4 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g31<8,8,1>F 0x140a0087 - urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q }; -send(8) null<1>F g118<8,8,1>F 0x940a0087 - urb MsgDesc: 8 SIMD8 write per-slot mlen 10 rlen 0 { align1 1Q EOT }; -send(8) g14<1>UW g11<8,8,1>UD 0x0a4b0202 - sampler MsgDesc: gather4_c SIMD8 Surface = 2 Sampler = 2 mlen 5 rlen 4 { align1 1Q }; -send(8) g18<1>UW g18<8,8,1>UD 0x0c4b0303 - sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 3 mlen 6 rlen 4 { align1 1Q }; -send(8) g22<1>UW g24<8,8,1>UD 0x084b0404 - sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; -send(8) g15<1>UW g2<8,8,1>UD 0x06423203 - sampler MsgDesc: sample_c SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q }; -send(16) g19<1>UW g27<8,8,1>UD 0x0c843203 - sampler MsgDesc: sample_c SIMD16 Surface = 3 Sampler = 2 mlen 6 rlen 8 { align1 1H }; -send(8) g7<1>UW g9<8,8,1>UD 0x0a13c001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(16) g20<1>UW g7<8,8,1>UD 0x1425c001 - sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; -send(8) g21<1>UW g5<8,8,1>UD 0x0a33c001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 3 { align1 1Q }; -send(8) g18<1>UW g24<8,8,1>UD 0x0a23c001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 2 { align1 1Q }; -send(16) g15<1>UW g21<8,8,1>UD 0x1465c001 - sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 6 { align1 1H }; -send(16) g7<1>UW g31<8,8,1>UD 0x1445c001 - sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 4 { align1 1H }; -send(8) g124<1>UW g6<8,8,1>UD 0x04438303 - sampler MsgDesc: sample_lz SIMD8 Surface = 3 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; -send(8) g11<1>UD g17<8,8,1>UD 0x043a0338 - urb MsgDesc: 51 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g14<1>UD g17<8,8,1>UD 0x043a0538 - urb MsgDesc: 83 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g17<1>UD g17<8,8,1>UD 0x043a0738 - urb MsgDesc: 115 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g9<1>UD g18<8,8,1>UD 0x043a0038 - urb MsgDesc: 3 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g12<1>UD g18<8,8,1>UD 0x043a0238 - urb MsgDesc: 35 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g15<1>UD g18<8,8,1>UD 0x043a0438 - urb MsgDesc: 67 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g18<1>UD g18<8,8,1>UD 0x043a0638 - urb MsgDesc: 99 SIMD8 read per-slot mlen 2 rlen 3 { align1 1Q }; -send(8) g6<1>UW g10<8,8,1>UD 0x08424001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 4 { align1 1Q }; -send(8) g9<1>UW g5<8,8,1>UD 0x04420002 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(16) g13<1>UW g7<8,8,1>UD 0x08840002 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -(+f1.0) send(8) g124<1>UW g2<8,8,1>UD 0x0211a501 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, inc) mlen 1 rlen 1 { align1 1Q }; -(+f1.0) send(8) g121<1>UW g3<8,8,1>UD 0x0211b501 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, inc) mlen 1 rlen 1 { align1 2Q }; -send(8) g22<1>UD g32<8,8,1>UD 0x02280238 - urb MsgDesc: 35 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g32<8,8,1>UD 0x02280438 - urb MsgDesc: 67 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g26<1>UD g32<8,8,1>UD 0x02280638 - urb MsgDesc: 99 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g28<1>UD g32<8,8,1>UD 0x02280248 - urb MsgDesc: 36 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g30<1>UD g32<8,8,1>UD 0x02280448 - urb MsgDesc: 68 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g32<1>UD g32<8,8,1>UD 0x02280648 - urb MsgDesc: 100 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g33<8,8,1>UD 0x02280258 - urb MsgDesc: 37 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g33<8,8,1>UD 0x02280458 - urb MsgDesc: 69 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g26<1>UD g33<8,8,1>UD 0x02280658 - urb MsgDesc: 101 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g34<8,8,1>UD 0x02280268 - urb MsgDesc: 38 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g34<8,8,1>UD 0x02280468 - urb MsgDesc: 70 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g26<1>UD g34<8,8,1>UD 0x02280668 - urb MsgDesc: 102 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g35<8,8,1>UD 0x02280478 - urb MsgDesc: 71 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g35<8,8,1>UD 0x02280278 - urb MsgDesc: 39 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g26<1>UD g35<8,8,1>UD 0x02280678 - urb MsgDesc: 103 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g36<8,8,1>UD 0x02280688 - urb MsgDesc: 104 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g36<8,8,1>UD 0x02280288 - urb MsgDesc: 40 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g36<8,8,1>UD 0x02280488 - urb MsgDesc: 72 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g37<8,8,1>UD 0x02280298 - urb MsgDesc: 41 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g37<8,8,1>UD 0x02280498 - urb MsgDesc: 73 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g37<8,8,1>UD 0x02280698 - urb MsgDesc: 105 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g38<8,8,1>UD 0x022802a8 - urb MsgDesc: 42 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g38<8,8,1>UD 0x022804a8 - urb MsgDesc: 74 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g38<8,8,1>UD 0x022806a8 - urb MsgDesc: 106 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g39<8,8,1>UD 0x022802b8 - urb MsgDesc: 43 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g39<8,8,1>UD 0x022804b8 - urb MsgDesc: 75 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g24<1>UD g39<8,8,1>UD 0x022806b8 - urb MsgDesc: 107 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g40<8,8,1>UD 0x022802c8 - urb MsgDesc: 44 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g40<8,8,1>UD 0x022804c8 - urb MsgDesc: 76 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g40<8,8,1>UD 0x022806c8 - urb MsgDesc: 108 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g41<8,8,1>UD 0x022802d8 - urb MsgDesc: 45 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g41<8,8,1>UD 0x022804d8 - urb MsgDesc: 77 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g41<8,8,1>UD 0x022806d8 - urb MsgDesc: 109 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g42<8,8,1>UD 0x022802e8 - urb MsgDesc: 46 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g42<8,8,1>UD 0x022804e8 - urb MsgDesc: 78 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g42<8,8,1>UD 0x022806e8 - urb MsgDesc: 110 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g43<8,8,1>UD 0x022802f8 - urb MsgDesc: 47 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g43<8,8,1>UD 0x022804f8 - urb MsgDesc: 79 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g22<1>UD g43<8,8,1>UD 0x022806f8 - urb MsgDesc: 111 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g44<8,8,1>UD 0x02280308 - urb MsgDesc: 48 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g44<8,8,1>UD 0x02280508 - urb MsgDesc: 80 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g44<8,8,1>UD 0x02280708 - urb MsgDesc: 112 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g45<8,8,1>UD 0x02280318 - urb MsgDesc: 49 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g45<8,8,1>UD 0x02280518 - urb MsgDesc: 81 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g45<8,8,1>UD 0x02280718 - urb MsgDesc: 113 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g46<8,8,1>UD 0x02280328 - urb MsgDesc: 50 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g46<8,8,1>UD 0x02280528 - urb MsgDesc: 82 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g46<8,8,1>UD 0x02280728 - urb MsgDesc: 114 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g47<8,8,1>UD 0x02280338 - urb MsgDesc: 51 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g47<8,8,1>UD 0x02280538 - urb MsgDesc: 83 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g47<8,8,1>UD 0x02280738 - urb MsgDesc: 115 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g48<8,8,1>UD 0x02280348 - urb MsgDesc: 52 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g48<8,8,1>UD 0x02280548 - urb MsgDesc: 84 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g48<8,8,1>UD 0x02280748 - urb MsgDesc: 116 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g49<8,8,1>UD 0x02280358 - urb MsgDesc: 53 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g49<8,8,1>UD 0x02280558 - urb MsgDesc: 85 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g49<8,8,1>UD 0x02280758 - urb MsgDesc: 117 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g50<8,8,1>UD 0x02280368 - urb MsgDesc: 54 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g50<8,8,1>UD 0x02280568 - urb MsgDesc: 86 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g50<8,8,1>UD 0x02280768 - urb MsgDesc: 118 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g53<8,8,1>UD 0x02280378 - urb MsgDesc: 55 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g53<8,8,1>UD 0x02280578 - urb MsgDesc: 87 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g53<8,8,1>UD 0x02280778 - urb MsgDesc: 119 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g54<8,8,1>UD 0x02280388 - urb MsgDesc: 56 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g54<8,8,1>UD 0x02280588 - urb MsgDesc: 88 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g54<8,8,1>UD 0x02280788 - urb MsgDesc: 120 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g55<8,8,1>UD 0x02280398 - urb MsgDesc: 57 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g55<8,8,1>UD 0x02280598 - urb MsgDesc: 89 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g55<8,8,1>UD 0x02280798 - urb MsgDesc: 121 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g56<8,8,1>UD 0x022803a8 - urb MsgDesc: 58 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g56<8,8,1>UD 0x022805a8 - urb MsgDesc: 90 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g56<8,8,1>UD 0x022807a8 - urb MsgDesc: 122 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g57<8,8,1>UD 0x022803b8 - urb MsgDesc: 59 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g57<8,8,1>UD 0x022805b8 - urb MsgDesc: 91 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g57<8,8,1>UD 0x022807b8 - urb MsgDesc: 123 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g58<8,8,1>UD 0x022803c8 - urb MsgDesc: 60 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g58<8,8,1>UD 0x022805c8 - urb MsgDesc: 92 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g58<8,8,1>UD 0x022807c8 - urb MsgDesc: 124 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g59<8,8,1>UD 0x022803d8 - urb MsgDesc: 61 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g59<8,8,1>UD 0x022805d8 - urb MsgDesc: 93 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g59<8,8,1>UD 0x022807d8 - urb MsgDesc: 125 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g60<8,8,1>UD 0x022803e8 - urb MsgDesc: 62 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g60<8,8,1>UD 0x022805e8 - urb MsgDesc: 94 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g60<8,8,1>UD 0x022807e8 - urb MsgDesc: 126 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g61<8,8,1>UD 0x022803f8 - urb MsgDesc: 63 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g61<8,8,1>UD 0x022805f8 - urb MsgDesc: 95 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g61<8,8,1>UD 0x022807f8 - urb MsgDesc: 127 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g62<8,8,1>UD 0x02280408 - urb MsgDesc: 64 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g62<8,8,1>UD 0x02280608 - urb MsgDesc: 96 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g14<1>UD g62<8,8,1>UD 0x02280808 - urb MsgDesc: 128 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g8<1>UD g63<8,8,1>UD 0x02280218 - urb MsgDesc: 33 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g10<1>UD g63<8,8,1>UD 0x02280418 - urb MsgDesc: 65 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g12<1>UD g63<8,8,1>UD 0x02280618 - urb MsgDesc: 97 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g14<1>UD g63<8,8,1>UD 0x02280818 - urb MsgDesc: 129 SIMD8 read mlen 1 rlen 2 { align1 1Q }; -send(8) g29<1>UW g18<8,8,1>UD 0x04420008 - sampler MsgDesc: sample SIMD8 Surface = 8 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(8) g35<1>UW g18<8,8,1>UD 0x04420109 - sampler MsgDesc: sample SIMD8 Surface = 9 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; -send(8) g41<1>UW g18<8,8,1>UD 0x0442020a - sampler MsgDesc: sample SIMD8 Surface = 10 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; -send(8) g2<1>UW g18<8,8,1>UD 0x0442030b - sampler MsgDesc: sample SIMD8 Surface = 11 Sampler = 3 mlen 2 rlen 4 { align1 1Q }; -send(8) g6<1>UW g18<8,8,1>UD 0x0442040c - sampler MsgDesc: sample SIMD8 Surface = 12 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; -send(8) g10<1>UW g18<8,8,1>UD 0x0442050d - sampler MsgDesc: sample SIMD8 Surface = 13 Sampler = 5 mlen 2 rlen 4 { align1 1Q }; -send(8) g14<1>UW g18<8,8,1>UD 0x0442060e - sampler MsgDesc: sample SIMD8 Surface = 14 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; -send(8) g18<1>UW g18<8,8,1>UD 0x0442070f - sampler MsgDesc: sample SIMD8 Surface = 15 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; -send(16) g32<1>UW g22<8,8,1>UD 0x08840008 - sampler MsgDesc: sample SIMD16 Surface = 8 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(16) g42<1>UW g22<8,8,1>UD 0x08840109 - sampler MsgDesc: sample SIMD16 Surface = 9 Sampler = 1 mlen 4 rlen 8 { align1 1H }; -send(16) g60<1>UW g22<8,8,1>UD 0x0884020a - sampler MsgDesc: sample SIMD16 Surface = 10 Sampler = 2 mlen 4 rlen 8 { align1 1H }; -send(16) g70<1>UW g22<8,8,1>UD 0x0884030b - sampler MsgDesc: sample SIMD16 Surface = 11 Sampler = 3 mlen 4 rlen 8 { align1 1H }; -send(16) g78<1>UW g22<8,8,1>UD 0x0884040c - sampler MsgDesc: sample SIMD16 Surface = 12 Sampler = 4 mlen 4 rlen 8 { align1 1H }; -send(16) g86<1>UW g22<8,8,1>UD 0x0884050d - sampler MsgDesc: sample SIMD16 Surface = 13 Sampler = 5 mlen 4 rlen 8 { align1 1H }; -send(16) g94<1>UW g22<8,8,1>UD 0x0884060e - sampler MsgDesc: sample SIMD16 Surface = 14 Sampler = 6 mlen 4 rlen 8 { align1 1H }; -send(16) g52<1>UW g22<8,8,1>UD 0x0884070f - sampler MsgDesc: sample SIMD16 Surface = 15 Sampler = 7 mlen 4 rlen 8 { align1 1H }; -send(8) g16<1>UW g42<8,8,1>UD 0x04438101 - sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 1 mlen 2 rlen 4 { align1 1Q }; -send(8) g20<1>UW g42<8,8,1>UD 0x04438202 - sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 2 mlen 2 rlen 4 { align1 1Q }; -send(8) g29<1>UW g42<8,8,1>UD 0x04438404 - sampler MsgDesc: sample_lz SIMD8 Surface = 4 Sampler = 4 mlen 2 rlen 4 { align1 1Q }; -send(8) g38<1>UW g42<8,8,1>UD 0x04438606 - sampler MsgDesc: sample_lz SIMD8 Surface = 6 Sampler = 6 mlen 2 rlen 4 { align1 1Q }; -send(8) g124<1>UW g42<8,8,1>UD 0x04438707 - sampler MsgDesc: sample_lz SIMD8 Surface = 7 Sampler = 7 mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g16<8,8,1>UD 0x044a0058 - urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0068 - urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0078 - urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0088 - urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0098 - urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a00a8 - urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a00b8 - urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a00c8 - urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a00d8 - urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a00e8 - urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a00f8 - urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0108 - urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0118 - urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0158 - urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0168 - urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0178 - urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0188 - urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0198 - urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a01a8 - urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a01b8 - urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a01c8 - urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a01d8 - urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a01e8 - urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a01f8 - urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g12<1>UD g2<8,8,1>UD 0x044a0208 - urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 4 { align1 1Q }; -send(8) g14<1>UW g15<8,8,1>UD 0x0a125001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 1 { align1 1Q }; -send(8) g15<1>UW g20<8,8,1>UD 0x0a125102 - sampler MsgDesc: sample_b_c SIMD8 Surface = 2 Sampler = 1 mlen 5 rlen 1 { align1 1Q }; -send(16) g41<1>UW g7<8,8,1>UD 0x14245001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 10 rlen 2 { align1 1H }; -send(16) g43<1>UW g17<8,8,1>UD 0x14245102 - sampler MsgDesc: sample_b_c SIMD16 Surface = 2 Sampler = 1 mlen 10 rlen 2 { align1 1H }; -send(8) g2<1>UW g5<8,8,1>UD 0x06223001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 2 { align1 1Q }; -send(16) g2<1>UW g7<8,8,1>UD 0x0c443001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 4 { align1 1H }; -send(8) g2<1>UW g2<8,8,1>UD 0x06323001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 3 { align1 1Q }; -send(16) g2<1>UW g24<8,8,1>UD 0x0c643001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 6 { align1 1H }; -send(8) null<1>F g120<8,8,1>F 0x8c0a0117 - urb MsgDesc: 17 SIMD8 write per-slot mlen 6 rlen 0 { align1 1Q EOT }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380128 - urb MsgDesc: 18 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380138 - urb MsgDesc: 19 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380148 - urb MsgDesc: 20 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380158 - urb MsgDesc: 21 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380168 - urb MsgDesc: 22 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380178 - urb MsgDesc: 23 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380188 - urb MsgDesc: 24 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x02380198 - urb MsgDesc: 25 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x023801a8 - urb MsgDesc: 26 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x023801b8 - urb MsgDesc: 27 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x023801c8 - urb MsgDesc: 28 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x023801d8 - urb MsgDesc: 29 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x023801e8 - urb MsgDesc: 30 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g11<1>UD g1<8,8,1>UD 0x023801f8 - urb MsgDesc: 31 SIMD8 read mlen 1 rlen 3 { align1 1Q }; -send(8) g10<1>UW g2<8,8,1>UD 0x04420004 - sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(16) g18<1>UW g2<8,8,1>UD 0x08840004 - sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(8) g10<1>UW g2<8,8,1>UD 0x04420003 - sampler MsgDesc: sample SIMD8 Surface = 3 Sampler = 0 mlen 2 rlen 4 { align1 1Q }; -send(16) g18<1>UW g2<8,8,1>UD 0x08840003 - sampler MsgDesc: sample SIMD16 Surface = 3 Sampler = 0 mlen 4 rlen 8 { align1 1H }; -send(8) g11<1>UD g13<8,8,1>UD 0x042a0058 - urb MsgDesc: 5 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a0068 - urb MsgDesc: 6 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a0078 - urb MsgDesc: 7 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a0088 - urb MsgDesc: 8 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a0098 - urb MsgDesc: 9 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a00a8 - urb MsgDesc: 10 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a00b8 - urb MsgDesc: 11 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a00c8 - urb MsgDesc: 12 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a00d8 - urb MsgDesc: 13 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a00e8 - urb MsgDesc: 14 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a00f8 - urb MsgDesc: 15 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a0108 - urb MsgDesc: 16 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g11<8,8,1>UD 0x042a0118 - urb MsgDesc: 17 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a0158 - urb MsgDesc: 21 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a0168 - urb MsgDesc: 22 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a0178 - urb MsgDesc: 23 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a0188 - urb MsgDesc: 24 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a0198 - urb MsgDesc: 25 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a01a8 - urb MsgDesc: 26 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a01b8 - urb MsgDesc: 27 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a01c8 - urb MsgDesc: 28 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a01d8 - urb MsgDesc: 29 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a01e8 - urb MsgDesc: 30 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a01f8 - urb MsgDesc: 31 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g2<1>UD g3<8,8,1>UD 0x042a0208 - urb MsgDesc: 32 SIMD8 read per-slot mlen 2 rlen 2 { align1 1Q }; -send(8) g9<1>UW g15<8,8,1>UD 0x021ab102 - sampler MsgDesc: sampleinfo SIMD8 Surface = 2 Sampler = 1 mlen 1 rlen 1 { align1 1Q }; -send(8) g10<1>UW g16<8,8,1>UD 0x021ab203 - sampler MsgDesc: sampleinfo SIMD8 Surface = 3 Sampler = 2 mlen 1 rlen 1 { align1 1Q }; -send(8) g11<1>UW g17<8,8,1>UD 0x021ab304 - sampler MsgDesc: sampleinfo SIMD8 Surface = 4 Sampler = 3 mlen 1 rlen 1 { align1 1Q }; -send(8) g12<1>UW g18<8,8,1>UD 0x021ab405 - sampler MsgDesc: sampleinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 1 { align1 1Q }; -send(8) g13<1>UW g19<8,8,1>UD 0x021ab506 - sampler MsgDesc: sampleinfo SIMD8 Surface = 6 Sampler = 5 mlen 1 rlen 1 { align1 1Q }; -send(16) g14<1>UW g16<8,8,1>UD 0x022cb102 - sampler MsgDesc: sampleinfo SIMD16 Surface = 2 Sampler = 1 mlen 1 rlen 2 { align1 1H }; -send(16) g16<1>UW g18<8,8,1>UD 0x022cb203 - sampler MsgDesc: sampleinfo SIMD16 Surface = 3 Sampler = 2 mlen 1 rlen 2 { align1 1H }; -send(16) g18<1>UW g20<8,8,1>UD 0x022cb304 - sampler MsgDesc: sampleinfo SIMD16 Surface = 4 Sampler = 3 mlen 1 rlen 2 { align1 1H }; -send(16) g20<1>UW g22<8,8,1>UD 0x022cb405 - sampler MsgDesc: sampleinfo SIMD16 Surface = 5 Sampler = 4 mlen 1 rlen 2 { align1 1H }; -send(16) g22<1>UW g24<8,8,1>UD 0x022cb506 - sampler MsgDesc: sampleinfo SIMD16 Surface = 6 Sampler = 5 mlen 1 rlen 2 { align1 1H }; -send(8) g14<1>UW g11<8,8,1>UD 0x0a4b0203 - sampler MsgDesc: gather4_c SIMD8 Surface = 3 Sampler = 2 mlen 5 rlen 4 { align1 1Q }; -send(8) g18<1>UW g18<8,8,1>UD 0x0c4b0304 - sampler MsgDesc: gather4_c SIMD8 Surface = 4 Sampler = 3 mlen 6 rlen 4 { align1 1Q }; -send(8) g22<1>UW g24<8,8,1>UD 0x084b0405 - sampler MsgDesc: gather4_c SIMD8 Surface = 5 Sampler = 4 mlen 4 rlen 4 { align1 1Q }; -send(16) g18<1>UW g26<8,8,1>UD 0x128d0203 - sampler MsgDesc: gather4_c SIMD16 Surface = 3 Sampler = 2 mlen 9 rlen 8 { align1 1H }; -send(16) g26<1>UW g35<8,8,1>UD 0x168d0304 - sampler MsgDesc: gather4_c SIMD16 Surface = 4 Sampler = 3 mlen 11 rlen 8 { align1 1H }; -send(16) g34<1>UW g46<8,8,1>UD 0x0e8d0405 - sampler MsgDesc: gather4_c SIMD16 Surface = 5 Sampler = 4 mlen 7 rlen 8 { align1 1H }; -send(8) g124<1>UW g9<8,8,1>UD 0x0c4b0000 - sampler MsgDesc: gather4_c SIMD8 Surface = 0 Sampler = 0 mlen 6 rlen 4 { align1 1Q }; diff --git a/src/intel/compiler/elk/tests/gen9/send.expected b/src/intel/compiler/elk/tests/gen9/send.expected deleted file mode 100644 index 9ed63c758f3..00000000000 --- a/src/intel/compiler/elk/tests/gen9/send.expected +++ /dev/null @@ -1,1803 +0,0 @@ -31 00 60 06 e0 3a 00 20 60 0f 8d 06 17 00 08 8a -31 00 60 06 e0 3a 00 20 a0 01 8d 06 07 00 08 12 -31 00 60 06 e0 3a 00 20 60 0f 8d 06 27 00 08 8a -31 00 80 09 0c 02 20 21 40 00 00 06 00 03 28 02 -31 00 60 06 e0 3a 00 20 e0 0e 8d 06 17 00 08 92 -31 00 80 07 44 12 00 20 e0 0f 8d 06 10 00 00 82 -31 00 60 02 48 02 80 2f a0 01 8d 06 01 a0 43 06 -31 00 80 02 48 02 00 2f e0 02 8d 06 01 a0 85 0c -31 00 60 06 08 02 40 21 40 00 8d 06 28 00 48 02 -31 00 60 06 e0 3a 00 20 00 01 8d 06 17 00 0a 14 -31 00 60 06 e0 3a 00 20 c0 0e 8d 06 17 00 0a 94 -31 00 60 02 48 02 40 20 40 01 8d 06 01 70 42 08 -31 00 80 02 48 02 40 20 40 02 8d 06 01 70 84 10 -31 00 60 06 e0 02 00 20 60 01 8d 06 37 00 0a 0c -31 00 60 06 e0 02 00 20 c0 00 8d 06 27 00 08 0a -31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 0c -31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 0a -31 00 60 06 e0 02 00 20 c0 00 8d 06 17 80 08 08 -31 00 60 06 e0 02 00 20 40 00 8d 06 17 80 08 06 -31 00 60 06 e0 02 00 20 c0 00 8d 06 07 80 08 0c -31 00 60 06 e0 02 00 20 c0 00 8d 06 07 80 08 0a -31 00 60 06 e0 02 00 20 a0 0f 8d 06 07 80 08 86 -31 00 60 02 48 02 e0 20 e0 00 8d 06 00 a0 43 04 -31 00 60 02 48 02 40 21 c0 00 8d 06 01 a0 22 02 -31 00 60 02 48 02 40 20 60 02 8d 06 01 80 4a 08 -31 00 80 02 48 02 20 23 00 02 8d 06 01 a0 44 04 -31 00 80 02 48 02 c0 21 e0 00 8d 06 01 80 8c 0e -31 00 60 06 e0 3a 00 20 60 01 8d 06 17 00 08 12 -31 00 60 06 e0 3a 00 20 80 02 8d 06 37 00 08 12 -31 00 60 06 e0 3a 00 20 60 0f 8d 06 57 00 08 8a -31 00 60 02 48 02 20 21 c0 00 8d 06 01 d0 13 06 -31 00 80 02 48 02 80 21 c0 01 8d 06 01 d0 25 0c -31 00 60 02 48 02 40 20 c0 01 8d 06 01 d0 43 06 -31 00 60 02 48 02 00 21 20 02 8d 06 01 e0 43 0a -31 00 80 02 48 02 40 23 40 01 8d 06 01 d0 85 0c -31 00 80 02 48 02 40 24 00 02 8d 06 01 e0 85 14 -31 00 60 02 48 02 a0 20 40 00 8d 06 01 00 32 04 -31 00 80 02 48 02 e0 20 40 00 8d 06 01 00 64 08 -31 00 60 02 48 02 80 21 40 01 8d 06 01 e0 33 0a -31 00 80 02 48 02 40 20 40 02 8d 06 01 e0 65 14 -31 00 60 02 48 02 a0 20 40 00 8d 06 01 00 42 04 -31 00 80 02 48 02 e0 20 40 00 8d 06 01 00 84 08 -31 00 60 02 48 02 60 21 20 01 8d 06 00 a0 22 02 -31 00 60 02 48 02 80 2f a0 01 8d 06 00 80 4a 06 -31 00 60 02 48 02 80 21 a0 00 8d 06 00 70 42 02 -31 00 60 06 e0 3a 00 20 60 0f 8d 06 37 00 08 8a -31 00 60 02 48 02 c0 20 60 01 8d 06 01 40 4a 14 -31 00 61 0c 4a 02 a0 2f 60 00 8d 06 01 b5 10 02 -31 00 81 0c 4a 02 40 2f 80 00 8d 06 01 a5 20 04 -31 00 60 02 48 02 c0 20 80 01 8d 06 01 40 4a 08 -31 00 60 02 48 02 40 2c 20 02 8d 06 01 c0 43 0c -31 00 60 02 48 02 80 2f 00 01 8d 06 01 80 4a 06 -31 00 80 02 48 02 00 2f 80 01 8d 06 01 80 8c 0a -31 00 60 02 48 02 c0 20 e0 00 8d 06 01 60 1a 0a -31 00 60 02 48 02 e0 20 80 01 8d 06 02 61 1a 0a -31 00 80 02 48 02 40 21 80 01 8d 06 01 60 2c 12 -31 00 80 02 48 02 80 21 a0 02 8d 06 02 61 2c 12 -31 00 60 02 48 02 80 2f 60 00 8d 06 00 e0 43 0a -31 00 60 06 e0 3a 00 20 e0 0e 8d 06 27 00 08 92 -31 00 60 02 48 02 40 20 60 00 8d 06 00 d0 43 06 -31 00 60 06 e0 02 00 20 e0 00 8d 06 37 00 08 0a -31 00 60 06 e0 02 00 20 00 01 8d 06 47 00 08 0a -31 00 60 06 e0 3a 00 20 a0 03 8d 06 17 00 0a 0c -31 00 60 06 e0 3a 00 20 40 0f 8d 06 17 00 0a 8c -31 00 60 02 48 02 a0 21 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80 21 e0 02 8d 06 06 86 4a 06 -31 00 60 02 48 02 80 21 00 04 8d 06 07 87 4a 08 -31 00 60 02 48 02 40 23 a0 01 8d 06 08 88 4a 06 -31 00 60 02 48 02 40 23 40 03 8d 06 09 09 4b 08 -31 00 60 02 48 02 40 20 40 00 8d 06 0a 0a 4b 0a -31 00 60 02 48 02 40 21 40 01 8d 06 0b 0b 4b 08 -31 00 60 06 08 02 40 20 e0 01 8d 06 48 00 3a 04 -31 00 60 06 08 02 80 21 e0 01 8d 06 58 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 68 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 78 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 88 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 98 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 a8 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 b8 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 c8 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 d8 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 e8 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 f8 00 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 08 01 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 18 01 3a 04 -31 00 60 06 08 02 40 20 40 00 8d 06 38 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8d 06 08 00 84 08 -31 00 80 02 48 02 40 25 c0 02 8d 06 09 01 84 08 -31 00 80 02 48 02 80 27 c0 02 8d 06 0a 02 84 08 -31 00 80 02 48 02 c0 28 c0 02 8d 06 0b 03 84 08 -31 00 80 02 48 02 c0 29 c0 02 8d 06 0c 04 84 08 -31 00 80 02 48 02 c0 2a c0 02 8d 06 0d 05 84 08 -31 00 80 02 48 02 c0 2b c0 02 8d 06 0e 06 84 08 -31 00 80 02 48 02 80 26 c0 02 8d 06 0f 07 84 08 -31 00 60 02 48 02 00 22 40 05 8d 06 01 81 43 04 -31 00 60 02 48 02 80 22 40 05 8d 06 02 82 43 04 -31 00 60 02 48 02 a0 23 40 05 8d 06 04 84 43 04 -31 00 60 02 48 02 c0 24 40 05 8d 06 06 86 43 04 -31 00 60 02 48 02 80 2f 40 05 8d 06 07 87 43 04 -31 00 60 06 08 02 80 21 00 02 8d 06 58 00 4a 04 -31 00 60 06 08 02 80 21 40 00 8d 06 68 00 4a 04 -31 00 60 06 08 02 80 21 40 00 8d 06 78 00 4a 04 -31 00 60 06 08 02 80 21 40 00 8d 06 88 00 4a 04 -31 00 60 06 08 02 80 21 40 00 8d 06 98 00 4a 04 -31 00 60 06 08 02 80 21 40 00 8d 06 a8 00 4a 04 -31 00 60 06 08 02 80 21 40 00 8d 06 b8 00 4a 04 -31 00 60 06 08 02 80 21 40 00 8d 06 c8 00 4a 04 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60 25 20 02 8d 06 02 51 24 14 -31 00 60 02 48 02 40 20 a0 00 8d 06 01 30 22 06 -31 00 80 02 48 02 40 20 e0 00 8d 06 01 30 44 0c -31 00 60 02 48 02 40 20 40 00 8d 06 01 30 32 06 -31 00 80 02 48 02 40 20 00 03 8d 06 01 30 64 0c -31 00 60 06 e0 3a 00 20 00 0f 8d 06 17 01 0a 8c -31 00 60 06 08 02 60 21 20 00 8d 06 28 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 38 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 48 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 58 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 68 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 78 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 88 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 98 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 a8 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 b8 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 c8 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 d8 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 e8 01 38 02 -31 00 60 06 08 02 60 21 20 00 8d 06 f8 01 38 02 -31 00 60 02 48 02 40 21 40 00 8d 06 04 00 42 04 -31 00 80 02 48 02 40 22 40 00 8d 06 04 00 84 08 -31 00 60 02 48 02 40 21 40 00 8d 06 03 00 42 04 -31 00 80 02 48 02 40 22 40 00 8d 06 03 00 84 08 -31 00 60 06 08 02 60 21 a0 01 8d 06 58 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 68 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 78 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 88 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 98 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 a8 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 b8 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 c8 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 d8 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 e8 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 f8 00 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 08 01 2a 04 -31 00 60 06 08 02 40 20 60 01 8d 06 18 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 58 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 68 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 78 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 88 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 98 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 a8 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 b8 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 c8 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 d8 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 e8 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 f8 01 2a 04 -31 00 60 06 08 02 40 20 60 00 8d 06 08 02 2a 04 -31 00 60 02 48 02 20 21 e0 01 8d 06 02 b1 1a 02 -31 00 60 02 48 02 40 21 00 02 8d 06 03 b2 1a 02 -31 00 60 02 48 02 60 21 20 02 8d 06 04 b3 1a 02 -31 00 60 02 48 02 80 21 40 02 8d 06 05 b4 1a 02 -31 00 60 02 48 02 a0 21 60 02 8d 06 06 b5 1a 02 -31 00 80 02 48 02 c0 21 00 02 8d 06 02 b1 2c 02 -31 00 80 02 48 02 00 22 40 02 8d 06 03 b2 2c 02 -31 00 80 02 48 02 40 22 80 02 8d 06 04 b3 2c 02 -31 00 80 02 48 02 80 22 c0 02 8d 06 05 b4 2c 02 -31 00 80 02 48 02 c0 22 00 03 8d 06 06 b5 2c 02 -31 00 60 02 48 02 c0 21 60 01 8d 06 03 02 4b 0a -31 00 60 02 48 02 40 22 40 02 8d 06 04 03 4b 0c -31 00 60 02 48 02 c0 22 00 03 8d 06 05 04 4b 08 -31 00 80 02 48 02 40 22 40 03 8d 06 03 02 8d 12 -31 00 80 02 48 02 40 23 60 04 8d 06 04 03 8d 16 -31 00 80 02 48 02 40 24 c0 05 8d 06 05 04 8d 0e -31 00 60 02 48 02 80 2f 20 01 8d 06 00 00 4b 0c diff --git a/src/intel/compiler/elk/tests/gen9/sendc.asm b/src/intel/compiler/elk/tests/gen9/sendc.asm deleted file mode 100644 index c340cb510a6..00000000000 --- a/src/intel/compiler/elk/tests/gen9/sendc.asm +++ /dev/null @@ -1,264 +0,0 @@ -sendc(8) null<1>UW g124<0,1,0>F 0x88031400 - render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g120<0,1,0>F 0x90031000 - render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g114<0,1,0>F 0x82031100 - render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880ba001 - sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0da001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -(+f0.1) sendc(8) null<1>UW g124<0,1,0>F 0x88031400 - render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0be001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960de001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a0001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c0001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g118<8,8,1>UD 0x940a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 10 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g125<8,8,1>UD a0<0,1,0>UD 0x80000200 - sampler MsgDesc: indirect { align1 1Q EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g121<8,8,1>UD 0x8e0bc001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g121<8,8,1>UD 0x8e0a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a2001 - sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c2001 - sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1401 - render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1001 - render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g13<0,1,0>F 0x0e0b0401 - render MsgDesc: RT write SIMD8 Surface = 1 mlen 7 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g121<0,1,0>F 0x8e0b1402 - render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g7<0,1,0>F 0x180b0001 - render MsgDesc: RT write SIMD16 Surface = 1 mlen 12 rlen 0 { align1 1H }; -sendc(16) null<1>UW g116<0,1,0>F 0x980b1002 - render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 12 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a1001 - sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c1001 - sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(1) g2<1>UW g2<0,1,0>UW 0x0209c000 - data MsgDesc: ( DC mfence, 0, 0) mlen 1 rlen 0 { align1 WE_all 1N }; -sendc(8) null<1>UW g120<8,8,1>UD 0x900b4001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0b4001 - sampler MsgDesc: sample_d_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(8) g6<1>F g2<0,1,0>UD 0x044b4100 - render MsgDesc: RT read MsgCtrl = 0x1 Surface = 0 mlen 2 rlen 4 { align1 1Q }; -sendc(16) g9<1>F g27<0,1,0>UD 0x048b4000 - render MsgDesc: RT read MsgCtrl = 0x0 Surface = 0 mlen 2 rlen 8 { align1 1H }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a3001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c3001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<0,1,0>F 0x8a031400 - render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x94031000 - render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0400 - render MsgDesc: RT write SIMD8 Surface = 0 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0401 - render MsgDesc: RT write SIMD8 Surface = 1 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0402 - render MsgDesc: RT write SIMD8 Surface = 2 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0403 - render MsgDesc: RT write SIMD8 Surface = 3 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g5<0,1,0>F 0x0c0b0404 - render MsgDesc: RT write SIMD8 Surface = 4 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1405 - render MsgDesc: RT write SIMD8 LastRT Surface = 5 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0000 - render MsgDesc: RT write SIMD16 Surface = 0 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0001 - render MsgDesc: RT write SIMD16 Surface = 1 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0002 - render MsgDesc: RT write SIMD16 Surface = 2 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0003 - render MsgDesc: RT write SIMD16 Surface = 3 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g5<0,1,0>F 0x140b0004 - render MsgDesc: RT write SIMD16 Surface = 4 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1005 - render MsgDesc: RT write SIMD16 LastRT Surface = 5 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) g6<1>F g6<0,1,0>UD 0x044b4101 - render MsgDesc: RT read MsgCtrl = 0x1 Surface = 1 mlen 2 rlen 4 { align1 1Q }; -sendc(8) g10<1>F g10<0,1,0>UD 0x044b4102 - render MsgDesc: RT read MsgCtrl = 0x1 Surface = 2 mlen 2 rlen 4 { align1 1Q }; -sendc(8) g14<1>F g14<0,1,0>UD 0x044b4103 - render MsgDesc: RT read MsgCtrl = 0x1 Surface = 3 mlen 2 rlen 4 { align1 1Q }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1403 - render MsgDesc: RT write SIMD8 LastRT Surface = 3 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) g32<1>F g14<0,1,0>UD 0x048b4001 - render MsgDesc: RT read MsgCtrl = 0x0 Surface = 1 mlen 2 rlen 8 { align1 1H }; -sendc(16) g40<1>F g16<0,1,0>UD 0x048b4002 - render MsgDesc: RT read MsgCtrl = 0x0 Surface = 2 mlen 2 rlen 8 { align1 1H }; -sendc(16) g48<1>F g18<0,1,0>UD 0x048b4003 - render MsgDesc: RT read MsgCtrl = 0x0 Surface = 3 mlen 2 rlen 8 { align1 1H }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1003 - render MsgDesc: RT write SIMD16 LastRT Surface = 3 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a1001 - sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c1001 - sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860ba001 - sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0da001 - sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g126<8,8,1>UD 0x840a0001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g125<8,8,1>UD 0x860c0001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a2001 - sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c2001 - sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0be001 - sampler MsgDesc: ld2dms SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920de001 - sampler MsgDesc: ld2dms SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g120<8,8,1>UD 0x900a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 8 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a2001 - sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c2001 - sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0304 - sampler MsgDesc: sample SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0304 - sampler MsgDesc: sample SIMD16 Surface = 4 Sampler = 3 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0a1001 - sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960c1001 - sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a3001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c3001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1402 - render MsgDesc: RT write SIMD8 LastRT Surface = 2 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1002 - render MsgDesc: RT write SIMD16 LastRT Surface = 2 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a6001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c6001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a5001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c5001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0a2001 - sampler MsgDesc: sample_l SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960c2001 - sampler MsgDesc: sample_l SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<8,8,1>UD 0x8c0bc001 - sampler MsgDesc: ld2dms_w SIMD8 Surface = 1 Sampler = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g117<8,8,1>UD 0x960dc001 - sampler MsgDesc: ld2dms_w SIMD16 Surface = 1 Sampler = 0 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1400 - render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1000 - render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a7001 - sampler MsgDesc: ld SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c7001 - sampler MsgDesc: ld SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g118<0,1,0>F 0x940b1200 - render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g3<0,1,0>F 0x140b1200 - render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g118<0,1,0>F 0x940b1300 - render MsgDesc: RT write SIMD8/DualSrcHigh LastRT Surface = 0 mlen 10 rlen 0 { align1 2Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a0001 - sampler MsgDesc: sample SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c0001 - sampler MsgDesc: sample SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(16) g11<1>F g37<0,1,0>UD 0x048b6000 - render MsgDesc: RT read MsgCtrl = 0x32 Surface = 0 mlen 2 rlen 8 { align1 1H }; -sendc(8) null<1>UW g23<0,1,0>F 0x0c0b0405 - render MsgDesc: RT write SIMD8 Surface = 5 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g29<0,1,0>F 0x0c0b0406 - render MsgDesc: RT write SIMD8 Surface = 6 mlen 6 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1407 - render MsgDesc: RT write SIMD8 LastRT Surface = 7 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g57<0,1,0>F 0x140b0005 - render MsgDesc: RT write SIMD16 Surface = 5 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g67<0,1,0>F 0x140b0006 - render MsgDesc: RT write SIMD16 Surface = 6 mlen 10 rlen 0 { align1 1H }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1007 - render MsgDesc: RT write SIMD16 LastRT Surface = 7 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a1001 - sampler MsgDesc: sample_b SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c1001 - sampler MsgDesc: sample_b SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g10<0,1,0>F 0x0e0b0400 - render MsgDesc: RT write SIMD8 Surface = 0 mlen 7 rlen 0 { align1 1Q }; -sendc(8) null<1>UW g121<0,1,0>F 0x8e0b1401 - render MsgDesc: RT write SIMD8 LastRT Surface = 1 mlen 7 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g2<0,1,0>F 0x160b0000 - render MsgDesc: RT write SIMD16 Surface = 0 mlen 11 rlen 0 { align1 1H }; -sendc(16) null<1>UW g117<0,1,0>F 0x960b1001 - render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 11 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1404 - render MsgDesc: RT write SIMD8 LastRT Surface = 4 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1004 - render MsgDesc: RT write SIMD16 LastRT Surface = 4 mlen 10 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c0b1406 - render MsgDesc: RT write SIMD8 LastRT Surface = 6 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g118<0,1,0>F 0x940b1006 - render MsgDesc: RT write SIMD16 LastRT Surface = 6 mlen 10 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g119<0,1,0>F 0x92031000 - render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g116<0,1,0>F 0x980b1001 - render MsgDesc: RT write SIMD16 LastRT Surface = 1 mlen 12 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a6001 - sampler MsgDesc: sample_l_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c6001 - sampler MsgDesc: sample_l_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g124<8,8,1>UD 0x880a5001 - sampler MsgDesc: sample_b_c SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g121<8,8,1>UD 0x8e0c5001 - sampler MsgDesc: sample_b_c SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a4001 - sampler MsgDesc: sample_d SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g123<8,8,1>UD 0x8a0a3001 - sampler MsgDesc: sample_c SIMD8 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g119<8,8,1>UD 0x920c3001 - sampler MsgDesc: sample_c SIMD16 Surface = 1 Sampler = 0 mlen 9 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0f10 - sampler MsgDesc: sample SIMD8 Surface = 16 Sampler = 15 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0f10 - sampler MsgDesc: sample SIMD16 Surface = 16 Sampler = 15 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g126<8,8,1>UD 0x840a0102 - sampler MsgDesc: sample SIMD8 Surface = 2 Sampler = 1 mlen 2 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g125<8,8,1>UD 0x860c0102 - sampler MsgDesc: sample SIMD16 Surface = 2 Sampler = 1 mlen 3 rlen 0 { align1 1H EOT }; -sendc(16) null<1>UW g11<0,1,0>F 0x180b0000 - render MsgDesc: RT write SIMD16 Surface = 0 mlen 12 rlen 0 { align1 1H }; -sendc(8) null<1>UW g122<0,1,0>F 0x8c031400 - render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 6 rlen 0 { align1 1Q EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860a0506 - sampler MsgDesc: sample SIMD8 Surface = 6 Sampler = 5 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0c0506 - sampler MsgDesc: sample SIMD16 Surface = 6 Sampler = 5 mlen 5 rlen 0 { align1 1H EOT }; -sendc(8) null<1>UW g125<8,8,1>UD 0x860b8001 - sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 0 { align1 1Q EOT }; -sendc(16) null<1>UW g123<8,8,1>UD 0x8a0d8001 - sampler MsgDesc: sample_lz SIMD16 Surface = 1 Sampler = 0 mlen 5 rlen 0 { align1 1H EOT }; diff --git a/src/intel/compiler/elk/tests/gen9/sendc.expected b/src/intel/compiler/elk/tests/gen9/sendc.expected deleted file mode 100644 index b4c30df0df2..00000000000 --- a/src/intel/compiler/elk/tests/gen9/sendc.expected +++ /dev/null @@ -1,132 +0,0 @@ -32 00 60 05 40 3a 00 20 80 0f 00 06 00 14 03 88 -32 00 80 05 40 3a 00 20 00 0f 00 06 00 10 03 90 -32 00 80 05 40 3a 00 20 40 0e 00 06 00 11 03 82 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 a0 0b 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 a0 0d 8e -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 00 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 00 0c 8a -32 00 61 05 41 3a 00 20 80 0f 00 06 00 14 03 88 -32 00 60 02 40 02 00 20 40 0f 8d 06 01 e0 0b 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 e0 0d 96 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 00 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 00 0c 8e -32 00 60 02 40 02 00 20 c0 0e 8d 06 01 40 0a 94 -32 00 60 02 40 02 00 20 a0 0f 8d 00 00 02 00 80 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 40 0a 88 -32 00 60 02 40 02 00 20 20 0f 8d 06 01 c0 0b 8e -32 00 60 02 40 02 00 20 20 0f 8d 06 01 40 0a 8e -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 20 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 20 0c 8a -32 00 60 05 40 3a 00 20 40 0f 00 06 01 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 01 10 0b 94 -32 00 60 05 40 3a 00 20 a0 01 00 06 01 04 0b 0e -32 00 60 05 40 3a 00 20 20 0f 00 06 02 14 0b 8e -32 00 80 05 40 3a 00 20 e0 00 00 06 01 00 0b 18 -32 00 80 05 40 3a 00 20 80 0e 00 06 02 10 0b 98 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 10 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 10 0c 92 -32 00 00 0a 4c 12 40 20 40 00 00 06 00 c0 09 02 -32 00 60 02 40 02 00 20 00 0f 8d 06 01 40 0b 90 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 40 0b 8a -32 00 60 05 e8 02 c0 20 40 00 00 06 00 41 4b 04 -32 00 80 05 e8 02 20 21 60 03 00 06 00 40 8b 04 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 30 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 30 0c 8e -32 00 60 05 40 3a 00 20 60 0f 00 06 00 14 03 8a -32 00 80 05 40 3a 00 20 c0 0e 00 06 00 10 03 94 -32 00 60 05 40 3a 00 20 a0 00 00 06 00 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 01 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 02 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 03 04 0b 0c -32 00 60 05 40 3a 00 20 a0 00 00 06 04 04 0b 0c -32 00 60 05 40 3a 00 20 40 0f 00 06 05 14 0b 8c -32 00 80 05 40 3a 00 20 a0 00 00 06 00 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 01 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 02 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 03 00 0b 14 -32 00 80 05 40 3a 00 20 a0 00 00 06 04 00 0b 14 -32 00 80 05 40 3a 00 20 c0 0e 00 06 05 10 0b 94 -32 00 60 05 e8 02 c0 20 c0 00 00 06 01 41 4b 04 -32 00 60 05 e8 02 40 21 40 01 00 06 02 41 4b 04 -32 00 60 05 e8 02 c0 21 c0 01 00 06 03 41 4b 04 -32 00 60 05 40 3a 00 20 40 0f 00 06 03 14 0b 8c -32 00 80 05 e8 02 00 24 c0 01 00 06 01 40 8b 04 -32 00 80 05 e8 02 00 25 00 02 00 06 02 40 8b 04 -32 00 80 05 e8 02 00 26 40 02 00 06 03 40 8b 04 -32 00 80 05 40 3a 00 20 c0 0e 00 06 03 10 0b 94 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 10 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 10 0c 8e -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 a0 0b 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 a0 0d 8a -32 00 60 02 40 02 00 20 c0 0f 8d 06 01 00 0a 84 -32 00 80 02 40 02 00 20 a0 0f 8d 06 01 00 0c 86 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 20 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 20 0c 8e -32 00 60 02 40 02 00 20 60 0f 8d 06 01 e0 0b 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 e0 0d 92 -32 00 60 02 40 02 00 20 00 0f 8d 06 01 40 0a 90 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 20 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 20 0c 92 -32 00 60 02 40 02 00 20 a0 0f 8d 06 04 03 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 04 03 0c 8a -32 00 60 02 40 02 00 20 40 0f 8d 06 01 10 0a 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 10 0c 96 -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 30 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 30 0c 8a -32 00 60 05 40 3a 00 20 40 0f 00 06 02 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 02 10 0b 94 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 60 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 60 0c 8e -32 00 60 02 40 02 00 20 60 0f 8d 06 01 50 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 50 0c 92 -32 00 60 02 40 02 00 20 40 0f 8d 06 01 20 0a 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 20 0c 96 -32 00 60 02 40 02 00 20 40 0f 8d 06 01 c0 0b 8c -32 00 80 02 40 02 00 20 a0 0e 8d 06 01 c0 0d 96 -32 00 60 05 40 3a 00 20 40 0f 00 06 00 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 00 10 0b 94 -32 00 60 02 40 02 00 20 80 0f 8d 06 01 70 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 70 0c 8e -32 00 60 05 40 3a 00 20 c0 0e 00 06 00 12 0b 94 -32 00 60 05 40 3a 00 20 60 00 00 06 00 12 0b 14 -32 10 60 05 40 3a 00 20 c0 0e 00 06 00 13 0b 94 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 00 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 00 0c 92 -32 00 80 05 e8 02 60 21 a0 04 00 06 00 60 8b 04 -32 00 60 05 40 3a 00 20 e0 02 00 06 05 04 0b 0c -32 00 60 05 40 3a 00 20 a0 03 00 06 06 04 0b 0c -32 00 60 05 40 3a 00 20 40 0f 00 06 07 14 0b 8c -32 00 80 05 40 3a 00 20 20 07 00 06 05 00 0b 14 -32 00 80 05 40 3a 00 20 60 08 00 06 06 00 0b 14 -32 00 80 05 40 3a 00 20 c0 0e 00 06 07 10 0b 94 -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 10 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 10 0c 8a -32 00 60 05 40 3a 00 20 40 01 00 06 00 04 0b 0e -32 00 60 05 40 3a 00 20 20 0f 00 06 01 14 0b 8e -32 00 80 05 40 3a 00 20 40 00 00 06 00 00 0b 16 -32 00 80 05 40 3a 00 20 a0 0e 00 06 01 10 0b 96 -32 00 60 05 40 3a 00 20 40 0f 00 06 04 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 04 10 0b 94 -32 00 60 05 40 3a 00 20 40 0f 00 06 06 14 0b 8c -32 00 80 05 40 3a 00 20 c0 0e 00 06 06 10 0b 94 -32 00 80 05 40 3a 00 20 e0 0e 00 06 00 10 03 92 -32 00 80 05 40 3a 00 20 80 0e 00 06 01 10 0b 98 -32 00 60 02 40 02 00 20 60 0f 8d 06 01 60 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 60 0c 92 -32 00 60 02 40 02 00 20 a0 0f 8d 06 02 01 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 02 01 0c 8a -32 00 60 02 40 02 00 20 80 0f 8d 06 01 50 0a 88 -32 00 80 02 40 02 00 20 20 0f 8d 06 01 50 0c 8e -32 00 60 02 40 02 00 20 60 0f 8d 06 01 40 0a 8a -32 00 60 02 40 02 00 20 60 0f 8d 06 01 30 0a 8a -32 00 80 02 40 02 00 20 e0 0e 8d 06 01 30 0c 92 -32 00 60 02 40 02 00 20 a0 0f 8d 06 10 0f 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 10 0f 0c 8a -32 00 60 02 40 02 00 20 c0 0f 8d 06 02 01 0a 84 -32 00 80 02 40 02 00 20 a0 0f 8d 06 02 01 0c 86 -32 00 80 05 40 3a 00 20 60 01 00 06 00 00 0b 18 -32 00 60 05 40 3a 00 20 40 0f 00 06 00 14 03 8c -32 00 60 02 40 02 00 20 a0 0f 8d 06 06 05 0a 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 06 05 0c 8a -32 00 60 02 40 02 00 20 a0 0f 8d 06 01 80 0b 86 -32 00 80 02 40 02 00 20 60 0f 8d 06 01 80 0d 8a diff --git a/src/intel/compiler/elk/tests/gen9/sends.asm b/src/intel/compiler/elk/tests/gen9/sends.asm deleted file mode 100644 index 9f7c8505c9c..00000000000 --- a/src/intel/compiler/elk/tests/gen9/sends.asm +++ /dev/null @@ -1,268 +0,0 @@ -sends(8) nullUD g34UD g36UD 0x04035001 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; -sends(8) nullUD g1UD g3UD 0x04036001 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q }; -sends(8) nullUD g21UD g23UD 0x04035001 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(8) g9UD g2UD g3UD 0x0210b201 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(16) g11UD g2UD g6UD 0x0420a201 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -sends(16) nullUD g6UD g8UD 0x04025efe 0x00000080 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g10UD g12UD 0x040087fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(8) nullUD g11UD g5UD 0x04035002 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g2UD g11UD 0x04036002 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g3UD g4UD 0x02026001 0x00000100 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(16) nullUD g3UD g5UD 0x04025001 0x00000200 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 2 ex_mlen 8 rlen 0 { align1 1H }; -sends(8) nullUD g2UD g3UD 0x02009b00 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 0, SIMD8, imin) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04035e01 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g45UD g41UD 0x04036e01 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04018c01 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g45UD g41UD 0x04019c01 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umax) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04018401 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g45UD g41UD 0x04019401 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04018e01 0x00000080 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 2 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g11UD g13UD 0x04019e01 0x00000080 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, cmpwr) mlen 2 ex_mlen 2 rlen 0 { align1 2Q }; -sends(16) nullUD g3UD g1UD 0x04008dfe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umin) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g5UD g1UD 0x04008bfe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imin) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g3UD g1UD 0x04008cfe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, umax) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g5UD g1UD 0x04008afe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, imax) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g3UD g1UD 0x040081fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, and) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g3UD g1UD 0x040082fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g3UD g1UD 0x040083fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, xor) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g3UD g1UD 0x040084fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(16) nullUD g3UD g7UD 0x04008efe 0x00000100 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; -sends(16) g1UD g19UD g21UD 0x0420a4fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -sends(16) g13UD g23UD g25UD 0x0420a2fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, or) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -sends(8) nullUD g14UD g10UD 0x02026000 0x00000100 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; -sends(8) nullUD g4UD g2UD 0x02026efe 0x00000040 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 254, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -sends(8) g7UD g19UD g20UD 0x0210bdfe 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g11UD g25UD g26UD 0x0210b4fe 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(16) g1UD g14UD g16UD 0x0420a7fe 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(8) nullUD g2UD g13UD a0<0>UD 0x00000100 - dp data 1 MsgDesc: indirect ex_mlen 4 { align1 1Q }; -(+f1.0) sends(8) nullUD g5UD g6UD 0x02026e01 0x00000040 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g5UD g6UD 0x02026e02 0x00000040 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(16) nullUD g6UD g8UD 0x04025e01 0x00000080 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(16) nullUD g6UD g8UD 0x04025e02 0x00000080 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(8) g3UD g8UD g9UD 0x0210b702 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(16) g4UD g11UD g13UD 0x0420a702 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(8) nullUD g5UD g3UD 0x02026c01 0x00000080 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD8, Mask = 0xc) mlen 1 ex_mlen 2 rlen 0 { align1 1Q }; -(+f1.0) sends(16) nullUD g19UD g21UD 0x04025c01 0x00000100 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 1, SIMD16, Mask = 0xc) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; -sends(8) nullUD g14UD g15UD 0x02026e00 0x00000040 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -sends(8) nullUD g16UD g9UD 0x02026c00 0x00000080 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 0, SIMD8, Mask = 0xc) mlen 1 ex_mlen 2 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g15UD g18UD 0x06035001 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 3 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g34UD g11UD 0x06036001 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 3 ex_mlen 4 rlen 0 { align1 2Q }; -(+f1.0) sends(8) g13UD g18UD g19UD 0x0210bb02 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, imin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g16UD g25UD g30UD 0x0210b402 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(16) g22UD g27UD g29UD 0x0420ab02 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, imin) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(16) g25UD g37UD g2UD 0x0420a402 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -sends(16) nullUD g8UD g10UD 0x04025c02 0x00000100 - dp data 1 MsgDesc: ( DC untyped surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; -(+f1.0) sends(8) g127UD g2UD g9UD 0x0411a401 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g127UD g2UD g4UD 0x0411b401 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, mov) mlen 2 ex_mlen 1 rlen 1 { align1 2Q }; -(+f1.0) sends(8) nullUD g14UD g15UD 0x02009201 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(16) nullUD g24UD g26UD 0x04008201 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, or) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(8) nullUD g124UD g11UD 0x04035000 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g5UD g6UD 0x02035e02 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g7UD g9UD 0x02036e02 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; -sends(8) nullUD g11UD g21UD 0x04035e00 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -sends(8) nullUD g15UD g27UD 0x04035e02 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -sends(8) nullUD g16UD g28UD 0x04036e02 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) g13UD g19UD g20UD 0x0210bd02 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(16) g22UD g28UD g30UD 0x0420ad02 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 2, SIMD16, umin) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04035c02 0x00000080 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0xc) mlen 2 ex_mlen 2 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g38UD g40UD 0x04036c02 0x00000080 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0xc) mlen 2 ex_mlen 2 rlen 0 { align1 2Q }; -sends(8) nullUD g17UD g6UD 0x02035000 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 0, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; -sends(8) g124UD g20UD g21UD 0x0211a700 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g124UD g20UD g21UD 0x0211ad00 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g124UD g20UD g21UD 0x0211ac00 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, umax) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g124UD g20UD g21UD 0x0211a100 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, and) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g124UD g20UD g21UD 0x0211a200 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, or) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g124UD g20UD g21UD 0x0211a300 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, xor) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g124UD g20UD g21UD 0x0211a400 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) g124UD g21UD g6UD 0x0211ae00 0x00000080 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 0, SIMD16, cmpwr) mlen 1 ex_mlen 2 rlen 1 { align1 1Q }; -(+f1.0) sends(8) nullUD g16UD g2UD 0x02035001 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g29UD g8UD 0x02036001 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g14UD g18UD 0x02035e01 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD16, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g23UD g7UD 0x02036e01 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 1, SIMD8, Mask = 0xe) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g17UD g2UD 0x02035002 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g28UD g3UD 0x02036002 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 2, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g17UD g2UD 0x02035003 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g23UD g6UD 0x02036003 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 1 ex_mlen 4 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g12UD g13UD 0x02009701 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(16) nullUD g20UD g22UD 0x04008701 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -sends(8) g7UD g18UD g19UD 0x0210bbfe 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 254, SIMD8, imin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -sends(8) nullUD g6UD g1UD 0x04035003 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD16, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 1Q }; -sends(8) nullUD g8UD g10UD 0x04036003 0x00000100 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 3, SIMD8, Mask = 0x0) mlen 2 ex_mlen 4 rlen 0 { align1 2Q }; -(+f1.0) sends(8) g3UD g21UD g20UD 0x0210b701 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, add) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g5UD g21UD g20UD 0x0210bd01 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g6UD g21UD g20UD 0x0210bc01 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g7UD g21UD g20UD 0x0210b101 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g9UD g21UD g20UD 0x0210b301 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g10UD g21UD g20UD 0x0210b401 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 1 ex_mlen 1 rlen 1 { align1 1Q }; -(+f1.0) sends(8) g11UD g21UD g11UD 0x0210be01 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 1 ex_mlen 2 rlen 1 { align1 1Q }; -(+f1.0) sends(16) g3UD g38UD g36UD 0x0420a701 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, add) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(16) g7UD g38UD g36UD 0x0420ad01 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(16) g9UD g38UD g36UD 0x0420ac01 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(16) g11UD g38UD g36UD 0x0420a101 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(16) g15UD g38UD g36UD 0x0420a301 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(16) g17UD g38UD g36UD 0x0420a401 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 2 rlen 2 { align1 1H }; -(+f1.0) sends(16) g19UD g38UD g21UD 0x0420ae01 0x00000100 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 2 { align1 1H }; -sends(8) nullUD g4UD g12UD 0x04035e09 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD16, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -sends(8) nullUD g5UD g13UD 0x04036e09 0x00000040 - dp data 1 MsgDesc: ( DC typed surface write, Surface = 9, SIMD8, Mask = 0xe) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g14UD g18UD 0x02009d01 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umin) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g17UD g19UD 0x02009c01 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, umax) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g19UD g20UD 0x02009101 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g27UD g22UD 0x02009301 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g29UD g23UD 0x02009401 0x00000040 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, mov) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g32UD g2UD 0x02009e01 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD8, cmpwr) mlen 1 ex_mlen 2 rlen 0 { align1 1Q }; -(+f1.0) sends(16) nullUD g18UD g32UD 0x04008d01 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(16) nullUD g24UD g33UD 0x04008c01 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, umax) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(16) nullUD g30UD g34UD 0x04008101 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, and) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(16) nullUD g46UD g36UD 0x04008301 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(16) nullUD g49UD g37UD 0x04008401 0x00000080 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, mov) mlen 2 ex_mlen 2 rlen 0 { align1 1H }; -(+f1.0) sends(16) nullUD g56UD g2UD 0x04008e01 0x00000100 - dp data 1 MsgDesc: ( DC untyped atomic op, Surface = 1, SIMD16, cmpwr) mlen 2 ex_mlen 4 rlen 0 { align1 1H }; -(+f1.0) sends(8) nullUD g20UD g21UD 0x02018101 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g3UD g38UD 0x02019101 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g19UD g20UD 0x02018201 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g3UD g36UD 0x02019201 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g19UD g20UD 0x02018301 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 1 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g3UD g36UD 0x02019301 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 1 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g18UD 0x04018701 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, add) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04019701 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, add) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g18UD 0x04018d01 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, umin) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04019d01 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, umin) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g18UD 0x04018101 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, and) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04019101 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, and) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g18UD 0x04018201 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, or) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04019201 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, or) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; -(+f1.0) sends(8) nullUD g2UD g18UD 0x04018301 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD16, xor) mlen 2 ex_mlen 1 rlen 0 { align1 1Q }; -(+f1.0) sends(8) nullUD g2UD g4UD 0x04019301 0x00000040 - dp data 1 MsgDesc: ( DC typed atomic, Surface = 1, SIMD8, xor) mlen 2 ex_mlen 1 rlen 0 { align1 2Q }; diff --git a/src/intel/compiler/elk/tests/gen9/sends.expected b/src/intel/compiler/elk/tests/gen9/sends.expected deleted file mode 100644 index ff7a1235086..00000000000 --- a/src/intel/compiler/elk/tests/gen9/sends.expected +++ /dev/null @@ -1,134 +0,0 @@ -33 00 60 0c 10 40 02 00 44 04 00 00 01 50 03 04 -33 10 60 0c 10 30 00 00 24 00 00 00 01 60 03 04 -33 00 60 0c 10 70 01 00 a4 02 00 00 01 50 03 04 -33 00 61 0c 1a 30 20 01 41 00 00 00 01 b2 10 02 -33 00 81 0c 1a 60 60 01 42 00 00 00 01 a2 20 04 -33 00 80 0c 10 80 00 00 c2 00 00 00 fe 5e 02 04 -33 00 80 0c 10 c0 00 00 42 01 00 00 fe 87 00 04 -33 00 61 0c 12 50 00 00 64 01 00 00 02 50 03 04 -33 10 61 0c 12 b0 00 00 44 00 00 00 02 60 03 04 -33 00 61 0c 12 40 00 00 64 00 00 00 01 60 02 02 -33 00 81 0c 12 50 00 00 68 00 00 00 01 50 02 04 -33 00 60 0c 10 30 00 00 41 00 00 00 00 9b 00 02 -33 00 61 0c 12 40 00 00 41 00 00 00 01 5e 03 04 -33 10 61 0c 12 90 02 00 a1 05 00 00 01 6e 03 04 -33 00 61 0c 12 40 00 00 41 00 00 00 01 8c 01 04 -33 10 61 0c 12 90 02 00 a1 05 00 00 01 9c 01 04 -33 00 61 0c 12 40 00 00 41 00 00 00 01 84 01 04 -33 10 61 0c 12 90 02 00 a1 05 00 00 01 94 01 04 -33 00 61 0c 12 40 00 00 42 00 00 00 01 8e 01 04 -33 10 61 0c 12 d0 00 00 62 01 00 00 01 9e 01 04 -33 00 80 0c 10 10 00 00 62 00 00 00 fe 8d 00 04 -33 00 80 0c 10 10 00 00 a2 00 00 00 fe 8b 00 04 -33 00 80 0c 10 10 00 00 62 00 00 00 fe 8c 00 04 -33 00 80 0c 10 10 00 00 a2 00 00 00 fe 8a 00 04 -33 00 80 0c 10 10 00 00 62 00 00 00 fe 81 00 04 -33 00 80 0c 10 10 00 00 62 00 00 00 fe 82 00 04 -33 00 80 0c 10 10 00 00 62 00 00 00 fe 83 00 04 -33 00 80 0c 10 10 00 00 62 00 00 00 fe 84 00 04 -33 00 80 0c 10 70 00 00 64 00 00 00 fe 8e 00 04 -33 00 80 0c 18 50 21 00 62 02 00 00 fe a4 20 04 -33 00 80 0c 18 90 a1 01 e2 02 00 00 fe a2 20 04 -33 00 60 0c 10 a0 00 00 c4 01 00 00 00 60 02 02 -33 00 60 0c 10 20 00 00 81 00 00 00 fe 6e 02 02 -33 00 60 0c 18 40 e1 00 61 02 00 00 fe bd 10 02 -33 00 60 0c 18 a0 61 01 21 03 00 00 fe b4 10 02 -33 00 80 0c 18 00 21 00 c2 01 00 00 fe a7 20 04 -33 00 61 0c 12 d0 00 00 44 20 00 00 00 00 00 00 -33 00 61 0c 12 60 00 00 a1 00 00 00 01 6e 02 02 -33 00 61 0c 12 60 00 00 a1 00 00 00 02 6e 02 02 -33 00 81 0c 12 80 00 00 c2 00 00 00 01 5e 02 04 -33 00 81 0c 12 80 00 00 c2 00 00 00 02 5e 02 04 -33 00 61 0c 1a 90 60 00 01 01 00 00 02 b7 10 02 -33 00 81 0c 1a d0 80 00 62 01 00 00 02 a7 20 04 -33 00 61 0c 12 30 00 00 a2 00 00 00 01 6c 02 02 -33 00 81 0c 12 50 01 00 64 02 00 00 01 5c 02 04 -33 00 60 0c 10 f0 00 00 c1 01 00 00 00 6e 02 02 -33 00 60 0c 10 90 00 00 02 02 00 00 00 6c 02 02 -33 00 61 0c 12 20 01 00 e4 01 00 00 01 50 03 06 -33 10 61 0c 12 b0 00 00 44 04 00 00 01 60 03 06 -33 00 61 0c 1a 30 a1 01 41 02 00 00 02 bb 10 02 -33 00 61 0c 1a e0 01 02 21 03 00 00 02 b4 10 02 -33 00 81 0c 1a d0 c1 02 62 03 00 00 02 ab 20 04 -33 00 81 0c 1a 20 20 03 a2 04 00 00 02 a4 20 04 -33 00 80 0c 10 a0 00 00 04 01 00 00 02 5c 02 04 -33 00 61 0c 1a 90 e0 0f 41 00 00 00 01 a4 11 04 -33 10 61 0c 1a 40 e0 0f 41 00 00 00 01 b4 11 04 -33 00 61 0c 12 f0 00 00 c1 01 00 00 01 92 00 02 -33 00 81 0c 12 a0 01 00 02 03 00 00 01 82 00 04 -33 00 60 0c 10 b0 00 00 84 0f 00 00 00 50 03 04 -33 00 61 0c 12 60 00 00 a1 00 00 00 02 5e 03 02 -33 10 61 0c 12 90 00 00 e1 00 00 00 02 6e 03 02 -33 00 60 0c 10 50 01 00 61 01 00 00 00 5e 03 04 -33 00 60 0c 10 b0 01 00 e1 01 00 00 02 5e 03 04 -33 10 60 0c 10 c0 01 00 01 02 00 00 02 6e 03 04 -33 00 61 0c 1a 40 a1 01 61 02 00 00 02 bd 10 02 -33 00 81 0c 1a e0 c1 02 82 03 00 00 02 ad 20 04 -33 00 61 0c 12 40 00 00 42 00 00 00 02 5c 03 04 -33 10 61 0c 12 80 02 00 c2 04 00 00 02 6c 03 04 -33 00 60 0c 10 60 00 00 24 02 00 00 00 50 03 02 -33 00 60 0c 18 50 81 0f 81 02 00 00 00 a7 11 02 -33 00 60 0c 18 50 81 0f 81 02 00 00 00 ad 11 02 -33 00 60 0c 18 50 81 0f 81 02 00 00 00 ac 11 02 -33 00 60 0c 18 50 81 0f 81 02 00 00 00 a1 11 02 -33 00 60 0c 18 50 81 0f 81 02 00 00 00 a2 11 02 -33 00 60 0c 18 50 81 0f 81 02 00 00 00 a3 11 02 -33 00 60 0c 18 50 81 0f 81 02 00 00 00 a4 11 02 -33 00 60 0c 18 60 80 0f a2 02 00 00 00 ae 11 02 -33 00 61 0c 12 20 00 00 04 02 00 00 01 50 03 02 -33 10 61 0c 12 80 00 00 a4 03 00 00 01 60 03 02 -33 00 61 0c 12 20 01 00 c1 01 00 00 01 5e 03 02 -33 10 61 0c 12 70 00 00 e1 02 00 00 01 6e 03 02 -33 00 61 0c 12 20 00 00 24 02 00 00 02 50 03 02 -33 10 61 0c 12 30 00 00 84 03 00 00 02 60 03 02 -33 00 61 0c 12 20 00 00 24 02 00 00 03 50 03 02 -33 10 61 0c 12 60 00 00 e4 02 00 00 03 60 03 02 -33 00 61 0c 12 d0 00 00 81 01 00 00 01 97 00 02 -33 00 81 0c 12 60 01 00 82 02 00 00 01 87 00 04 -33 00 60 0c 18 30 e1 00 41 02 00 00 fe bb 10 02 -33 00 60 0c 10 10 00 00 c4 00 00 00 03 50 03 04 -33 10 60 0c 10 a0 00 00 04 01 00 00 03 60 03 04 -33 00 61 0c 1a 40 61 00 a1 02 00 00 01 b7 10 02 -33 00 61 0c 1a 40 a1 00 a1 02 00 00 01 bd 10 02 -33 00 61 0c 1a 40 c1 00 a1 02 00 00 01 bc 10 02 -33 00 61 0c 1a 40 e1 00 a1 02 00 00 01 b1 10 02 -33 00 61 0c 1a 40 21 01 a1 02 00 00 01 b3 10 02 -33 00 61 0c 1a 40 41 01 a1 02 00 00 01 b4 10 02 -33 00 61 0c 1a b0 60 01 a2 02 00 00 01 be 10 02 -33 00 81 0c 1a 40 62 00 c2 04 00 00 01 a7 20 04 -33 00 81 0c 1a 40 e2 00 c2 04 00 00 01 ad 20 04 -33 00 81 0c 1a 40 22 01 c2 04 00 00 01 ac 20 04 -33 00 81 0c 1a 40 62 01 c2 04 00 00 01 a1 20 04 -33 00 81 0c 1a 40 e2 01 c2 04 00 00 01 a3 20 04 -33 00 81 0c 1a 40 22 02 c2 04 00 00 01 a4 20 04 -33 00 81 0c 1a 50 61 02 c4 04 00 00 01 ae 20 04 -33 00 60 0c 10 c0 00 00 81 00 00 00 09 5e 03 04 -33 10 60 0c 10 d0 00 00 a1 00 00 00 09 6e 03 04 -33 00 61 0c 12 20 01 00 c1 01 00 00 01 9d 00 02 -33 00 61 0c 12 30 01 00 21 02 00 00 01 9c 00 02 -33 00 61 0c 12 40 01 00 61 02 00 00 01 91 00 02 -33 00 61 0c 12 60 01 00 61 03 00 00 01 93 00 02 -33 00 61 0c 12 70 01 00 a1 03 00 00 01 94 00 02 -33 00 61 0c 12 20 00 00 02 04 00 00 01 9e 00 02 -33 00 81 0c 12 00 02 00 42 02 00 00 01 8d 00 04 -33 00 81 0c 12 10 02 00 02 03 00 00 01 8c 00 04 -33 00 81 0c 12 20 02 00 c2 03 00 00 01 81 00 04 -33 00 81 0c 12 40 02 00 c2 05 00 00 01 83 00 04 -33 00 81 0c 12 50 02 00 22 06 00 00 01 84 00 04 -33 00 81 0c 12 20 00 00 04 07 00 00 01 8e 00 04 -33 00 61 0c 12 50 01 00 81 02 00 00 01 81 01 02 -33 10 61 0c 12 60 02 00 61 00 00 00 01 91 01 02 -33 00 61 0c 12 40 01 00 61 02 00 00 01 82 01 02 -33 10 61 0c 12 40 02 00 61 00 00 00 01 92 01 02 -33 00 61 0c 12 40 01 00 61 02 00 00 01 83 01 02 -33 10 61 0c 12 40 02 00 61 00 00 00 01 93 01 02 -33 00 61 0c 12 20 01 00 41 00 00 00 01 87 01 04 -33 10 61 0c 12 40 00 00 41 00 00 00 01 97 01 04 -33 00 61 0c 12 20 01 00 41 00 00 00 01 8d 01 04 -33 10 61 0c 12 40 00 00 41 00 00 00 01 9d 01 04 -33 00 61 0c 12 20 01 00 41 00 00 00 01 81 01 04 -33 10 61 0c 12 40 00 00 41 00 00 00 01 91 01 04 -33 00 61 0c 12 20 01 00 41 00 00 00 01 82 01 04 -33 10 61 0c 12 40 00 00 41 00 00 00 01 92 01 04 -33 00 61 0c 12 20 01 00 41 00 00 00 01 83 01 04 -33 10 61 0c 12 40 00 00 41 00 00 00 01 93 01 04 diff --git a/src/intel/compiler/elk/tests/gen9/shl.asm b/src/intel/compiler/elk/tests/gen9/shl.asm deleted file mode 100644 index 03484a216db..00000000000 --- a/src/intel/compiler/elk/tests/gen9/shl.asm +++ /dev/null @@ -1,13 +0,0 @@ -shl(16) g18<1>D g20<8,8,1>D 0x00000002UD { align1 1H }; -shl(8) g18<1>D g17<8,8,1>D 0x00000002UD { align1 1Q }; -shl(1) g8<1>UD g5<0,1,0>UD 0x00000008UD { align1 WE_all 1N }; -shl(8) g4<1>UD g6<8,8,1>UD g3<8,8,1>UD { align1 1Q }; -shl(1) a0<1>UD g43<0,1,0>UD 0x00000002UD { align1 WE_all 1N }; -shl(16) g116<1>D g1<0,1,0>D 0x00000005UD { align1 2H }; -shl(8) g26<1>UD g34<8,8,1>UW 0x00000002UD { align1 1Q }; -shl(8) g3<1>UD g23<8,8,1>UD g21<8,8,1>UD { align1 WE_all 1Q }; -shl(16) g10<1>UD g10<8,8,1>UD 0x00000010UD { align1 1H }; -shl(1) g14<1>UD g21<0,1,0>UD 0x00000008UD { align1 WE_all 3N }; -shl(8) g11<1>Q g5<4,4,1>Q g3<4,4,1>UD { align1 1Q }; -shl(1) a0<1>UD g13<0,1,0>D 0x00000002UD { align1 WE_all 1N }; -shl(8) g22<1>Q g8<4,4,1>Q g4<4,4,1>UD { align1 2Q }; diff --git a/src/intel/compiler/elk/tests/gen9/shl.expected b/src/intel/compiler/elk/tests/gen9/shl.expected deleted file mode 100644 index 0b09a78762d..00000000000 --- a/src/intel/compiler/elk/tests/gen9/shl.expected +++ /dev/null @@ -1,13 +0,0 @@ -09 00 80 00 28 0a 40 22 80 02 8d 06 02 00 00 00 -09 00 60 00 28 0a 40 22 20 02 8d 06 02 00 00 00 -09 00 00 00 0c 02 00 21 a0 00 00 06 08 00 00 00 -09 00 60 00 08 02 80 20 c0 00 8d 02 60 00 8d 00 -09 00 00 00 04 02 00 22 60 05 00 06 02 00 00 00 -09 20 80 00 28 0a 80 2e 20 00 00 06 05 00 00 00 -09 00 60 00 08 12 40 23 40 04 8d 06 02 00 00 00 -09 00 60 00 0c 02 60 20 e0 02 8d 02 a0 02 8d 00 -09 00 80 00 08 02 40 21 40 01 8d 06 10 00 00 00 -09 10 00 00 0c 02 c0 21 a0 02 00 06 08 00 00 00 -09 00 60 00 28 4b 60 21 a0 00 69 02 60 00 69 00 -09 00 00 00 04 0a 00 22 a0 01 00 06 02 00 00 00 -09 10 60 00 28 4b c0 22 00 01 69 02 80 00 69 00 diff --git a/src/intel/compiler/elk/tests/gen9/shr.asm b/src/intel/compiler/elk/tests/gen9/shr.asm deleted file mode 100644 index f64c61767d2..00000000000 --- a/src/intel/compiler/elk/tests/gen9/shr.asm +++ /dev/null @@ -1,8 +0,0 @@ -shr(8) g20<1>UD g19<8,8,1>UD 0x00000001UD { align1 1Q }; -shr(16) g43<1>UD g41<8,8,1>UD 0x00000001UD { align1 1H }; -shr.z.f0.0(8) g3<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q }; -shr(16) g8<1>UW g1<1,8,0>UB 0x44440000V { align1 1H }; -shr.z.f0.0(8) null<1>UD g1<8,8,1>UD 0x0000001bUD { align1 1Q }; -shr(8) g3<1>UW g1.28<1,8,0>UB 0x76543210V { align1 1Q }; -shr(8) g3<2>UW g5<8,8,1>UD g4<8,8,1>UW { align1 1Q }; -shr(16) g20<2>UW g15<8,8,1>UD g13<8,8,1>UW { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/shr.expected b/src/intel/compiler/elk/tests/gen9/shr.expected deleted file mode 100644 index 58830ed506a..00000000000 --- a/src/intel/compiler/elk/tests/gen9/shr.expected +++ /dev/null @@ -1,8 +0,0 @@ -08 00 60 00 08 02 80 22 60 02 8d 06 01 00 00 00 -08 00 80 00 08 02 60 25 20 05 8d 06 01 00 00 00 -08 00 60 01 08 02 60 20 20 00 8d 06 1b 00 00 00 -08 00 80 00 48 22 00 21 20 00 2c 36 00 00 44 44 -08 00 60 01 00 02 00 20 20 00 8d 06 1b 00 00 00 -08 00 60 00 48 22 60 20 3c 00 2c 36 10 32 54 76 -08 00 60 00 48 02 60 40 a0 00 8d 12 80 00 8d 00 -08 00 80 00 48 02 80 42 e0 01 8d 12 a0 01 8d 00 diff --git a/src/intel/compiler/elk/tests/gen9/wait.asm b/src/intel/compiler/elk/tests/gen9/wait.asm deleted file mode 100644 index 864acd0a8e0..00000000000 --- a/src/intel/compiler/elk/tests/gen9/wait.asm +++ /dev/null @@ -1,3 +0,0 @@ -wait(1) n0<1>UD { align1 WE_all 1N }; -wait(1) n0.1<1>UD { align1 WE_all 1N }; -wait(1) n0.2<1>UD { align1 WE_all 1N }; diff --git a/src/intel/compiler/elk/tests/gen9/wait.expected b/src/intel/compiler/elk/tests/gen9/wait.expected deleted file mode 100644 index 31565e5049f..00000000000 --- a/src/intel/compiler/elk/tests/gen9/wait.expected +++ /dev/null @@ -1,3 +0,0 @@ -30 00 00 00 04 00 00 32 00 12 00 38 00 00 8d 00 -30 00 00 00 04 00 04 32 04 12 00 38 00 00 8d 00 -30 00 00 00 04 00 08 32 08 12 00 38 00 00 8d 00 diff --git a/src/intel/compiler/elk/tests/gen9/while.asm b/src/intel/compiler/elk/tests/gen9/while.asm deleted file mode 100644 index 7aaae755391..00000000000 --- a/src/intel/compiler/elk/tests/gen9/while.asm +++ /dev/null @@ -1,5 +0,0 @@ -LABEL0: -while(8) JIP: LABEL0 { align1 1Q }; -while(16) JIP: LABEL0 { align1 1H }; -(-f0.0) while(8) JIP: LABEL0 { align1 1Q }; -(-f0.0) while(16) JIP: LABEL0 { align1 1H }; diff --git a/src/intel/compiler/elk/tests/gen9/while.expected b/src/intel/compiler/elk/tests/gen9/while.expected deleted file mode 100644 index 8b6c4da652f..00000000000 --- a/src/intel/compiler/elk/tests/gen9/while.expected +++ /dev/null @@ -1,4 +0,0 @@ -27 00 60 00 20 0e 00 20 00 00 00 08 00 00 00 00 -27 00 80 00 20 0e 00 20 00 00 00 08 f0 ff ff ff -27 00 71 00 20 0e 00 20 00 00 00 08 e0 ff ff ff -27 00 91 00 20 0e 00 20 00 00 00 08 d0 ff ff ff diff --git a/src/intel/compiler/elk/tests/gen9/xor.asm b/src/intel/compiler/elk/tests/gen9/xor.asm deleted file mode 100644 index bc4c05456ef..00000000000 --- a/src/intel/compiler/elk/tests/gen9/xor.asm +++ /dev/null @@ -1,2 +0,0 @@ -xor(16) g3<1>UD g1<0,1,0>UD g1.1<0,1,0>UD { align1 1H }; -xor(8) g4<1>UD g5.6<0,1,0>UD ~g5.7<0,1,0>D { align1 1Q }; diff --git a/src/intel/compiler/elk/tests/gen9/xor.expected b/src/intel/compiler/elk/tests/gen9/xor.expected deleted file mode 100644 index 2e27e335dd8..00000000000 --- a/src/intel/compiler/elk/tests/gen9/xor.expected +++ /dev/null @@ -1,2 +0,0 @@ -07 00 80 00 08 02 60 20 20 00 00 02 24 00 00 00 -07 00 60 00 08 02 80 20 b8 00 00 0a bc 40 00 00