mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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freedreno: update generated headers
Mostly to pull in perf ctrs. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
2a7ceb5957
commit
dcb69185a0
5 changed files with 1355 additions and 30 deletions
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@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2015-11-24 14:39:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15149 bytes, from 2015-11-20 16:22:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 69600 bytes, from 2015-11-24 14:39:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 67220 bytes, from 2015-12-13 17:58:09)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109858 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
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Copyright (C) 2013-2015 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2015-11-24 14:39:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15149 bytes, from 2015-11-20 16:22:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 69600 bytes, from 2015-11-24 14:39:00)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 67220 bytes, from 2015-12-13 17:58:09)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109858 bytes, from 2016-02-10 17:07:21)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
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Copyright (C) 2013-2015 by the following authors:
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Copyright (C) 2013-2016 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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@ -255,11 +256,273 @@ enum a3xx_color_fmt {
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RB_R32G32B32A32_UINT = 59,
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};
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enum a3xx_cp_perfcounter_select {
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CP_ALWAYS_COUNT = 0,
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CP_AHB_PFPTRANS_WAIT = 3,
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CP_AHB_NRTTRANS_WAIT = 6,
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CP_CSF_NRT_READ_WAIT = 8,
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CP_CSF_I1_FIFO_FULL = 9,
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CP_CSF_I2_FIFO_FULL = 10,
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CP_CSF_ST_FIFO_FULL = 11,
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CP_RESERVED_12 = 12,
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CP_CSF_RING_ROQ_FULL = 13,
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CP_CSF_I1_ROQ_FULL = 14,
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CP_CSF_I2_ROQ_FULL = 15,
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CP_CSF_ST_ROQ_FULL = 16,
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CP_RESERVED_17 = 17,
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CP_MIU_TAG_MEM_FULL = 18,
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CP_MIU_NRT_WRITE_STALLED = 22,
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CP_MIU_NRT_READ_STALLED = 23,
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CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
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CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
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CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
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CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
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CP_ME_MICRO_RB_STARVED = 30,
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CP_AHB_RBBM_DWORD_SENT = 40,
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CP_ME_BUSY_CLOCKS = 41,
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CP_ME_WAIT_CONTEXT_AVAIL = 42,
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CP_PFP_TYPE0_PACKET = 43,
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CP_PFP_TYPE3_PACKET = 44,
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CP_CSF_RB_WPTR_NEQ_RPTR = 45,
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CP_CSF_I1_SIZE_NEQ_ZERO = 46,
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CP_CSF_I2_SIZE_NEQ_ZERO = 47,
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CP_CSF_RBI1I2_FETCHING = 48,
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};
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enum a3xx_gras_tse_perfcounter_select {
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GRAS_TSEPERF_INPUT_PRIM = 0,
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GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
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GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
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GRAS_TSEPERF_CLIPPED_PRIM = 3,
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GRAS_TSEPERF_NEW_PRIM = 4,
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GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
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GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
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GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
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GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
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GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
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GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
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GRAS_TSEPERF_POST_CLIP_PRIM = 11,
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GRAS_TSEPERF_WORKING_CYCLES = 12,
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GRAS_TSEPERF_PC_STARVE = 13,
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GRAS_TSERASPERF_STALL = 14,
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};
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enum a3xx_gras_ras_perfcounter_select {
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GRAS_RASPERF_16X16_TILES = 0,
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GRAS_RASPERF_8X8_TILES = 1,
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GRAS_RASPERF_4X4_TILES = 2,
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GRAS_RASPERF_WORKING_CYCLES = 3,
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GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
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GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
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GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
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};
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enum a3xx_hlsq_perfcounter_select {
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HLSQ_PERF_SP_VS_CONSTANT = 0,
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HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
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HLSQ_PERF_SP_FS_CONSTANT = 2,
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HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
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HLSQ_PERF_TP_STATE = 4,
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HLSQ_PERF_QUADS = 5,
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HLSQ_PERF_PIXELS = 6,
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HLSQ_PERF_VERTICES = 7,
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HLSQ_PERF_FS8_THREADS = 8,
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HLSQ_PERF_FS16_THREADS = 9,
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HLSQ_PERF_FS32_THREADS = 10,
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HLSQ_PERF_VS8_THREADS = 11,
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HLSQ_PERF_VS16_THREADS = 12,
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HLSQ_PERF_SP_VS_DATA_BYTES = 13,
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HLSQ_PERF_SP_FS_DATA_BYTES = 14,
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HLSQ_PERF_ACTIVE_CYCLES = 15,
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HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
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HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
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HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
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HLSQ_PERF_STALL_CYCLES_UCHE = 19,
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HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
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HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
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HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
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HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
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HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
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HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
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HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
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HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
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HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
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};
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enum a3xx_pc_perfcounter_select {
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PC_PCPERF_VISIBILITY_STREAMS = 0,
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PC_PCPERF_TOTAL_INSTANCES = 1,
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PC_PCPERF_PRIMITIVES_PC_VPC = 2,
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PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
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PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
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PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
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PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
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PC_PCPERF_VERTICES_TO_VFD = 7,
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PC_PCPERF_REUSED_VERTICES = 8,
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PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
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PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
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PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
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PC_PCPERF_CYCLES_IS_WORKING = 12,
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};
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enum a3xx_rb_perfcounter_select {
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RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
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RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
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RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
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RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
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RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
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RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
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RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
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RB_RBPERF_RB_MARB_DATA = 7,
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RB_RBPERF_SP_RB_QUAD = 8,
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RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
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RB_RBPERF_GMEM_CH0_READ = 10,
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RB_RBPERF_GMEM_CH1_READ = 11,
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RB_RBPERF_GMEM_CH0_WRITE = 12,
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RB_RBPERF_GMEM_CH1_WRITE = 13,
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RB_RBPERF_CP_CONTEXT_DONE = 14,
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RB_RBPERF_CP_CACHE_FLUSH = 15,
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RB_RBPERF_CP_ZPASS_DONE = 16,
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};
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enum a3xx_rbbm_perfcounter_select {
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RBBM_ALAWYS_ON = 0,
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RBBM_VBIF_BUSY = 1,
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RBBM_TSE_BUSY = 2,
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RBBM_RAS_BUSY = 3,
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RBBM_PC_DCALL_BUSY = 4,
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RBBM_PC_VSD_BUSY = 5,
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RBBM_VFD_BUSY = 6,
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RBBM_VPC_BUSY = 7,
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RBBM_UCHE_BUSY = 8,
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RBBM_VSC_BUSY = 9,
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RBBM_HLSQ_BUSY = 10,
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RBBM_ANY_RB_BUSY = 11,
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RBBM_ANY_TEX_BUSY = 12,
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RBBM_ANY_USP_BUSY = 13,
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RBBM_ANY_MARB_BUSY = 14,
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RBBM_ANY_ARB_BUSY = 15,
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RBBM_AHB_STATUS_BUSY = 16,
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RBBM_AHB_STATUS_STALLED = 17,
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RBBM_AHB_STATUS_TXFR = 18,
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RBBM_AHB_STATUS_TXFR_SPLIT = 19,
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RBBM_AHB_STATUS_TXFR_ERROR = 20,
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RBBM_AHB_STATUS_LONG_STALL = 21,
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RBBM_RBBM_STATUS_MASKED = 22,
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};
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enum a3xx_sp_perfcounter_select {
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SP_LM_LOAD_INSTRUCTIONS = 0,
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SP_LM_STORE_INSTRUCTIONS = 1,
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SP_LM_ATOMICS = 2,
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SP_UCHE_LOAD_INSTRUCTIONS = 3,
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SP_UCHE_STORE_INSTRUCTIONS = 4,
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SP_UCHE_ATOMICS = 5,
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SP_VS_TEX_INSTRUCTIONS = 6,
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SP_VS_CFLOW_INSTRUCTIONS = 7,
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SP_VS_EFU_INSTRUCTIONS = 8,
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SP_VS_FULL_ALU_INSTRUCTIONS = 9,
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SP_VS_HALF_ALU_INSTRUCTIONS = 10,
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SP_FS_TEX_INSTRUCTIONS = 11,
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SP_FS_CFLOW_INSTRUCTIONS = 12,
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SP_FS_EFU_INSTRUCTIONS = 13,
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SP_FS_FULL_ALU_INSTRUCTIONS = 14,
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SP0_ICL1_MISSES = 26,
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SP_FS_HALF_ALU_INSTRUCTIONS = 15,
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SP_FS_BARY_INSTRUCTIONS = 16,
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SP_VS_INSTRUCTIONS = 17,
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SP_FS_INSTRUCTIONS = 18,
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SP_ADDR_LOCK_COUNT = 19,
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SP_UCHE_READ_TRANS = 20,
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SP_UCHE_WRITE_TRANS = 21,
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SP_EXPORT_VPC_TRANS = 22,
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SP_EXPORT_RB_TRANS = 23,
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SP_PIXELS_KILLED = 24,
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SP_ICL1_REQUESTS = 25,
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SP_ICL1_MISSES = 26,
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SP_ICL0_REQUESTS = 27,
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SP_ICL0_MISSES = 28,
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SP_ALU_ACTIVE_CYCLES = 29,
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SP_EFU_ACTIVE_CYCLES = 30,
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SP_STALL_CYCLES_BY_VPC = 31,
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SP_STALL_CYCLES_BY_TP = 32,
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SP_STALL_CYCLES_BY_UCHE = 33,
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SP_STALL_CYCLES_BY_RB = 34,
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SP_ACTIVE_CYCLES_ANY = 35,
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SP_ACTIVE_CYCLES_ALL = 36,
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};
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enum a3xx_tp_perfcounter_select {
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TPL1_TPPERF_L1_REQUESTS = 0,
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TPL1_TPPERF_TP0_L1_REQUESTS = 1,
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TPL1_TPPERF_TP0_L1_MISSES = 2,
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TPL1_TPPERF_TP1_L1_REQUESTS = 3,
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TPL1_TPPERF_TP1_L1_MISSES = 4,
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TPL1_TPPERF_TP2_L1_REQUESTS = 5,
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TPL1_TPPERF_TP2_L1_MISSES = 6,
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TPL1_TPPERF_TP3_L1_REQUESTS = 7,
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TPL1_TPPERF_TP3_L1_MISSES = 8,
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TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
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TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
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TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
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TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
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TPL1_TPPERF_BILINEAR_OPS = 13,
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TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
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TPL1_TPPERF_QUADQUADS_SHADOW = 15,
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TPL1_TPPERF_QUADS_ARRAY = 16,
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TPL1_TPPERF_QUADS_PROJECTION = 17,
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TPL1_TPPERF_QUADS_GRADIENT = 18,
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TPL1_TPPERF_QUADS_1D2D = 19,
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TPL1_TPPERF_QUADS_3DCUBE = 20,
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TPL1_TPPERF_ZERO_LOD = 21,
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TPL1_TPPERF_OUTPUT_TEXELS = 22,
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TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
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TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
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TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
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TPL1_TPPERF_LATENCY = 26,
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TPL1_TPPERF_LATENCY_TRANS = 27,
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};
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enum a3xx_vfd_perfcounter_select {
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VFD_PERF_UCHE_BYTE_FETCHED = 0,
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VFD_PERF_UCHE_TRANS = 1,
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VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
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VFD_PERF_FETCH_INSTRUCTIONS = 3,
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VFD_PERF_DECODE_INSTRUCTIONS = 4,
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VFD_PERF_ACTIVE_CYCLES = 5,
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VFD_PERF_STALL_CYCLES_UCHE = 6,
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VFD_PERF_STALL_CYCLES_HLSQ = 7,
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VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
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VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
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};
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enum a3xx_vpc_perfcounter_select {
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VPC_PERF_SP_LM_PRIMITIVES = 0,
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VPC_PERF_COMPONENTS_FROM_SP = 1,
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VPC_PERF_SP_LM_COMPONENTS = 2,
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VPC_PERF_ACTIVE_CYCLES = 3,
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VPC_PERF_STALL_CYCLES_LM = 4,
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VPC_PERF_STALL_CYCLES_RAS = 5,
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};
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enum a3xx_uche_perfcounter_select {
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UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
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UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
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UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
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UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
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UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
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UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
|
||||
UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
|
||||
UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
|
||||
UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
|
||||
UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
|
||||
UCHE_UCHEPERF_EVICTS = 16,
|
||||
UCHE_UCHEPERF_FLUSHES = 17,
|
||||
UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
|
||||
UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
|
||||
UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
|
||||
};
|
||||
|
||||
enum a3xx_rb_blend_opcode {
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2015-11-24 14:39:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15149 bytes, from 2015-11-20 16:22:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 69600 bytes, from 2015-11-24 14:39:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 67220 bytes, from 2015-12-13 17:58:09)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109858 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
|
|||
|
|
@ -9,16 +9,17 @@ git clone https://github.com/freedreno/envytools.git
|
|||
|
||||
The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2015-11-24 14:39:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15149 bytes, from 2015-11-20 16:22:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 69600 bytes, from 2015-11-24 14:39:00)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 67220 bytes, from 2015-12-13 17:58:09)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109858 bytes, from 2016-02-10 17:07:21)
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
|
||||
|
||||
Copyright (C) 2013-2015 by the following authors:
|
||||
Copyright (C) 2013-2016 by the following authors:
|
||||
- Rob Clark <robdclark@gmail.com> (robclark)
|
||||
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
|
|
@ -172,6 +173,11 @@ enum adreno_pm4_type3_packets {
|
|||
CP_UNKNOWN_1A = 26,
|
||||
CP_UNKNOWN_4E = 78,
|
||||
CP_WIDE_REG_WRITE = 116,
|
||||
CP_SCRATCH_TO_REG = 77,
|
||||
CP_REG_TO_SCRATCH = 74,
|
||||
CP_WAIT_MEM_WRITES = 18,
|
||||
CP_COND_REG_EXEC = 71,
|
||||
CP_MEM_TO_REG = 66,
|
||||
IN_IB_PREFETCH_END = 23,
|
||||
IN_SUBBLK_PREFETCH = 31,
|
||||
IN_INSTR_PREFETCH = 32,
|
||||
|
|
@ -503,5 +509,29 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
|
|||
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
|
||||
}
|
||||
|
||||
#define REG_CP_REG_TO_MEM_0 0x00000000
|
||||
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
|
||||
#define CP_REG_TO_MEM_0_REG__SHIFT 0
|
||||
static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
|
||||
}
|
||||
#define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
|
||||
#define CP_REG_TO_MEM_0_CNT__SHIFT 19
|
||||
static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
|
||||
}
|
||||
#define CP_REG_TO_MEM_0_64B 0x40000000
|
||||
#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
|
||||
|
||||
#define REG_CP_REG_TO_MEM_1 0x00000001
|
||||
#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
|
||||
#define CP_REG_TO_MEM_1_DEST__SHIFT 0
|
||||
static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
|
||||
{
|
||||
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
|
||||
}
|
||||
|
||||
|
||||
#endif /* ADRENO_PM4_XML */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue