From dca9d859410fe2e514c59f8daa4e6904aaa820ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 10 Jul 2024 16:44:49 -0400 Subject: [PATCH] ac/surface: finish display DCC for gfx11.5 Fixes: 6835257246c - amd/common: update DCC for gfx11.5 Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: (cherry picked from commit 46071c90c7a8f112f5ee34abe3c24ad5b9b0bf02) --- .pick_status.json | 2 +- src/amd/common/ac_surface.c | 6 +----- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 7303e59bb82..42f9c5e48f5 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -34,7 +34,7 @@ "description": "ac/surface: finish display DCC for gfx11.5", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "6835257246c239fd3c3f7bed1af1952b2fd6584d", "notes": null diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 399b5ec26d5..6e78809a434 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1736,6 +1736,7 @@ static bool gfx9_is_dcc_supported_by_DCN(const struct radeon_info *info, case GFX10: case GFX10_3: case GFX11: + case GFX11_5: /* DCN requires INDEPENDENT_128B_BLOCKS = 0 only on Navi1x. */ if (info->gfx_level == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks) return false; @@ -1743,9 +1744,6 @@ static bool gfx9_is_dcc_supported_by_DCN(const struct radeon_info *info, return (!gfx10_DCN_requires_independent_64B_blocks(info, config) || (surf->u.gfx9.color.dcc.independent_64B_blocks && surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B)); - case GFX11_5: - // TODO: clarify DCN support for 256B compressed block sizes and other modes with the DAL team - return true; default: unreachable("unhandled chip"); return false; @@ -2363,8 +2361,6 @@ static int gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_ /* Don't change the DCC settings for imported buffers - they might differ. */ if (!(surf->flags & RADEON_SURF_IMPORTED) && (info->use_display_dcc_unaligned || info->use_display_dcc_with_retile_blit)) { - // TODO: clarify DCN support with the DAL team for gfx11.5 - /* Only Navi12/14 support independent 64B blocks in L2, * but without DCC image stores. */