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i965: Use MOV, not OR for setting URB write channel enables on Gen8+.

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On Broadwell, g0.5 contains the "Scratch Space Pointer"; using OR
puts some bits of that into "ignored" sections of our message header.

While this doesn't hurt, it's also not terribly /useful/.  Using MOV
is sufficient to set the only interesting bits in this part of the
message header.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2014-01-30 15:30:19 -08:00
parent e643c7d036
commit dca84b4b5b
1 changed files with 2 additions and 5 deletions
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7
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
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@ -173,11 +173,8 @@ gen8_vec4_generator::generate_urb_write(vec4_instruction *ir, bool vs)
if (!(ir->urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) { if (!(ir->urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
/* Enable Channel Masks in the URB_WRITE_OWORD message header */ /* Enable Channel Masks in the URB_WRITE_OWORD message header */
default_state.access_mode = BRW_ALIGN_1; default_state.access_mode = BRW_ALIGN_1;
inst = OR(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5), MOV_RAW(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5),
BRW_REGISTER_TYPE_UD), brw_imm_ud(0xff00));
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
brw_imm_ud(0xff00));
gen8_set_mask_control(inst, BRW_MASK_DISABLE);
default_state.access_mode = BRW_ALIGN_16; default_state.access_mode = BRW_ALIGN_16;
} }