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radv,aco: scalarize all phis via nir_lower_phis_to_scalar()

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This allows to remove some ACO code which did so previously.

Totals from 93 (0.06% of 149839) affected shaders (Navi2):
CodeSize: 582424 -> 582348 (-0.01%); split: -0.10%, +0.08%
Instrs: 107083 -> 107011 (-0.07%); split: -0.08%, +0.01%
Latency: 483338 -> 484881 (+0.32%); split: -0.09%, +0.40%
InvThroughput: 101129 -> 101532 (+0.40%); split: -0.03%, +0.42%
Copies: 9893 -> 9774 (-1.20%); split: -1.28%, +0.08%
Branches: 2862 -> 2858 (-0.14%)
PreSGPRs: 3342 -> 3339 (-0.09%)
PreVGPRs: 4567 -> 4565 (-0.04%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11181>
This commit is contained in:
Daniel Schürmann 2021-06-04 11:11:52 +02:00 • committed by Marge Bot
parent 057a702a3f
commit dc807dff3e
3 changed files with 2 additions and 37 deletions
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35
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -9498,41 +9498,6 @@ void visit_phi(isel_context *ctx, nir_phi_instr *instr)
return;
}
/* try to scalarize vector phis */
if (instr->dest.ssa.bit_size != 1 && dst.size() > 1) {
// TODO: scalarize linear phis on divergent ifs
bool can_scalarize = (opcode == aco_opcode::p_phi || !(ctx->block->kind & block_kind_merge));
std::array<Temp, NIR_MAX_VEC_COMPONENTS> new_vec;
for (unsigned i = 0; can_scalarize && (i < num_operands); i++) {
Operand src = operands[i];
if (src.isTemp() && ctx->allocated_vec.find(src.tempId()) == ctx->allocated_vec.end())
can_scalarize = false;
}
if (can_scalarize) {
unsigned num_components = instr->dest.ssa.num_components;
assert(dst.size() % num_components == 0);
RegClass rc = RegClass(dst.type(), dst.size() / num_components);
aco_ptr<Pseudo_instruction> vec{create_instruction<Pseudo_instruction>(aco_opcode::p_create_vector, Format::PSEUDO, num_components, 1)};
for (unsigned k = 0; k < num_components; k++) {
phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
for (unsigned i = 0; i < num_operands; i++) {
Operand src = operands[i];
phi->operands[i] = src.isTemp() ? Operand(ctx->allocated_vec[src.tempId()][k]) : Operand(rc);
}
Temp phi_dst = ctx->program->allocateTmp(rc);
phi->definitions[0] = Definition(phi_dst);
ctx->block->instructions.emplace(ctx->block->instructions.begin(), std::move(phi));
new_vec[k] = phi_dst;
vec->operands[k] = Operand(phi_dst);
}
vec->definitions[0] = Definition(dst);
ctx->block->instructions.emplace_back(std::move(vec));
ctx->allocated_vec.emplace(dst.id(), new_vec);
return;
}
}
phi.reset(create_instruction<Pseudo_instruction>(opcode, Format::PSEUDO, num_operands, 1));
for (unsigned i = 0; i < num_operands; i++)
phi->operands[i] = operands[i];

2
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -509,7 +509,7 @@ setup_nir(isel_context *ctx, nir_shader *nir)
setup_variables(ctx, nir);
nir_convert_to_lcssa(nir, true, false);
nir_lower_phis_to_scalar(nir, false);
nir_lower_phis_to_scalar(nir, true);
nir_function_impl *func = nir_shader_get_entrypoint(nir);
nir_index_ssa_defs(func);

2
src/amd/vulkan/radv_shader.c
View file

@ -146,7 +146,7 @@ radv_optimize_nir(const struct radv_device *device, struct nir_shader *shader,
nir_var_function_temp | nir_var_shader_in | nir_var_shader_out, NULL);
NIR_PASS_V(shader, nir_lower_alu_to_scalar, NULL, NULL);
NIR_PASS_V(shader, nir_lower_phis_to_scalar, false);
NIR_PASS_V(shader, nir_lower_phis_to_scalar, true);
NIR_PASS(progress, shader, nir_copy_prop);
NIR_PASS(progress, shader, nir_opt_remove_phis);