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i965/gen11: Fix must-be-ones bit positions in 3D_MODE

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Fixes: f0d29238df ("i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>
(cherry picked from commit b9a7f9314b)
This commit is contained in:
Jordan Justen 2021-03-10 09:26:13 -08:00 • committed by Dylan Baker
parent 8e300244d9
commit dc301a17df
2 changed files with 2 additions and 2 deletions
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2
.pick_status.json
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@ -337,7 +337,7 @@
"description": "i965/gen11: Fix must-be-ones bit positions in 3D_MODE",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "f0d29238df33d66ca4ee1e5f25a1edd9034f632e"
},

2
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -144,7 +144,7 @@ brw_upload_gen11_slice_hashing_state(struct brw_context *brw)
*/
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_3D_MODE << 16 | (2 - 2));
OUT_BATCH(0xffff | SLICE_HASHING_TABLE_ENABLE);
OUT_BATCH(0xffff0000 | SLICE_HASHING_TABLE_ENABLE);
ADVANCE_BATCH();
}