fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 05:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

aco: fix non-rtz pack_half_2x16

Browse source 
We were using the wrong conversion opcode. The high bits are also not
zero'd on GFX10, which can cause v_cvt_pk_u16_u32 to clamp.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: df645fa369 ('aco: implement VK_KHR_shader_float_controls')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6346>
(cherry picked from commit 9c1e0d86a8)
This commit is contained in:
Rhys Perry 2020-08-17 11:28:07 +01:00 • committed by Eric Engestrom
parent e8d449071f
commit dbed75ce6f
2 changed files with 12 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -3910,7 +3910,7 @@
"description": "aco: fix non-rtz pack_half_2x16",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "df645fa369d12be4d5e0fd9e4f6d4455caf2f4c3"
},

16
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -2721,12 +2721,18 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
Temp src0 = bld.tmp(v1);
Temp src1 = bld.tmp(v1);
bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
if (0 && (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)) {
bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
else
bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
} else {
src0 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src0);
src1 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src1);
if (ctx->program->chip_class >= GFX10) {
/* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
bld.vop3(aco_opcode::v_pack_b32_f16, Definition(dst), src0, src1);
} else {
bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst), src0, src1);
}
}
} else {
fprintf(stderr, "Unimplemented NIR instr bit size: ");
nir_print_instr(&instr->instr, stderr);