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radv/amdgpu: Let addrlib calculate the HTILE parameters.

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Still not sure we can support miptrees when sampling from
HTILE enabled textures.

Added the tcCompatible winsys stuff while I'm at it.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Bas Nieuwenhuizen 2017-03-07 00:37:46 +01:00
parent 03f5405fc2
commit dbecbab5aa
2 changed files with 31 additions and 0 deletions
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5
src/amd/vulkan/radv_radeon_winsys.h
View file

@ -148,6 +148,7 @@ struct radeon_info {
#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
#define RADEON_SURF_FMASK (1 << 21)
#define RADEON_SURF_DISABLE_DCC (1 << 22)
#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
@ -217,6 +218,10 @@ struct radeon_surf {
uint64_t dcc_size;
uint64_t dcc_alignment;
uint64_t htile_size;
uint64_t htile_slice_size;
uint64_t htile_alignment;
};
enum radeon_bo_layout {

26
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c
View file

@ -260,6 +260,30 @@ static int radv_compute_level(ADDR_HANDLE addrlib,
}
}
if (!is_stencil && AddrSurfInfoIn->flags.depth &&
surf_level->mode == RADEON_SURF_MODE_2D && level == 0) {
ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
AddrHtileIn.flags.tcCompatible = AddrSurfInfoIn->flags.tcCompatible;
AddrHtileIn.pitch = AddrSurfInfoOut->pitch;
AddrHtileIn.height = AddrSurfInfoOut->height;
AddrHtileIn.numSlices = AddrSurfInfoOut->depth;
AddrHtileIn.blockWidth = ADDR_HTILE_BLOCKSIZE_8;
AddrHtileIn.blockHeight = ADDR_HTILE_BLOCKSIZE_8;
AddrHtileIn.pTileInfo = AddrSurfInfoOut->pTileInfo;
AddrHtileIn.tileIndex = AddrSurfInfoOut->tileIndex;
AddrHtileIn.macroModeIndex = AddrSurfInfoOut->macroModeIndex;
ret = AddrComputeHtileInfo(addrlib,
&AddrHtileIn,
&AddrHtileOut);
if (ret == ADDR_OK) {
surf->htile_size = AddrHtileOut.htileBytes;
surf->htile_slice_size = AddrHtileOut.sliceSize;
surf->htile_alignment = AddrHtileOut.baseAlign;
}
}
return 0;
}
@ -455,6 +479,8 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws,
surf->bo_size = 0;
surf->dcc_size = 0;
surf->dcc_alignment = 1;
surf->htile_size = surf->htile_slice_size = 0;
surf->htile_alignment = 1;
/* Calculate texture layout information. */
for (level = 0; level <= surf->last_level; level++) {