mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-22 09:10:11 +01:00
r300: setup render target format for r300/r400 cards too
This commit is contained in:
Maciej Cencora
parent
353966b2da
commit
dbd53f8f55
1 changed files with 82 additions and 86 deletions
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@ -35,12 +35,6 @@
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#include "compiler/radeon_compiler.h"
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#include "compiler/radeon_compiler.h"
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#include "compiler/radeon_opcodes.h"
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#include "compiler/radeon_opcodes.h"
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/**
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* TODO:
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* - handle depth buffer
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* - r300 fp and rs setup
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*/
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static void vp_ins_outs(struct r300_vertex_program_compiler *c)
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static void vp_ins_outs(struct r300_vertex_program_compiler *c)
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{
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{
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c->code->inputs[VERT_ATTRIB_POS] = 0;
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c->code->inputs[VERT_ATTRIB_POS] = 0;
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@ -135,85 +129,6 @@ void r300_blit_init(struct r300_context *r300)
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create_fragment_program(r300);
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create_fragment_program(r300);
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}
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}
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static void r500_emit_rs_setup(struct r300_context *r300)
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{
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BATCH_LOCALS(&r300->radeon);
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BEGIN_BATCH(7);
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OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
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OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
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OUT_BATCH(0);
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OUT_BATCH_REGVAL(R500_RS_INST_0,
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(0 << R500_RS_INST_TEX_ID_SHIFT) |
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(0 << R500_RS_INST_TEX_ADDR_SHIFT) |
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R500_RS_INST_TEX_CN_WRITE |
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R500_RS_INST_COL_CN_NO_WRITE);
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OUT_BATCH_REGVAL(R500_RS_IP_0,
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(0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
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(1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
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(2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
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(3 << R500_RS_IP_TEX_PTR_Q_SHIFT));
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END_BATCH();
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}
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static void r300_emit_fp_setup(struct r300_context *r300,
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struct r300_fragment_program_code *code)
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{
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unsigned i;
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BATCH_LOCALS(&r300->radeon);
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BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 9);
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OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].rgb_inst);
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}
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OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].rgb_addr);
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}
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OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].alpha_inst);
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}
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OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].alpha_addr);
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}
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OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length);
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OUT_BATCH_TABLE(code->tex.inst, code->tex.length);
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OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
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OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX);
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OUT_BATCH(code->pixsize);
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OUT_BATCH(code->code_offset);
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OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
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OUT_BATCH_TABLE(code->code_addr, 4);
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END_BATCH();
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}
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static void r300_emit_rs_setup(struct r300_context *r300)
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{
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BATCH_LOCALS(&r300->radeon);
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BEGIN_BATCH(7);
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OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
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OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
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OUT_BATCH(0);
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OUT_BATCH_REGVAL(R300_RS_INST_0,
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R300_RS_INST_TEX_ID(0) |
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R300_RS_INST_TEX_ADDR(0) |
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R300_RS_INST_TEX_CN_WRITE);
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OUT_BATCH_REGVAL(R300_RS_IP_0,
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R300_RS_TEX_PTR(0) |
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R300_RS_SEL_S(R300_RS_SEL_C0) |
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R300_RS_SEL_R(R300_RS_SEL_C1) |
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R300_RS_SEL_T(R300_RS_SEL_K0) |
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R300_RS_SEL_Q(R300_RS_SEL_K1));
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END_BATCH();
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}
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static void r300_emit_tx_setup(struct r300_context *r300,
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static void r300_emit_tx_setup(struct r300_context *r300,
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gl_format mesa_format,
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gl_format mesa_format,
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struct radeon_bo *bo,
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struct radeon_bo *bo,
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@ -325,6 +240,87 @@ static void r500_emit_fp_setup(struct r300_context *r300,
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END_BATCH();
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END_BATCH();
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}
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}
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static void r500_emit_rs_setup(struct r300_context *r300)
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{
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BATCH_LOCALS(&r300->radeon);
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BEGIN_BATCH(7);
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OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
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OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
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OUT_BATCH(0);
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OUT_BATCH_REGVAL(R500_RS_INST_0,
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(0 << R500_RS_INST_TEX_ID_SHIFT) |
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(0 << R500_RS_INST_TEX_ADDR_SHIFT) |
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R500_RS_INST_TEX_CN_WRITE |
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R500_RS_INST_COL_CN_NO_WRITE);
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OUT_BATCH_REGVAL(R500_RS_IP_0,
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(0 << R500_RS_IP_TEX_PTR_S_SHIFT) |
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(1 << R500_RS_IP_TEX_PTR_T_SHIFT) |
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(2 << R500_RS_IP_TEX_PTR_R_SHIFT) |
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(3 << R500_RS_IP_TEX_PTR_Q_SHIFT));
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END_BATCH();
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}
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static void r300_emit_fp_setup(struct r300_context *r300,
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struct r300_fragment_program_code *code,
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gl_format dst_format)
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{
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unsigned i;
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BATCH_LOCALS(&r300->radeon);
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BEGIN_BATCH((code->alu.length + 1) * 4 + code->tex.length + 1 + 11);
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OUT_BATCH_REGSEQ(R300_US_ALU_RGB_INST_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].rgb_inst);
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}
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OUT_BATCH_REGSEQ(R300_US_ALU_RGB_ADDR_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].rgb_addr);
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}
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OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_INST_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].alpha_inst);
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}
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OUT_BATCH_REGSEQ(R300_US_ALU_ALPHA_ADDR_0, code->alu.length);
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for (i = 0; i < code->alu.length; i++) {
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OUT_BATCH(code->alu.inst[i].alpha_addr);
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}
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OUT_BATCH_REGSEQ(R300_US_TEX_INST_0, code->tex.length);
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OUT_BATCH_TABLE(code->tex.inst, code->tex.length);
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OUT_BATCH_REGSEQ(R300_US_CONFIG, 3);
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OUT_BATCH(R300_PFS_CNTL_FIRST_NODE_HAS_TEX);
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OUT_BATCH(code->pixsize);
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OUT_BATCH(code->code_offset);
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OUT_BATCH_REGSEQ(R300_US_CODE_ADDR_0, 4);
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OUT_BATCH_TABLE(code->code_addr, 4);
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OUT_BATCH_REGVAL(R500_US_OUT_FMT_0, mesa_format_to_us_format(dst_format));
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END_BATCH();
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}
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static void r300_emit_rs_setup(struct r300_context *r300)
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{
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BATCH_LOCALS(&r300->radeon);
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BEGIN_BATCH(7);
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OUT_BATCH_REGSEQ(R300_RS_COUNT, 2);
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OUT_BATCH((4 << R300_IT_COUNT_SHIFT) | R300_HIRES_EN);
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OUT_BATCH(0);
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OUT_BATCH_REGVAL(R300_RS_INST_0,
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R300_RS_INST_TEX_ID(0) |
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R300_RS_INST_TEX_ADDR(0) |
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R300_RS_INST_TEX_CN_WRITE);
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OUT_BATCH_REGVAL(R300_RS_IP_0,
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R300_RS_TEX_PTR(0) |
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R300_RS_SEL_S(R300_RS_SEL_C0) |
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R300_RS_SEL_R(R300_RS_SEL_C1) |
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R300_RS_SEL_T(R300_RS_SEL_K0) |
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R300_RS_SEL_Q(R300_RS_SEL_K1));
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END_BATCH();
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}
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static void emit_pvs_setup(struct r300_context *r300,
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static void emit_pvs_setup(struct r300_context *r300,
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uint32_t *vp_code,
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uint32_t *vp_code,
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unsigned vp_len)
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unsigned vp_len)
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@ -507,7 +503,7 @@ GLboolean r300_blit(struct r300_context *r300,
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r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat);
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r500_emit_fp_setup(r300, &r300->blit.fp_code.code.r500, dst_mesaformat);
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r500_emit_rs_setup(r300);
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r500_emit_rs_setup(r300);
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} else {
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} else {
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r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300);
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r300_emit_fp_setup(r300, &r300->blit.fp_code.code.r300, dst_mesaformat);
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r300_emit_rs_setup(r300);
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r300_emit_rs_setup(r300);
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}
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}
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