From db905159fdfbad0bb4e3b3c376a2744e438cae14 Mon Sep 17 00:00:00 2001
From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Tue, 10 Mar 2026 08:36:30 +0100
Subject: [PATCH] amd/drm-shim: add phoenix

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40313>
---
 src/amd/drm-shim/amdgpu_devices.c | 129 ++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/src/amd/drm-shim/amdgpu_devices.c b/src/amd/drm-shim/amdgpu_devices.c
index 8e0c9f06b83..a1c27602619 100644
--- a/src/amd/drm-shim/amdgpu_devices.c
+++ b/src/amd/drm-shim/amdgpu_devices.c
@@ -2571,6 +2571,135 @@ const struct amdgpu_device amdgpu_devices[] = {
          },
       },
    },
+   {
+      .name = "phoenix",
+      .radeon_family = CHIP_PHOENIX,
+      .hw_ip_gfx = {
+         .hw_ip_version_major = 11,
+         .hw_ip_version_minor = 0,
+         .capabilities_flags = UINT64_C(0),
+         .ib_start_alignment = 32,
+         .ib_size_alignment = 32,
+         .available_rings = 0x1,
+         .ip_discovery_version = 0xb0001,
+      },
+      .hw_ip_compute = {
+         .hw_ip_version_major = 11,
+         .hw_ip_version_minor = 0,
+         .capabilities_flags = UINT64_C(0),
+         .ib_start_alignment = 32,
+         .ib_size_alignment = 32,
+         .available_rings = 0xf,
+         .ip_discovery_version = 0xb0001,
+      },
+      .fw_gfx_me = {
+         .ver = 40,
+         .feature = 35,
+      },
+      .fw_gfx_pfp = {
+         .ver = 49,
+         .feature = 35,
+      },
+      .fw_gfx_mec = {
+         .ver = 40,
+         .feature = 35,
+      },
+      .mmr_regs = {
+         0x263e, 0xffffffff, 0x00000242,
+      },
+      .mmr_reg_count = 1,
+      .dev = {
+         .device_id = 0x15bf,
+         .chip_rev = 0x09,
+         .external_rev = 0x0a,
+         .pci_rev = 0x04,
+         .family = AMDGPU_FAMILY_GC_11_0_1,
+         .num_shader_engines = 1,
+         .num_shader_arrays_per_engine = 2,
+         .gpu_counter_freq = 99810,
+         .max_engine_clock = UINT64_C(2700000),
+         .max_memory_clock = UINT64_C(937000),
+         .cu_active_number = 12,
+         .cu_ao_mask = 0x0,
+         .cu_bitmap = {
+            { 0x3f, 0x3f, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+         },
+         .enabled_rb_pipes_mask = 0xf,
+         .num_rb_pipes = 4,
+         .num_hw_gfx_contexts = 8,
+         .pcie_gen = 4,
+         .ids_flags = UINT64_C(0x1d),
+         .virtual_address_offset = UINT64_C(0x10000),
+         .virtual_address_max = UINT64_C(0x800000000000),
+         .virtual_address_alignment = 4096,
+         .pte_fragment_size = 2097152,
+         .gart_page_size = 4096,
+         .ce_ram_size = 0,
+         .vram_type = 12,
+         .vram_bit_width = 128,
+         .vce_harvest_config = 0,
+         .gc_double_offchip_lds_buf = 0,
+         .prim_buf_gpu_addr = UINT64_C(0),
+         .pos_buf_gpu_addr = UINT64_C(0),
+         .cntl_sb_buf_gpu_addr = UINT64_C(0),
+         .param_buf_gpu_addr = UINT64_C(0),
+         .prim_buf_size = 0,
+         .pos_buf_size = 0,
+         .cntl_sb_buf_size = 0,
+         .param_buf_size = 0,
+         .wave_front_size = 32,
+         .num_shader_visible_vgprs = 1024,
+         .num_cu_per_sh = 6,
+         .num_tcc_blocks = 4,
+         .gs_vgt_table_depth = 32,
+         .gs_prim_buffer_depth = 1792,
+         .max_gs_waves_per_vgt = 32,
+         .pcie_num_lanes = 16,
+         .cu_ao_bitmap = {
+            { 0x0, 0x0, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+            { 0x0, 0x0, 0x0, 0x0, },
+         },
+         .high_va_offset = UINT64_C(0xffff800000000000),
+         .high_va_max = UINT64_C(0xffffffffffbfe000),
+         .pa_sc_tile_steering_override = 0,
+         .tcc_disabled_mask = UINT64_C(0),
+         .min_engine_clock = UINT64_C(800000),
+         .min_memory_clock = UINT64_C(400000),
+         .tcp_cache_size = 32,
+         .num_sqc_per_wgp = 1,
+         .sqc_data_cache_size = 16,
+         .sqc_inst_cache_size = 32,
+         .gl1c_cache_size = 256,
+         .gl2c_cache_size = 2048,
+         .mall_size = UINT64_C(0),
+         .enabled_rb_pipes_mask_hi = 0,
+      },
+      .mem = {
+         .vram = {
+            .total_heap_size = UINT64_C(536870912),
+            .usable_heap_size = UINT64_C(447279104),
+            .heap_usage = UINT64_C(421896192),
+            .max_allocation = UINT64_C(335459328),
+         },
+         .cpu_accessible_vram = {
+            .total_heap_size = UINT64_C(536870912),
+            .usable_heap_size = UINT64_C(447279104),
+            .heap_usage = UINT64_C(421896192),
+            .max_allocation = UINT64_C(335459328),
+         },
+         .gtt = {
+            .total_heap_size = UINT64_C(16447774720),
+            .usable_heap_size = UINT64_C(16423583744),
+            .heap_usage = UINT64_C(300511232),
+            .max_allocation = UINT64_C(12317687808),
+         },
+      },
+   },
 };
 
 const size_t num_amdgpu_devices = ARRAY_SIZE(amdgpu_devices);