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freedreno/ir3: add ir3_shader_disasm()
Split out most of dump_info() from ir3_cmdline compiler into a function that can be used both by cmdline compiler and also for the disasm debug option. This way, for FD_MESA_DEBUG=disasm we also get to see intput/ output registers, etc. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
3244195f48
commit
db5105b4b3
3 changed files with 124 additions and 120 deletions
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@ -43,127 +43,15 @@
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#include "instr-a3xx.h"
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#include "ir3.h"
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static void dump_reg(const char *name, uint32_t r)
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{
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if (r != regid(63,0))
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debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
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}
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static void dump_semantic(struct ir3_shader_variant *so,
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unsigned sem, const char *name)
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{
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uint32_t regid;
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regid = ir3_find_output_regid(so, ir3_semantic_name(sem, 0));
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dump_reg(name, regid);
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}
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static void dump_info(struct ir3_shader_variant *so, const char *str)
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{
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uint32_t *bin;
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const char *type = (so->type == SHADER_VERTEX) ? "VERT" : "FRAG";
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// for debug, dump some before/after info:
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// TODO make gpu_id configurable on cmdline
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bin = ir3_shader_assemble(so, 320);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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struct ir3 *ir = so->ir;
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struct ir3_register *reg;
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uint8_t regid;
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unsigned i;
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debug_printf("; %s: %s\n", type, str);
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for (i = 0; i < ir->ninputs; i++) {
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if (!ir->inputs[i]) {
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debug_printf("; in%d unused\n", i);
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continue;
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}
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reg = ir->inputs[i]->regs[0];
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regid = reg->num;
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debug_printf("@in(%sr%d.%c)\tin%d\n",
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(reg->flags & IR3_REG_HALF) ? "h" : "",
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(regid >> 2), "xyzw"[regid & 0x3], i);
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}
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for (i = 0; i < ir->noutputs; i++) {
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if (!ir->outputs[i]) {
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debug_printf("; out%d unused\n", i);
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continue;
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}
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/* kill shows up as a virtual output.. skip it! */
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if (is_kill(ir->outputs[i]))
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continue;
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reg = ir->outputs[i]->regs[0];
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regid = reg->num;
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debug_printf("@out(%sr%d.%c)\tout%d\n",
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(reg->flags & IR3_REG_HALF) ? "h" : "",
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(regid >> 2), "xyzw"[regid & 0x3], i);
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}
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for (i = 0; i < so->immediates_count; i++) {
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debug_printf("@const(c%d.x)\t", so->first_immediate + i);
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debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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so->immediates[i].val[0],
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so->immediates[i].val[1],
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so->immediates[i].val[2],
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so->immediates[i].val[3]);
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}
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disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
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debug_printf("; %s: outputs:", type);
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for (i = 0; i < so->outputs_count; i++) {
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uint8_t regid = so->outputs[i].regid;
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ir3_semantic sem = so->outputs[i].semantic;
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debug_printf(" r%d.%c (%u:%u)",
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(regid >> 2), "xyzw"[regid & 0x3],
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sem2name(sem), sem2idx(sem));
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}
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debug_printf("\n");
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debug_printf("; %s: inputs:", type);
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for (i = 0; i < so->inputs_count; i++) {
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uint8_t regid = so->inputs[i].regid;
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ir3_semantic sem = so->inputs[i].semantic;
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debug_printf(" r%d.%c (%u:%u,cm=%x,il=%u,b=%u)",
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(regid >> 2), "xyzw"[regid & 0x3],
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sem2name(sem), sem2idx(sem),
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so->inputs[i].compmask,
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so->inputs[i].inloc,
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so->inputs[i].bary);
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}
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debug_printf("\n");
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}
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/* print generic shader info: */
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debug_printf("; %s: %u instructions, %d half, %d full\n", type,
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so->info.instrs_count,
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so->info.max_half_reg + 1,
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so->info.max_reg + 1);
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/* print shader type specific info: */
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switch (so->type) {
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case SHADER_VERTEX:
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dump_semantic(so, TGSI_SEMANTIC_POSITION, "pos");
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dump_semantic(so, TGSI_SEMANTIC_PSIZE, "psize");
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break;
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case SHADER_FRAGMENT:
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dump_reg("pos (bary)", so->pos_regid);
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dump_semantic(so, TGSI_SEMANTIC_POSITION, "posz");
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dump_semantic(so, TGSI_SEMANTIC_COLOR, "color");
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/* these two are hard-coded since we don't know how to
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* program them to anything but all 0's...
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*/
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if (so->frag_coord)
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debug_printf("; fragcoord: r0.x\n");
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if (so->frag_face)
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debug_printf("; fragface: hr0.x\n");
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break;
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case SHADER_COMPUTE:
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break;
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}
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debug_printf("; %s: %s\n", type, str);
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ir3_shader_disasm(so, bin);
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free(bin);
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debug_printf("\n");
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}
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@ -140,6 +140,13 @@ assemble_variant(struct ir3_shader_variant *v)
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memcpy(fd_bo_map(v->bo), bin, sz);
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if (fd_mesa_debug & FD_DBG_DISASM) {
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struct ir3_shader_key key = v->key;
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DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
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key.binning_pass, key.color_two_side, key.half_precision);
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ir3_shader_disasm(v, bin);
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}
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free(bin);
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/* no need to keep the ir around beyond this point: */
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@ -179,12 +186,6 @@ create_variant(struct ir3_shader *shader, struct ir3_shader_key key)
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goto fail;
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}
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if (fd_mesa_debug & FD_DBG_DISASM) {
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DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
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key.binning_pass, key.color_two_side, key.half_precision);
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disasm_a3xx(fd_bo_map(v->bo), v->info.sizedwords, 0, v->type);
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}
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return v;
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fail:
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@ -262,3 +263,117 @@ ir3_shader_create(struct pipe_context *pctx, const struct tgsi_token *tokens,
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shader->tokens = tgsi_dup_tokens(tokens);
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return shader;
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}
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static void dump_reg(const char *name, uint32_t r)
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{
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if (r != regid(63,0))
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debug_printf("; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
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}
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static void dump_semantic(struct ir3_shader_variant *so,
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unsigned sem, const char *name)
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{
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uint32_t regid;
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regid = ir3_find_output_regid(so, ir3_semantic_name(sem, 0));
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dump_reg(name, regid);
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}
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void
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ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin)
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{
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struct ir3 *ir = so->ir;
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struct ir3_register *reg;
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const char *type = (so->type == SHADER_VERTEX) ? "VERT" : "FRAG";
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uint8_t regid;
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unsigned i;
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for (i = 0; i < ir->ninputs; i++) {
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if (!ir->inputs[i]) {
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debug_printf("; in%d unused\n", i);
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continue;
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}
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reg = ir->inputs[i]->regs[0];
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regid = reg->num;
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debug_printf("@in(%sr%d.%c)\tin%d\n",
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(reg->flags & IR3_REG_HALF) ? "h" : "",
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(regid >> 2), "xyzw"[regid & 0x3], i);
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}
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for (i = 0; i < ir->noutputs; i++) {
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if (!ir->outputs[i]) {
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debug_printf("; out%d unused\n", i);
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continue;
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}
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/* kill shows up as a virtual output.. skip it! */
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if (is_kill(ir->outputs[i]))
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continue;
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reg = ir->outputs[i]->regs[0];
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regid = reg->num;
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debug_printf("@out(%sr%d.%c)\tout%d\n",
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(reg->flags & IR3_REG_HALF) ? "h" : "",
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(regid >> 2), "xyzw"[regid & 0x3], i);
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}
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for (i = 0; i < so->immediates_count; i++) {
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debug_printf("@const(c%d.x)\t", so->first_immediate + i);
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debug_printf("0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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so->immediates[i].val[0],
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so->immediates[i].val[1],
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so->immediates[i].val[2],
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so->immediates[i].val[3]);
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}
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disasm_a3xx(bin, so->info.sizedwords, 0, so->type);
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debug_printf("; %s: outputs:", type);
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for (i = 0; i < so->outputs_count; i++) {
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uint8_t regid = so->outputs[i].regid;
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ir3_semantic sem = so->outputs[i].semantic;
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debug_printf(" r%d.%c (%u:%u)",
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(regid >> 2), "xyzw"[regid & 0x3],
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sem2name(sem), sem2idx(sem));
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}
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debug_printf("\n");
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debug_printf("; %s: inputs:", type);
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for (i = 0; i < so->inputs_count; i++) {
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uint8_t regid = so->inputs[i].regid;
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ir3_semantic sem = so->inputs[i].semantic;
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debug_printf(" r%d.%c (%u:%u,cm=%x,il=%u,b=%u)",
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(regid >> 2), "xyzw"[regid & 0x3],
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sem2name(sem), sem2idx(sem),
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so->inputs[i].compmask,
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so->inputs[i].inloc,
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so->inputs[i].bary);
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}
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debug_printf("\n");
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/* print generic shader info: */
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debug_printf("; %s: %u instructions, %d half, %d full\n", type,
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so->info.instrs_count,
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so->info.max_half_reg + 1,
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so->info.max_reg + 1);
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/* print shader type specific info: */
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switch (so->type) {
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case SHADER_VERTEX:
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dump_semantic(so, TGSI_SEMANTIC_POSITION, "pos");
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dump_semantic(so, TGSI_SEMANTIC_PSIZE, "psize");
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break;
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case SHADER_FRAGMENT:
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dump_reg("pos (bary)", so->pos_regid);
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dump_semantic(so, TGSI_SEMANTIC_POSITION, "posz");
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dump_semantic(so, TGSI_SEMANTIC_COLOR, "color");
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/* these two are hard-coded since we don't know how to
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* program them to anything but all 0's...
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*/
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if (so->frag_coord)
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debug_printf("; fragcoord: r0.x\n");
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if (so->frag_face)
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debug_printf("; fragface: hr0.x\n");
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break;
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case SHADER_COMPUTE:
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break;
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}
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debug_printf("\n");
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}
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@ -212,6 +212,7 @@ struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
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void ir3_shader_destroy(struct ir3_shader *shader);
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struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
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struct ir3_shader_key key);
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void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin);
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/*
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* Helper/util:
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