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intel/brw: Use fs_inst explicitly in various passes

Browse source 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27866>
This commit is contained in:
Caio Oliveira 2024-02-28 15:19:10 -08:00
parent 692021cad7
commit db322554a7
6 changed files with 21 additions and 25 deletions
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14
src/intel/compiler/brw_dead_control_flow.cpp
View file

@ -48,8 +48,8 @@ brw_fs_opt_dead_control_flow_eliminate(fs_visitor &s)
if (!prev_block)
continue;
backend_instruction *const inst = block->start();
backend_instruction *const prev_inst = prev_block->end();
fs_inst *const inst = block->start();
fs_inst *const prev_inst = prev_block->end();
/* ENDIF instructions, by definition, can only be found at the start of
* basic blocks.
@ -57,7 +57,7 @@ brw_fs_opt_dead_control_flow_eliminate(fs_visitor &s)
if (inst->opcode == BRW_OPCODE_ENDIF &&
prev_inst->opcode == BRW_OPCODE_ELSE) {
bblock_t *const else_block = prev_block;
backend_instruction *const else_inst = prev_inst;
fs_inst *const else_inst = prev_inst;
else_inst->remove(else_block);
progress = true;
@ -65,8 +65,8 @@ brw_fs_opt_dead_control_flow_eliminate(fs_visitor &s)
prev_inst->opcode == BRW_OPCODE_IF) {
bblock_t *const endif_block = block;
bblock_t *const if_block = prev_block;
backend_instruction *const endif_inst = inst;
backend_instruction *const if_inst = prev_inst;
fs_inst *const endif_inst = inst;
fs_inst *const if_inst = prev_inst;
bblock_t *earlier_block = NULL, *later_block = NULL;
@ -101,8 +101,8 @@ brw_fs_opt_dead_control_flow_eliminate(fs_visitor &s)
} else if (inst->opcode == BRW_OPCODE_ELSE &&
prev_inst->opcode == BRW_OPCODE_IF) {
bblock_t *const else_block = block;
backend_instruction *const if_inst = prev_inst;
backend_instruction *const else_inst = inst;
fs_inst *const if_inst = prev_inst;
fs_inst *const else_inst = inst;
/* Since the else-branch is becoming the new then-branch, the
* condition has to be inverted.

2
src/intel/compiler/brw_fs.cpp
View file

@ -2808,7 +2808,7 @@ fs_visitor::compute_max_register_pressure()
{
const register_pressure &rp = regpressure_analysis.require();
uint32_t ip = 0, max_pressure = 0;
foreach_block_and_inst(block, backend_instruction, inst, cfg) {
foreach_block_and_inst(block, fs_inst, inst, cfg) {
max_pressure = MAX2(max_pressure, rp.regs_live_at_ip[ip]);
ip++;
}

2
src/intel/compiler/brw_fs_register_coalesce.cpp
View file

@ -331,7 +331,7 @@ brw_fs_opt_register_coalesce(fs_visitor &s)
}
if (progress) {
foreach_block_and_inst_safe (block, backend_instruction, inst, s.cfg) {
foreach_block_and_inst_safe (block, fs_inst, inst, s.cfg) {
if (inst->opcode == BRW_OPCODE_NOP) {
inst->remove(block, true);
}

2
src/intel/compiler/brw_fs_workaround.cpp
View file

@ -19,7 +19,7 @@ brw_fs_workaround_emit_dummy_mov_instruction(fs_visitor &s)
if (!intel_needs_workaround(s.devinfo, 14015360517))
return false;
struct backend_instruction *first_inst =
fs_inst *first_inst =
s.cfg->first_block()->start();
/* We can skip the WA if first instruction is marked with

16
src/intel/compiler/brw_ir_performance.cpp
View file

@ -877,7 +877,7 @@ namespace {
*/
unsigned
accum_reg_of_channel(const intel_device_info *devinfo,
const backend_instruction *inst,
const fs_inst *inst,
brw_reg_type tx, unsigned i)
{
assert(inst->reads_accumulator_implicitly() ||
@ -891,11 +891,10 @@ namespace {
* Model the performance behavior of an FS back-end instruction.
*/
void
issue_fs_inst(state &st, const struct brw_isa_info *isa,
const backend_instruction *be_inst)
issue_inst(state &st, const struct brw_isa_info *isa,
const fs_inst *inst)
{
const struct intel_device_info *devinfo = isa->devinfo;
const fs_inst *inst = static_cast<const fs_inst *>(be_inst);
const instruction_info info(isa, inst);
const perf_desc perf = instruction_desc(info);
@ -1014,9 +1013,6 @@ namespace {
*/
void
calculate_performance(performance &p, const fs_visitor *s,
void (*issue_instruction)(
state &, const struct brw_isa_info *,
const backend_instruction *),
unsigned dispatch_width)
{
/* XXX - Note that the previous version of this code used worst-case
@ -1054,10 +1050,10 @@ namespace {
foreach_block(block, s->cfg) {
const unsigned elapsed0 = elapsed;
foreach_inst_in_block(backend_instruction, inst, block) {
foreach_inst_in_block(fs_inst, inst, block) {
const unsigned clock0 = st.unit_ready[EU_UNIT_FE];
issue_instruction(st, &s->compiler->isa, inst);
issue_inst(st, &s->compiler->isa, inst);
if (inst->opcode == SHADER_OPCODE_HALT_TARGET && halt_count)
st.weight /= discard_weight;
@ -1083,7 +1079,7 @@ namespace {
brw::performance::performance(const fs_visitor *v) :
block_latency(new unsigned[v->cfg->num_blocks])
{
calculate_performance(*this, v, issue_fs_inst, v->dispatch_width);
calculate_performance(*this, v, v->dispatch_width);
}
brw::performance::~performance()

10
src/intel/compiler/brw_predicated_break.cpp
View file

@ -108,12 +108,12 @@ brw_fs_opt_predicated_break(fs_visitor &s)
/* DO instructions, by definition, can only be found at the beginning of
* basic blocks.
*/
backend_instruction *const do_inst = block->start();
fs_inst *const do_inst = block->start();
/* BREAK, CONTINUE, and WHILE instructions, by definition, can only be
* found at the ends of basic blocks.
*/
backend_instruction *jump_inst = block->end();
fs_inst *jump_inst = block->end();
if (do_inst->opcode == BRW_OPCODE_DO)
enter_loop(&state);
@ -130,11 +130,11 @@ brw_fs_opt_predicated_break(fs_visitor &s)
jump_inst->opcode != BRW_OPCODE_CONTINUE)
continue;
backend_instruction *if_inst = block->prev()->end();
fs_inst *if_inst = block->prev()->end();
if (if_inst->opcode != BRW_OPCODE_IF)
continue;
backend_instruction *endif_inst = block->next()->start();
fs_inst *endif_inst = block->next()->start();
if (endif_inst->opcode != BRW_OPCODE_ENDIF)
continue;
@ -219,7 +219,7 @@ brw_fs_opt_predicated_break(fs_visitor &s)
* CONT instruction.
*/
bblock_t *while_block = earlier_block->next();
backend_instruction *while_inst = while_block->start();
fs_inst *while_inst = while_block->start();
if (jump_inst->opcode == BRW_OPCODE_BREAK &&
while_inst->opcode == BRW_OPCODE_WHILE &&