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i965: Don't flush the batch at the end of blorp.

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Improves GLB2.7 performance 0.13% +/- 0.09% (n=104/105, outliers removed).
More importantly, once color glClear()s are done through blorp in the next
commit, this reduces regression in GLES3 conformance tests that rely on
queueing up many glClear()s and having the GPU report being still busy in
an ARB_sync query after that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt 2013-02-07 18:46:18 -08:00
parent fb1eed9ec5
commit db31bc5cfb
3 changed files with 19 additions and 18 deletions
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19
src/mesa/drivers/dri/i965/brw_blorp.cpp
View file

@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
#include "intel_batchbuffer.h"
#include "intel_fbo.h"
#include "brw_blorp.h"
@ -163,6 +164,8 @@ intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
void
brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
{
struct brw_context *brw = brw_context(&intel->ctx);
switch (intel->gen) {
case 6:
gen6_blorp_exec(intel, params);
@ -175,6 +178,22 @@ brw_blorp_exec(struct intel_context *intel, const brw_blorp_params *params)
assert(false);
break;
}
if (unlikely(intel->always_flush_batch))
intel_batchbuffer_flush(intel);
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
brw->state.dirty.brw = ~0;
brw->state.dirty.cache = ~0;
brw->state_batch_count = 0;
intel->batch.need_workaround_flush = true;
/* Flush the sampler cache so any texturing from the destination is
* coherent.
*/
intel_batchbuffer_emit_mi_flush(intel);
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,

9
src/mesa/drivers/dri/i965/gen6_blorp.cpp
View file

@ -1093,14 +1093,5 @@ gen6_blorp_exec(struct intel_context *intel,
gen6_blorp_emit_clear_params(brw, params);
gen6_blorp_emit_drawing_rectangle(brw, params);
gen6_blorp_emit_primitive(brw, params);
/* See comments above at first invocation of intel_flush() in
* gen6_blorp_emit_batch_head().
*/
intel_flush(ctx);
/* Be safe. */
brw->state.dirty.brw = ~0;
brw->state.dirty.cache = ~0;
}

9
src/mesa/drivers/dri/i965/gen7_blorp.cpp
View file

@ -807,13 +807,4 @@ gen7_blorp_exec(struct intel_context *intel,
gen7_blorp_emit_clear_params(brw, params);
gen6_blorp_emit_drawing_rectangle(brw, params);
gen7_blorp_emit_primitive(brw, params);
/* See comments above at first invocation of intel_flush() in
* gen6_blorp_emit_batch_head().
*/
intel_flush(ctx);
/* Be safe. */
brw->state.dirty.brw = ~0;
brw->state.dirty.cache = ~0;
}