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iris: actually pin the instruction cache buffers

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This commit is contained in:
Kenneth Graunke 2018-01-30 02:16:34 -08:00
parent bda9a77b47
commit db15993cfd
4 changed files with 17 additions and 2 deletions
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7
src/gallium/drivers/iris/iris_batch.c
View file

@ -659,6 +659,13 @@ emit_reloc(struct iris_batch *batch,
return entry->offset + target_offset;
}
void
iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo)
{
assert(bo->kflags & EXEC_OBJECT_PINNED);
add_exec_bo(batch, bo);
}
uint64_t
iris_batch_reloc(struct iris_batch *batch, uint32_t batch_offset,
struct iris_bo *target, uint32_t target_offset,

2
src/gallium/drivers/iris/iris_batch.h
View file

@ -121,6 +121,8 @@ bool iris_batch_references(struct iris_batch *batch, struct iris_bo *bo);
#define RELOC_WRITE EXEC_OBJECT_WRITE
void iris_use_pinned_bo(struct iris_batch *batch, struct iris_bo *bo);
uint64_t iris_batch_reloc(struct iris_batch *batch,
uint32_t batch_offset,
struct iris_bo *target,

2
src/gallium/drivers/iris/iris_resource.c
View file

@ -263,6 +263,8 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
goto fail;
if (templ->flags & IRIS_RESOURCE_FLAG_INSTRUCTION_CACHE) {
res->bo->kflags = EXEC_OBJECT_PINNED;
res->bo->name = "instruction cache";
// XXX: p_atomic_add is backwards :(
res->bo->gtt_offset = __atomic_fetch_add(&screen->next_instruction_address, res->bo->size, __ATOMIC_ACQ_REL);
}

8
src/gallium/drivers/iris/iris_state.c
View file

@ -1989,8 +1989,12 @@ iris_upload_render_state(struct iris_context *ice,
if (!(dirty & (IRIS_DIRTY_VS << stage)))
continue;
if (ice->shaders.prog[stage]) {
iris_batch_emit(batch, ice->shaders.prog[stage]->derived_data,
struct iris_compiled_shader *shader = ice->shaders.prog[stage];
if (shader) {
struct iris_resource *cache = (void *) shader->buffer;
iris_use_pinned_bo(batch, cache->bo);
iris_batch_emit(batch, shader->derived_data,
iris_derived_program_state_size(stage));
} else {
if (stage == MESA_SHADER_TESS_EVAL) {