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genX/pipeline: Break emit_vertex_input out into common code
It's mostly the same and contains some non-trivial logic, so it really should be shared. Also, we're about to make some modifications here that we would really like to share.
This commit is contained in:
Jason Ekstrand
parent
fe6ccb6031
commit
da75492879
3 changed files with 107 additions and 156 deletions
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@ -34,85 +34,6 @@
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#include "genX_pipeline_util.h"
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static void
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emit_vertex_input(struct anv_pipeline *pipeline,
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const VkPipelineVertexInputStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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uint32_t elements;
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if (extra && extra->disable_vs) {
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/* If the VS is disabled, just assume the user knows what they're
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* doing and apply the layout blindly. This can only come from
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* meta, so this *should* be safe.
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*/
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elements = 0;
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
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elements |= (1 << info->pVertexAttributeDescriptions[i].location);
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} else {
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/* Pull inputs_read out of the VS prog data */
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uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
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assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
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elements = inputs_read >> VERT_ATTRIB_GENERIC0;
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}
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uint32_t vb_count = __builtin_popcount(elements);
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if (pipeline->vs_prog_data.uses_vertexid ||
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pipeline->vs_prog_data.uses_instanceid)
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vb_count++;
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if (vb_count == 0)
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return;
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const uint32_t num_dwords = 1 + vb_count * 2;
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uint32_t *p = anv_batch_emitn(&pipeline->batch, num_dwords,
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GEN7_3DSTATE_VERTEX_ELEMENTS);
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memset(p + 1, 0, (num_dwords - 1) * 4);
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
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const VkVertexInputAttributeDescription *desc =
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&info->pVertexAttributeDescriptions[i];
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enum isl_format format = anv_get_isl_format(desc->format,
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VK_IMAGE_ASPECT_COLOR_BIT,
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VK_IMAGE_TILING_LINEAR);
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assert(desc->binding < 32);
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if ((elements & (1 << desc->location)) == 0)
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continue; /* Binding unused */
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uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
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struct GEN7_VERTEX_ELEMENT_STATE element = {
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.VertexBufferIndex = desc->binding,
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.Valid = true,
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.SourceElementFormat = format,
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.EdgeFlagEnable = false,
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.SourceElementOffset = desc->offset,
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.Component0Control = vertex_element_comp_control(format, 0),
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.Component1Control = vertex_element_comp_control(format, 1),
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.Component2Control = vertex_element_comp_control(format, 2),
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.Component3Control = vertex_element_comp_control(format, 3),
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};
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GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + slot * 2], &element);
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}
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if (pipeline->vs_prog_data.uses_vertexid ||
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pipeline->vs_prog_data.uses_instanceid) {
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struct GEN7_VERTEX_ELEMENT_STATE element = {
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.Valid = true,
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/* FIXME: Do we need to provide the base vertex as component 0 here
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* to support the correct base vertex ID? */
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.Component0Control = VFCOMP_STORE_0,
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.Component1Control = VFCOMP_STORE_0,
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.Component2Control = VFCOMP_STORE_VID,
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.Component3Control = VFCOMP_STORE_IID
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};
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GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + (vb_count - 1) * 2], &element);
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}
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}
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static void
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gen7_emit_rs_state(struct anv_pipeline *pipeline,
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const VkPipelineRasterizationStateCreateInfo *info,
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@ -34,83 +34,6 @@
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#include "genX_pipeline_util.h"
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static void
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emit_vertex_input(struct anv_pipeline *pipeline,
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const VkPipelineVertexInputStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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static_assert(ANV_GEN >= 8, "should be compiling this for gen < 8");
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uint32_t elements;
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if (extra && extra->disable_vs) {
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/* If the VS is disabled, just assume the user knows what they're
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* doing and apply the layout blindly. This can only come from
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* meta, so this *should* be safe.
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*/
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elements = 0;
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
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elements |= (1 << info->pVertexAttributeDescriptions[i].location);
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} else {
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/* Pull inputs_read out of the VS prog data */
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uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
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assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
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elements = inputs_read >> VERT_ATTRIB_GENERIC0;
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}
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const uint32_t num_dwords = 1 + __builtin_popcount(elements) * 2;
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uint32_t *p;
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if (elements != 0) {
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p = anv_batch_emitn(&pipeline->batch, num_dwords,
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GENX(3DSTATE_VERTEX_ELEMENTS));
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memset(p + 1, 0, (num_dwords - 1) * 4);
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}
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
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const VkVertexInputAttributeDescription *desc =
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&info->pVertexAttributeDescriptions[i];
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enum isl_format format = anv_get_isl_format(desc->format,
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VK_IMAGE_ASPECT_COLOR_BIT,
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VK_IMAGE_TILING_LINEAR);
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assert(desc->binding < 32);
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if ((elements & (1 << desc->location)) == 0)
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continue; /* Binding unused */
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uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
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struct GENX(VERTEX_ELEMENT_STATE) element = {
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.VertexBufferIndex = desc->binding,
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.Valid = true,
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.SourceElementFormat = format,
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.EdgeFlagEnable = false,
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.SourceElementOffset = desc->offset,
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.Component0Control = vertex_element_comp_control(format, 0),
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.Component1Control = vertex_element_comp_control(format, 1),
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.Component2Control = vertex_element_comp_control(format, 2),
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.Component3Control = vertex_element_comp_control(format, 3),
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};
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GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
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.InstancingEnable = pipeline->instancing_enable[desc->binding],
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.VertexElementIndex = slot,
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/* Vulkan so far doesn't have an instance divisor, so
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* this is always 1 (ignored if not instancing). */
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.InstanceDataStepRate = 1);
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}
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const uint32_t id_slot = __builtin_popcount(elements);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
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.VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
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.VertexIDComponentNumber = 2,
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.VertexIDElementOffset = id_slot,
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.InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
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.InstanceIDComponentNumber = 3,
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.InstanceIDElementOffset = id_slot);
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}
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static void
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emit_ia_state(struct anv_pipeline *pipeline,
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const VkPipelineInputAssemblyStateCreateInfo *info,
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@ -47,6 +47,113 @@ vertex_element_comp_control(enum isl_format format, unsigned comp)
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}
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}
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static void
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emit_vertex_input(struct anv_pipeline *pipeline,
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const VkPipelineVertexInputStateCreateInfo *info,
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const struct anv_graphics_pipeline_create_info *extra)
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{
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uint32_t elements;
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if (extra && extra->disable_vs) {
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/* If the VS is disabled, just assume the user knows what they're
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* doing and apply the layout blindly. This can only come from
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* meta, so this *should* be safe.
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*/
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elements = 0;
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++)
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elements |= (1 << info->pVertexAttributeDescriptions[i].location);
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} else {
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/* Pull inputs_read out of the VS prog data */
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uint64_t inputs_read = pipeline->vs_prog_data.inputs_read;
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assert((inputs_read & ((1 << VERT_ATTRIB_GENERIC0) - 1)) == 0);
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elements = inputs_read >> VERT_ATTRIB_GENERIC0;
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}
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uint32_t elem_count = __builtin_popcount(elements);
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#if ANV_GEN <= 7
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/* On Haswell and prior, vertex and instance id are created by using the
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* ComponentControl fields, so we need an element for any of them.
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*/
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if (pipeline->vs_prog_data.uses_vertexid ||
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pipeline->vs_prog_data.uses_instanceid)
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elem_count++;
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#endif
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uint32_t *p;
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if (elem_count > 0) {
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const uint32_t num_dwords = 1 + elem_count * 2;
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p = anv_batch_emitn(&pipeline->batch, num_dwords,
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GENX(3DSTATE_VERTEX_ELEMENTS));
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memset(p + 1, 0, (num_dwords - 1) * 4);
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}
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for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
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const VkVertexInputAttributeDescription *desc =
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&info->pVertexAttributeDescriptions[i];
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enum isl_format format = anv_get_isl_format(desc->format,
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VK_IMAGE_ASPECT_COLOR_BIT,
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VK_IMAGE_TILING_LINEAR);
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assert(desc->binding < 32);
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if ((elements & (1 << desc->location)) == 0)
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continue; /* Binding unused */
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uint32_t slot = __builtin_popcount(elements & ((1 << desc->location) - 1));
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struct GENX(VERTEX_ELEMENT_STATE) element = {
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.VertexBufferIndex = desc->binding,
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.Valid = true,
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.SourceElementFormat = format,
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.EdgeFlagEnable = false,
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.SourceElementOffset = desc->offset,
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.Component0Control = vertex_element_comp_control(format, 0),
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.Component1Control = vertex_element_comp_control(format, 1),
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.Component2Control = vertex_element_comp_control(format, 2),
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.Component3Control = vertex_element_comp_control(format, 3),
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};
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GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
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#if ANV_GEN >= 8
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/* On Broadwell and later, we have a separate VF_INSTANCING packet
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* that controls instancing. On Haswell and prior, that's part of
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* VERTEX_BUFFER_STATE which we emit later.
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*/
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING),
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.InstancingEnable = pipeline->instancing_enable[desc->binding],
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.VertexElementIndex = slot,
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/* Vulkan so far doesn't have an instance divisor, so
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* this is always 1 (ignored if not instancing). */
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.InstanceDataStepRate = 1);
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#endif
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}
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const uint32_t id_slot = __builtin_popcount(elements);
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#if ANV_GEN >= 8
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS),
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.VertexIDEnable = pipeline->vs_prog_data.uses_vertexid,
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.VertexIDComponentNumber = 2,
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.VertexIDElementOffset = id_slot,
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.InstanceIDEnable = pipeline->vs_prog_data.uses_instanceid,
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.InstanceIDComponentNumber = 3,
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.InstanceIDElementOffset = id_slot);
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#else
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if (pipeline->vs_prog_data.uses_vertexid ||
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pipeline->vs_prog_data.uses_instanceid) {
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struct GEN7_VERTEX_ELEMENT_STATE element = {
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.Valid = true,
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/* FIXME: Do we need to provide the base vertex as component 0 here
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* to support the correct base vertex ID? */
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.Component0Control = VFCOMP_STORE_0,
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.Component1Control = VFCOMP_STORE_0,
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.Component2Control = VFCOMP_STORE_VID,
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.Component3Control = VFCOMP_STORE_IID
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};
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GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + id_slot * 2], &element);
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}
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#endif
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}
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static const uint32_t vk_to_gen_cullmode[] = {
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[VK_CULL_MODE_NONE] = CULLMODE_NONE,
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[VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,
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