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Bunch of documention additions.

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This commit is contained in:
Jose Fonseca 2003-02-22 09:17:11 +00:00
parent 661a236d09
commit da69c37f98
16 changed files with 765 additions and 306 deletions
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2
src/mesa/drivers/dri/radeon/radeon_context.h
View file

@ -670,7 +670,7 @@ static __inline GLuint radeonPackColor( GLuint cpp,
}
/* ================================================================
/******************************************************************
* Debugging:
*/
#define DO_DEBUG 1

263
src/mesa/drivers/dri/radeon/radeon_ioctl.c
View file

@ -1,38 +1,37 @@
/**
* \file radeon_ioctl.c
* \brief DRM interface functions.
*
* \author Kevin E. Martin <martin@valinux.com>
* \author Gareth Hughes <gareth@valinux.com>
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.c,v 1.7 2002/09/16 18:05:19 eich Exp $ */
@ -60,11 +59,18 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
static void radeonWaitForIdle( radeonContextPtr rmesa );
/***************************************************************
* \name Kernel command buffer handling
/***************************************************************/
/** \name Kernel command buffer handling
*/
/*@{*/
/**
* \brief Print state atom information.
*
* For debugging purposes only.
*
* \param state state atom.
*/
static void print_state_atom( struct radeon_state_atom *state )
{
int i;
@ -77,6 +83,16 @@ static void print_state_atom( struct radeon_state_atom *state )
}
/**
* \brief Emit a list of state atoms.
*
* \param rmesa Radeon context.
* \param list state atom list.
*
* For each active state in the list copies the associated commands into the
* command buffer, and moves the atom into the clean list.
*
*/
static void radeon_emit_state_list( radeonContextPtr rmesa,
struct radeon_state_atom *list )
{
@ -97,6 +113,18 @@ static void radeon_emit_state_list( radeonContextPtr rmesa,
}
/**
* \brief Emit dirty state.
*
* \param rmesa Radeon context.
*
* Calls radeon_emit_state_list() with the radeon_hw_state::dirty list.
*
* If radeon_context::lost_context is set then all state is emited by moving
* everything in radeon_hw_state::dirty prior to the radeon_emit_state_list()
* call. For woring around a Quake3 lock-up radeon_hw_state::zbs is always made
* \e dirty.
*/
void radeonEmitState( radeonContextPtr rmesa )
{
struct radeon_state_atom *state, *tmp;
@ -137,6 +165,14 @@ void radeonEmitState( radeonContextPtr rmesa )
/**
* Fire a section of the retained (indexed_verts) buffer as a regular
* primitive.
*
* \param rmesa Radeon context.
* \param vertex_format vertex format.
* \param primitive primitive.
* \param vertex_nr number of vertices.
*
* Emits the dirty state and adds a new command to the command buffer for
* firing the vertices pointed by radeon_context::ioctl.
*/
extern void radeonEmitVbufPrim( radeonContextPtr rmesa,
GLuint vertex_format,
@ -257,7 +293,15 @@ void radeonEmitAOS( radeonContextPtr rmesa,
#endif
/**
* \brief Emit vertex.
*
* \param rmesa Radeon context.
* \param vertex_size size of the vertex buffer.
* \param offset offset of the vertex buffer.
*
* Updates radeon_context::ioctl with the parameters given.
*/
void radeonEmitVertexAOS( radeonContextPtr rmesa,
GLuint vertex_size,
GLuint offset )
@ -267,8 +311,23 @@ void radeonEmitVertexAOS( radeonContextPtr rmesa,
}
/**
* \brief Flush the command buffer while holding the hardware lock.
*
* \param rmesa Radeon context.
* \param caller name of the calling function for debugging purposes.
*
* \return zero on success, non-zero otherwise.
*
* Issues a DRM_RADEON_CMDBUF command to the DRM passing a drmRadeonCmdBuffer
* structure as argument. The command buffer is reset before returning.
*
* If debugging is enabled, it prints several debug information and performs a
* sanity check before.
*
* \note Does not emit any commands to avoid recursion on
* radeonAllocCmdBuf().
*/
static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
const char * caller )
{
@ -327,8 +386,13 @@ static int radeonFlushCmdBufLocked( radeonContextPtr rmesa,
/**
* \note Does not emit any commands to avoid recursion on
* radeonAllocCmdBuf().
* \brief Flush the command buffer.
*
* \param rmesa Radeon context.
* \param caller name of the calling function for debugging purposes.
*
* Locks the hardware and calls radeonFlushCmdBufLocked(), aborting in case of
* failure.
*/
void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller )
{
@ -348,11 +412,24 @@ void radeonFlushCmdBuf( radeonContextPtr rmesa, const char *caller )
/*@}*/
/***************************************************************
* \name Hardware vertex buffer handling
/***************************************************************/
/** \name Hardware vertex buffer handling
*/
/*@{*/
/**
* \brief Refill the current DMA region.
*
* \param rmesa Radeon context.
*
* Releases and eventually flushes the current DMA region (if the number of
* released buffers is greater than 4). Locks the hardware and requests a new
* DMA buffer as the new current DMA region.
*
* In case of failure in the first try to get a new DMA buffer, flushes any
* previously released buffers, wait's for engine idle and tries once more,
* aborting if it fails.
*/
void radeonRefillCurrentDmaRegion( radeonContextPtr rmesa )
{
struct radeon_dma_buffer *dmabuf;
@ -459,8 +536,14 @@ void radeonReleaseDmaRegion( radeonContextPtr rmesa,
}
/**
* Allocates a region from rmesa->dma.current. If there isn't enough space in
* current, grab a new buffer (and discard what was left of current)
* \brief Allocates a new region from rmesa->dma.current.
*
* \param rmesa Radeon context.
* \param region will received the allocated region.
* \param bytes size
* \param alignment
*
* If there isn't enough space incurrent, grab a new buffer (and discard what was left of current).
*/
void radeonAllocDmaRegion( radeonContextPtr rmesa,
struct radeon_dma_region *region,
@ -498,6 +581,11 @@ void radeonAllocDmaRegion( radeonContextPtr rmesa,
radeonRefillCurrentDmaRegion( rmesa );
}
/**
* \brief Allocate a DMA region for vertices.
*
* Calls radeonAllocDmaRegion() with \p bytes = \p vertsize * \p numverts.
*/
void radeonAllocDmaRegionVerts( radeonContextPtr rmesa,
struct radeon_dma_region *region,
int numverts,
@ -510,11 +598,21 @@ void radeonAllocDmaRegionVerts( radeonContextPtr rmesa,
/*@}*/
/******************************************************************
* \name SwapBuffers with client-side throttling
/******************************************************************/
/** \name SwapBuffers with client-side throttling
*/
/*@{*/
/**
* \brief Get last frame.
*
* \param rmesa Radeon context.
*
* \return last frame number on success, or a nec
*
* Gets the last frame number via the DRM_RADEON_GETPARAM command in recent
* DRMs, or via the RADEON_LAST_FRAME_REG register.
*/
static GLuint radeonGetLastFrame (radeonContextPtr rmesa)
{
unsigned char *RADEONMMIO = rmesa->radeonScreen->mmio.map;
@ -543,6 +641,14 @@ static GLuint radeonGetLastFrame (radeonContextPtr rmesa)
return frame;
}
/**
* \brief Emit an IRQ while holding the hardware lock.
*
* \param rmesa Radeon context.
*
* Sends the DRM_RADEON_IRQ_EMIT command, aborting on failure.
*/
static void radeonEmitIrqLocked( radeonContextPtr rmesa )
{
drmRadeonIrqEmit ie;
@ -558,6 +664,13 @@ static void radeonEmitIrqLocked( radeonContextPtr rmesa )
}
/**
* \brief Wait on IRQ.
*
* \param rmesa Radeon context.
*
* Sends the DRM_RADEON_IRQ_WAIT command, aborting on failure.
*/
static void radeonWaitIrq( radeonContextPtr rmesa )
{
int ret;
@ -574,6 +687,19 @@ static void radeonWaitIrq( radeonContextPtr rmesa )
}
/**
* \brief Wait for frame completion.
*
* \param rmesa Radeon context.
*
* Waits until the number of processed frames reaches the one specifies in the SAREA.
*
* If IRQs are enabled and one has been emited then wait on the IRQ and send
* one afterwards.
*
* It assumes that the hardware was locked prior to the call but all waits are
* internally done with the hardware unlocked.
*/
static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
{
RADEONSAREAPrivPtr sarea = rmesa->sarea;
@ -609,6 +735,12 @@ static void radeonWaitForFrameCompletion( radeonContextPtr rmesa )
/**
* \brief Copy the back color buffer to the front color buffer.
*
* \param dPriv DRI specific drawable data.
*
* Fires the existing vertices and waits for frame completion and vertical
* retrace. Sends the DRM_RADEON_SWAP command for each set of existing
* cliprects.
*/
void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv )
{
@ -660,6 +792,16 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv )
UNLOCK_HARDWARE( rmesa );
}
/**
* \brief Do page flipping.
*
* \param dPriv DRI drawable speficic data.
*
* Fires the existing vertices and waits for frame completion and vertical
* retrace. Sends the DRM_RADEON_FLIP command and swaps the front and back
* buffer offsets and pitches.
*/
void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
{
radeonContextPtr rmesa;
@ -722,8 +864,8 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv )
/*@}*/
/******************************************************************
* Buffer clear
/******************************************************************/
/* \name Buffer clear
*/
/*@{*/
@ -897,6 +1039,14 @@ static void radeonClear( GLcontext *ctx, GLbitfield mask, GLboolean all,
}
/**
* \brief Wait for engine idle while holding the hardware lock.
*
* \param rmesa Radeon context.
*
* Sends the DRM_RADEON_CP_IDLE command until the engine is reported as idle or
* a timeout occurs.
*/
void radeonWaitForIdleLocked( radeonContextPtr rmesa )
{
int fd = rmesa->dri.fd;
@ -917,6 +1067,13 @@ void radeonWaitForIdleLocked( radeonContextPtr rmesa )
}
/**
* \brief Wait for engine idle.
*
* \param rmesa Radeon context.
*
* Locks the hardware and calls radeonWaitForIdleLocked().
*/
static void radeonWaitForIdle( radeonContextPtr rmesa )
{
LOCK_HARDWARE(rmesa);
@ -925,6 +1082,13 @@ static void radeonWaitForIdle( radeonContextPtr rmesa )
}
/**
* \brief Wait for vertical retrace.
*
* \param rmesa Radeon context.
*
* Disabled - no-op.
*/
void radeonWaitForVBlank( radeonContextPtr rmesa )
{
#if 0
@ -962,6 +1126,14 @@ void radeonWaitForVBlank( radeonContextPtr rmesa )
#endif
}
/**
* \brief Flush all dirty state and pending buffers.
*
* \param ctx GL context.
*
* Calls radeonEmitState() with the dirty state list if not empty, and
* radeonFlushCmdBuf() if the command buffer has been used.
*/
void radeonFlush( GLcontext *ctx )
{
radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
@ -982,8 +1154,13 @@ void radeonFlush( GLcontext *ctx )
}
/**
* Make sure all commands have been sent to the hardware and have
* \brief Make sure all commands have been sent to the hardware and have
* completed processing.
*
* \param ctx GL context.
*
* If IRQs are enabled then emits and waits on the IRQ, otherwise waits for
* engine idle.
*/
void radeonFinish( GLcontext *ctx )
{

67
src/mesa/drivers/dri/radeon/radeon_ioctl.h
View file

@ -1,37 +1,36 @@
/**
* \file radeon_ioctl.h
* \brief DRM interface functions.
*
* \author Kevin E. Martin <martin@valinux.com>
* \author Gareth Hughes <gareth@valinux.com>
*/
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
VA Linux Systems Inc., Fremont, California.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
* VA Linux Systems Inc., Fremont, California.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* ATI, VA LINUX SYSTEMS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_ioctl.h,v 1.4 2002/09/16 18:05:20 eich Exp $ */
@ -107,6 +106,8 @@ extern void radeonCompatEmitPrimitive( radeonContextPtr rmesa,
/**
* \brief Close off the last primitive, if it exists.
*
* \param rmesa Radeon context.
*/
#define RADEON_NEWPRIM( rmesa ) \
do { \
@ -117,6 +118,9 @@ do { \
/**
* Can accomodate several state changes and primitive changes without
* actually firing the buffer.
*
* \param rmesa Radeon context.
* \param ATOM state atom variable name.
*/
#define RADEON_STATECHANGE( rmesa, ATOM ) \
do { \
@ -148,6 +152,8 @@ static __inline int RADEON_DB_STATECHANGE(
/**
* \brief Fire the buffered vertices no matter what.
*
* \param rmesa Radeon context.
*/
#define RADEON_FIREVERTICES( rmesa ) \
do { \
@ -158,6 +164,13 @@ do { \
/**
* \brief Allocate space in the command buffer
*
* \param rmesa Radeon context.
* \param bytes number of bytes to allocate.
* \param where Not used.
*
* If there isn't enough space available flush the command buffer, otherwise
* just advance the buffer head the requested ammount.
*/
static __inline char *radeonAllocCmdBuf( radeonContextPtr rmesa,
int bytes, const char *where )

9
src/mesa/drivers/dri/radeon/radeon_screen.c
View file

@ -1,5 +1,6 @@
/**
* \file radeon_screen.c
* \brief Screen initialization functions.
*
* \author Kevin E. Martin <martin@valinux.com>
* \author Gareth Hughes <gareth@valinux.com>
@ -61,9 +62,9 @@
/**
* \brief Create the device specific screen private data struct.
* \brief Create the device specific screen data structure.
*
* \param sPriv DRI screen private data.
* \param sPriv DRI specific screen data.
*
* \return pointer to the device specific screen private data.
*
@ -265,9 +266,9 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv )
}
/**
* \brief Destroy the device specific screen private data struct.
* \brief Destroy the device specific screen data.
*
* \param sPriv DRI screen private data.
* \param sPriv DRI specific screen data.
*
* Unmaps all previously mapped regions and deallocates the device specific
* private data.

3
src/mesa/drivers/dri/radeon/radeon_screen.h
View file

@ -1,5 +1,6 @@
/**
* \file radeon_screen.h
* \brief Screen initialization functions.
*
* \author Kevin E. Martin <martin@valinux.com>
* \author Gareth Hughes <gareth@valinux.com>
@ -61,7 +62,7 @@ typedef struct {
#define RADEON_CHIPSET_TCL (1 << 0)
/**
* \brief Device specific screen private data.
* \brief Device specific screen data.
*/
typedef struct {

49
src/mesa/drivers/dri/radeon/radeon_state.c
View file

@ -1,5 +1,6 @@
/**
* \file radeon_state.c
* \brief State management.
*
* \author Gareth Hughes <gareth@valinux.com>
* \author Keith Whitwell <keith@tungstengraphics.com>
@ -65,8 +66,8 @@
#define TEXMAT_2 5
/***************************************************************
* \name Alpha blending
/***************************************************************/
/** \name Alpha blending
*/
/*@{*/
@ -288,8 +289,8 @@ static void radeonBlendFuncSeparate( GLcontext *ctx,
/*@}*/
/***************************************************************
* \name Depth testing
/***************************************************************/
/** \name Depth testing
*/
/*@{*/
@ -393,8 +394,8 @@ static void radeonClearDepth( GLcontext *ctx, GLclampd d )
/*@}*/
/***************************************************************
* \name Scissoring
/***************************************************************/
/** \name Scissoring
*/
/*@{*/
@ -499,8 +500,8 @@ static void radeonScissor( GLcontext *ctx,
/*@}*/
/***************************************************************
* \name Culling
/***************************************************************/
/** \name Culling
*/
/*@{*/
@ -590,8 +591,8 @@ static void radeonFrontFace( GLcontext *ctx, GLenum mode )
/*@}*/
/***************************************************************
* \name Line state
/***************************************************************/
/** \name Line state
*/
/*@{*/
@ -647,8 +648,8 @@ static void radeonLineStipple( GLcontext *ctx, GLint factor, GLushort pattern )
/*@}*/
/***************************************************************
* \name Masks
/***************************************************************/
/** \name Masks
*/
/*@{*/
@ -686,8 +687,8 @@ static void radeonColorMask( GLcontext *ctx,
/*@}*/
/***************************************************************
* \name Polygon state
/***************************************************************/
/** \name Polygon state
*/
/*@{*/
@ -765,8 +766,8 @@ static void radeonShadeModel( GLcontext *ctx, GLenum mode )
/*@}*/
/***************************************************************
* \name Stencil
/***************************************************************/
/** \name Stencil
*/
/*@{*/
@ -964,8 +965,8 @@ static void radeonClearStencil( GLcontext *ctx, GLint s )
/*@}*/
/***************************************************************
* \name Window position and viewport transformation
/***************************************************************/
/** \name Window position and viewport transformation
*/
/*@{*/
@ -1047,8 +1048,8 @@ static void radeonDepthRange( GLcontext *ctx, GLclampd nearval,
/*@}*/
/***************************************************************
* \name Miscellaneous
/***************************************************************/
/** \name Miscellaneous
*/
/*@{*/
@ -1231,8 +1232,8 @@ static void radeonReadBuffer( GLcontext *ctx, GLenum mode )
/*@}*/
/***************************************************************
* \name State enable/disable
/***************************************************************/
/** \name State enable/disable
*/
/*@{*/
@ -1550,8 +1551,8 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state )
/*@}*/
/***************************************************************
* \name Deferred state management - matrices, textures, other?
/***************************************************************/
/** \name Deferred state management - matrices, textures, other?
*/
/*@{*/

1
src/mesa/drivers/dri/radeon/radeon_state.h
View file

@ -1,5 +1,6 @@
/**
* \file radeon_state.h
* \brief State management.
*
* \authors Kevin E. Martin <martin@valinux.com>
* \author Gareth Hughes <gareth@valinux.com>

74
src/mesa/drivers/dri/radeon/radeon_state_init.c
View file

@ -73,6 +73,14 @@ void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
fprintf(stderr, "\n");
}
/**
* \brief Constructs a register packet command.
*
* \param register ID.
* \return integer equivalent of the command.
*
* \sa drmRadeonCmdHeader and drmRadeonCmdType::RADEON_CMD_PACKET.
*/
static int cmdpkt( int id )
{
drmRadeonCmdHeader h;
@ -82,6 +90,17 @@ static int cmdpkt( int id )
return h.i;
}
/**
* \brief Constructs a vector data command
*
* \param offset data offset.
* \param stride array stride.
* \param count vector count.
*
* \return integer equivalent of the command.
*
* \sa drmRadeonCmdHeader and drmRadeonCmdType::RADEON_CMD_VECTORS.
*/
static int cmdvec( int offset, int stride, int count )
{
drmRadeonCmdHeader h;
@ -93,6 +112,17 @@ static int cmdvec( int offset, int stride, int count )
return h.i;
}
/**
* \brief Constructs a scalar data command.
*
* \param offset data offset.
* \param stride array stride.
* \param count scalar count.
*
* \return integer equivalent of the command.
*
* \sa drmRadeonCmdHeader and drmRadeonCmdType::RADEON_CMD_SCALARS.
*/
static int cmdscl( int offset, int stride, int count )
{
drmRadeonCmdHeader h;
@ -104,9 +134,14 @@ static int cmdscl( int offset, int stride, int count )
return h.i;
}
/**
* \brief Utility macro for state checking functions definition.
*
* It is used for a shorthand definiton of the state checking functions. Four
* functions are defined:
* - one which always returns GL_TRUE for state which is always active;
* - two which determine whether the respective texture unit is enabled;
* - one which determines whether fog is enabled.
*/
#define CHECK( NM, FLAG ) \
static GLboolean check_##NM( GLcontext *ctx ) \
@ -116,6 +151,16 @@ static GLboolean check_##NM( GLcontext *ctx ) \
/**
* \brief Utility macro for TCL state checking functions definition.
*
* Same as for #CHECK but the functions defined by this macro always check
* whether TCL is enabled. Several functions are defined:
* - one which simply returns whether TCL is enabled;
* - for the texture units (2);
* - ligthing
* - eye-space coordinates and lighting
* - lights sources (8).
* - clip planes (6)
* - eye-space coordinates or fog
*/
#define TCL_CHECK( NM, FLAG ) \
static GLboolean check_##NM( GLcontext *ctx ) \
@ -151,9 +196,30 @@ TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
/**
* \def ALLOC_STATE
* \brief Utility macro to initialize a state atom.
*
* Used internally by radeonInitState() to allocate the state atom command
* buffer and initiaze the state checking function.
*
* \param ATOM atom name, as defined in radeon_hw_state.
* \param CHK state checking function, as defined by #CHECK or #TCL_CHECK.
* \param SZ command buffer size.
* \param NM C string name for debugging output purposes.
* \param FLAG whether is a TCL dependent flag.
*/
/**
* \brief Initialize the context's hardware state.
*
* \param rmesa Radeon context.
*
* Initalizes all state atoms giving apropriate inital state values. Allocates
* the state atoms' command buffers, using internally the #ALLOC_STATE macro
* for this effect. Fills in the packet headers with the register ID
* associated with the atom, via cmdpkt().
*/
void radeonInitState( radeonContextPtr rmesa )
{
@ -224,14 +290,14 @@ void radeonInitState( radeonContextPtr rmesa )
make_empty_list(&(rmesa->hw.clean));
#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
#define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
do { \
rmesa->hw.ATOM.cmd_size = SZ; \
rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
rmesa->hw.ATOM.name = NM; \
rmesa->hw.ATOM.is_tcl = FLAG; \
rmesa->hw.ATOM.check = check_##CHK; \
rmesa->hw.ATOM.is_tcl = FLAG; \
rmesa->hw.ATOM.check = check_##CHK; \
insert_at_head(&(rmesa->hw.dirty), &(rmesa->hw.ATOM)); \
} while (0)

65
src/mesa/drivers/dri/radeon/radeon_subset.h
View file

@ -1,38 +1,38 @@
/* $XFree86$ */
/**************************************************************************
Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
Tungsten Grahpics Inc., Austin, Texas.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
ATI, TUNGSTEN GRAHPICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/**
* \file radeon_subset.h
* \brief Radeon subset driver declarations.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
*
* Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
* Tungsten Grahpics Inc., Austin, Texas.
*
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* on the rights to use, copy, modify, merge, publish, distribute, sub
* license, and/or sell copies of the Software, and to permit persons to whom
* the Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
* ATI, TUNGSTEN GRAHPICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* $XFree86$ */
#ifndef __RADEON_SUBSET_H__
#define __RADEON_SUBSET_H__
@ -74,7 +74,4 @@ extern void radeonAgeTextures( radeonContextPtr rmesa, int heap );
extern void radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t );
#endif

14
src/mesa/drivers/dri/radeon/radeon_subset_bitmap.c
View file

@ -1,5 +1,6 @@
/**
* \file radeon_subset_bitmap.c
* \brief Bitmap drawing.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
@ -48,6 +49,19 @@
/**
* \brief Cope with depth operations by drawing individual pixels as points
*
* \param ctx GL context.
* \param px x coordinate of the bitmap corner.
* \param py y coordinate of the bitmap corner.
* \param width bitmap width.
* \param height bitmap height.
* \param unpack unpacking pixel attributes.
* \param bitmap bitmap pointer.
*
* Clips the bitmap coordinates and adjusts for windows coordinates. Draws the
* bitmap with glPoints(), turning off TCL and hardware viewport transformation
* to emit raw pixel coordinates. Finally fires any outstanding vertices and
* restores TCL, viewport, texture and color states.
*/
void
radeonPointsBitmap( GLcontext *ctx, GLint px, GLint py,

46
src/mesa/drivers/dri/radeon/radeon_subset_readpix.c
View file

@ -1,5 +1,6 @@
/**
* \file radeon_subset_readpix.c
* \brief Pixel reading.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
* \author Brian Paul <brian@tungstengraphics.com>
@ -29,7 +30,6 @@
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*/
/* $XFree86$ */
@ -47,6 +47,12 @@
#include "radeon_state.h"
#include "radeon_subset.h"
/**
* \brief Read pixel in RGBA format on a Radeon 16bpp frame buffer.
*
* \param rgba destination pointer.
* \param ptr pointer to the pixel in the frame buffer.
*/
#define READ_RGBA_16( rgba, ptr ) \
do { \
GLushort p = *(GLushort *)ptr; \
@ -56,6 +62,12 @@ do { \
rgba[3] = 0xff; \
} while (0)
/**
* \brief Read pixel in RGBA format on a Radeon 32bpp frame buffer.
*
* \param rgba destination pointer.
* \param ptr pointer to the pixel in the frame buffer.
*/
#define READ_RGBA_32( rgba, ptr ) \
do { \
GLuint p = *(GLuint *)ptr; \
@ -65,6 +77,18 @@ do { \
rgba[3] = (p >> 24) & 0xff; \
} while (0)
/**
* \brief Read a span in RGBA format.
*
* \param ctx GL context.
* \param n number of pixels in the span.
* \param x x position of the span start.
* \param y y position of the span.
* \param rgba destination buffer.
*
* Calculates the pointer to the span start in the frame buffer and uses either
* #READ_RGBA_16 or #READ_RGBA_32 macros to copy the values.
*/
static void ReadRGBASpan( const GLcontext *ctx,
GLuint n, GLint x, GLint y,
GLubyte rgba[][4])
@ -88,12 +112,24 @@ static void ReadRGBASpan( const GLcontext *ctx,
}
/**
* \brief Optimized glReadPixels
* \brief Optimized glReadPixels().
*
* For particular pixel formats GL_UNSIGNED_BYTE, GL_RGBA when pixel scaling,
* biasing and mapping are disabled.
* To be used with particular pixel formats GL_UNSIGNED_BYTE and GL_RGBA, when pixel
* scaling, biasing and mapping are disabled.
*
* \param ctx GL context.
* \param x x start position of the reading rectangle.
* \param y y start position of the reading rectangle.
* \param width width of the reading rectangle.
* \param height height of the reading recatangle.
* \param format pixel format. Must be GL_RGBA.
* \param format pixel type. Must be GL_UNSIGNED_BYTE.
* \param packing packing attributes. Must specify byte alignment and no byte
* swaping or LSB ordering.
*
* After asserting the above conditions, compensates for clipping and calls
* ReadRGBASpan() to read each row.
*/
void radeonReadPixels( GLcontext *ctx,
GLint x, GLint y,

85
src/mesa/drivers/dri/radeon/radeon_subset_select.c
View file

@ -1,5 +1,6 @@
/**
* \file radeon_subset_select.c
* \brief Selection.
*/
/*
@ -26,7 +27,7 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* $Id: radeon_subset_select.c,v 1.1.2.2 2003/02/16 20:48:12 jrfonseca Exp $ */
/* $Id: radeon_subset_select.c,v 1.1.2.3 2003/02/22 09:17:11 jrfonseca Exp $ */
#include "glheader.h"
@ -41,12 +42,19 @@
#include "radeon_context.h"
#include "radeon_subset.h"
/**
* \brief Vertex.
*/
typedef struct {
struct { GLfloat x, y, z, w; } pos, eyePos, clipPos, winPos;
struct { GLfloat s, t; } texCoord;
struct { GLfloat r, g, b, a; } color;
struct { GLfloat x, y, z, w; } pos, /**< \brief position */
eyePos, /**< \brief position, eye coordinates */
clipPos, /**< \brief clipped coordiantes */
winPos; /**< \brief position, windows coordinates */
struct { GLfloat s, t; } texCoord; /**< \brief texture coordinates */
struct { GLfloat r, g, b, a; } color; /**< \brief color */
} vertex;
static struct {
GLuint vCount;
vertex vBuffer[4];
@ -63,16 +71,24 @@ static struct {
/*@{*/
/**
* \brief Transform a point (column vector) by a matrix: Q = M * P
* \brief Transform a point (column vector) by a matrix: Q = M * P.
*
* \param Q destination point.
* \param P source point.
* \param M transformation matrix.
*/
#define TRANSFORM_POINT( Q, M, P ) \
#define TRANSFORM_POINT( Q, M, P ) \
Q.x = M[0] * P.x + M[4] * P.y + M[8] * P.z + M[12] * P.w; \
Q.y = M[1] * P.x + M[5] * P.y + M[9] * P.z + M[13] * P.w; \
Q.z = M[2] * P.x + M[6] * P.y + M[10] * P.z + M[14] * P.w; \
Q.w = M[3] * P.x + M[7] * P.y + M[11] * P.z + M[15] * P.w;
/**
* \brief Clip coord to window coord mapping
* \brief Clip coord to window coord mapping.
*
* \param Q destination point.
* \param P source point.
* \param VP view port.
*/
#define MAP_POINT( Q, P, VP ) \
Q.x = (GLfloat) (((P.x / P.w) + 1.0) * VP.Width / 2.0 + VP.X); \
@ -82,7 +98,12 @@ static struct {
/**
* \brief Linear interpolation:
* \brief Linear interpolation: (1 - T) * A + T * B.
*
* \param T interpolation factor.
* \param A first value.
* \param B second value.
* \result interpolated value.
*/
#define INTERPOLATE(T, A, B) ((A) + ((B) - (A)) * (T))
@ -90,6 +111,13 @@ static struct {
/**
* \brief Interpolate vertex position, color, texcoords, etc.
*
* \param t interpolation factor.
* \param v0 first vertex.
* \param v1 second vertex.
* \param vOut output vertex.
*
* Uses the #INTERPOLATE macro for all the interpolation of all elements.
*/
static void
interpolate_vertex(GLfloat t, const vertex *v0, const vertex *v1,
@ -131,7 +159,10 @@ interpolate_vertex(GLfloat t, const vertex *v0, const vertex *v1,
/**
* \brief Apply view volume clip testing to a point.
*
* \return zero if visible, or the clip code mask (binary OR of above CLIP_* bits)
* \param v point to test.
* \return zero if visible, or the clip code mask, i.e., binary OR of a
* combination of the #CLIP_LEFT, #CLIP_RIGHT, #CLIP_BOTTOM, #CLIP_TOP, #CLIP_NEAR,
* #CLIP_FAR clip bit codes.
*/
static GLuint
clip_point(const vertex *v)
@ -147,6 +178,16 @@ clip_point(const vertex *v)
}
/**
* \def GENERAL_CLIP
* \brief Clipping utility macro.
*
* We use 6 instances of this code in each of the clip_line() and
* clip_polygon() to clip agains the 6 planes. For each plane, we define the
* #OUTSIDE and #COMPUTE_INTERSECTION macros appropriately.
*/
/**
* \brief Apply clipping to a line segment.
*
@ -155,8 +196,10 @@ clip_point(const vertex *v)
* \param v0new output start vertice
* \param v1new output end vertice
*
* \return GL_TRUE if the line segment is visible, ot GL_FALS if it is totally
* \return GL_TRUE if the line segment is visible, ot GL_FALSE if it is totally
* clipped.
*
* \sa #GENERAL_CLIP.
*/
static GLboolean
clip_line(const vertex *v0in, const vertex *v1in,
@ -180,11 +223,6 @@ clip_line(const vertex *v0in, const vertex *v1in,
v1 = *v1in;
/**
* We use 6 instances of this code to clip agains the 6 planes.
* For each plane, we define the OUTSIDE and COMPUTE_INTERSECTION
* macros apprpriately.
*/
#define GENERAL_CLIP \
if (OUTSIDE(v0)) { \
if (OUTSIDE(v1)) { \
@ -208,7 +246,7 @@ clip_line(const vertex *v0in, const vertex *v1in,
/* else both verts are inside ==> do nothing */ \
}
/*** Clip against +X side ***/
/* Clip against +X side */
#define OUTSIDE(V) (V.clipPos.x > V.clipPos.w)
#define COMPUTE_INTERSECTION( IN, OUT, NEW ) \
dx = OUT.clipPos.x - IN.clipPos.x; \
@ -218,7 +256,7 @@ clip_line(const vertex *v0in, const vertex *v1in,
#undef OUTSIDE
#undef COMPUTE_INTERSECTION
/*** Clip against -X side ***/
/* Clip against -X side */
#define OUTSIDE(V) (V.clipPos.x < -(V.clipPos.w))
#define COMPUTE_INTERSECTION( IN, OUT, NEW ) \
dx = OUT.clipPos.x - IN.clipPos.x; \
@ -228,7 +266,7 @@ clip_line(const vertex *v0in, const vertex *v1in,
#undef OUTSIDE
#undef COMPUTE_INTERSECTION
/*** Clip against +Y side ***/
/* Clip against +Y side */
#define OUTSIDE(V) (V.clipPos.y > V.clipPos.w)
#define COMPUTE_INTERSECTION( IN, OUT, NEW ) \
dy = OUT.clipPos.y - IN.clipPos.y; \
@ -238,7 +276,7 @@ clip_line(const vertex *v0in, const vertex *v1in,
#undef OUTSIDE
#undef COMPUTE_INTERSECTION
/*** Clip against -Y side ***/
/* Clip against -Y side */
#define OUTSIDE(V) (V.clipPos.y < -(V.clipPos.w))
#define COMPUTE_INTERSECTION( IN, OUT, NEW ) \
dy = OUT.clipPos.y - IN.clipPos.y; \
@ -248,7 +286,7 @@ clip_line(const vertex *v0in, const vertex *v1in,
#undef OUTSIDE
#undef COMPUTE_INTERSECTION
/*** Clip against +Z side ***/
/* Clip against +Z side */
#define OUTSIDE(V) (V.clipPos.z > V.clipPos.w)
#define COMPUTE_INTERSECTION( IN, OUT, NEW ) \
dz = OUT.clipPos.z - IN.clipPos.z; \
@ -258,7 +296,7 @@ clip_line(const vertex *v0in, const vertex *v1in,
#undef OUTSIDE
#undef COMPUTE_INTERSECTION
/*** Clip against -Z side ***/
/* Clip against -Z side */
#define OUTSIDE(V) (V.clipPos.z < -(V.clipPos.w))
#define COMPUTE_INTERSECTION( IN, OUT, NEW ) \
dz = OUT.clipPos.z - IN.clipPos.z; \
@ -285,6 +323,8 @@ clip_line(const vertex *v0in, const vertex *v1in,
* \param vOut array of output vertices.
*
* \return number of vertices in /p vOut.
*
* \sa #GENERAL_CLIP.
*/
static GLuint
clip_polygon(const vertex *vIn, unsigned int inCount, vertex *vOut)
@ -775,7 +815,6 @@ static void radeon_select_Begin(GLenum mode)
vb.partialLineLoop = GL_FALSE;
}
static void radeon_select_End(void)
{
GET_CURRENT_CONTEXT(ctx);
@ -803,7 +842,6 @@ static void radeonSelectFlushVertices( GLcontext *ctx, GLuint flags )
ctx->Driver.NeedFlush = 0;
}
void radeon_select_Install( GLcontext *ctx )
{
struct _glapi_table *exec = ctx->Exec;
@ -824,7 +862,6 @@ void radeon_select_Install( GLcontext *ctx )
ctx->Driver.FlushVertices = radeonSelectFlushVertices;
}
static void radeonRenderMode( GLcontext *ctx, GLenum mode )
{
switch (mode) {

78
src/mesa/drivers/dri/radeon/radeon_subset_tex.c
View file

@ -1,5 +1,6 @@
/**
* \file radeon_subset_tex.c
* \brief Texturing.
*
* \author Gareth Hughes <gareth@valinux.com>
* \author Brian Paul <brianp@valinux.com>
@ -55,8 +56,11 @@
/**
* \brief Destroy hardware state associated with a texture.
*
* \param rmesa device context data.
* \param t texture object to be destroyed.
* \param rmesa Radeon context.
* \param t Radeon texture object to be destroyed.
*
* Frees the momery associated with the texture and if the texture is bound to
* a texture unit cleans the associated hardware state.
*/
void radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
{
@ -83,6 +87,11 @@ void radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
/**
* \brief Keep track of swapped out texture objects.
*
* \param rmesa Radeon context.
* \param t Radeon texture object.
* Frees the memory associated with the texture, signal all mipmap images in
* the texture as dirty and add it to the radeon_texture::swapped list.
*/
static void radeonSwapOutTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
{
@ -96,9 +105,13 @@ static void radeonSwapOutTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
}
/**
* Texture space has been invalidated.
*
* \param rmesa Radeon context.
* \param heap texture heap number.
*
* Swaps out every texture in the specified heap.
*/
void radeonAgeTextures( radeonContextPtr rmesa, int heap )
{
@ -111,13 +124,24 @@ void radeonAgeTextures( radeonContextPtr rmesa, int heap )
}
/***************************************************************
* \name Texture image conversions
/***************************************************************/
/** \name Texture image conversions
*/
/*@{*/
/* Upload the texture image associated with texture `t' at level `level'
* at the address relative to `start'.
/**
* \brief Upload texture image.
*
* \param rmesa Radeon context.
* \param t Radeon texture object.
* \param level level of the image to take the sub-image.
* \param x sub-image abcissa.
* \param y sub-image ordinate.
* \param width sub-image width.
* \param height sub-imate height.
*
* Fills in a drmRadeonTexture and drmRadeonTexImage structures and uploads the
* texture via the DRM_RADEON_TEXTURE IOCTL, aborting in case of failure.
*/
static void radeonUploadSubImage( radeonContextPtr rmesa,
radeonTexObjPtr t, GLint level,
@ -162,7 +186,16 @@ static void radeonUploadSubImage( radeonContextPtr rmesa,
*
* This might require removing our own and/or other client's texture objects to
* make room for these images.
*
*
* \param rmesa Radeon context.
* \param tObj texture object to upload.
*
* Sets the matching hardware texture format. Calculates which mipmap levels to
* send, depending of the base image size, GL_TEXTURE_MIN_LOD,
* GL_TEXTURE_MAX_LOD, GL_TEXTURE_BASE_LEVEL, and GL_TEXTURE_MAX_LEVEL and the
* Radeon offset rules. Kicks out textures until the requested texture fits,
* sets the texture hardware state and, while holding the hardware lock,
* uploads any images that are new.
*/
static void radeonSetTexImages( radeonContextPtr rmesa,
struct gl_texture_object *tObj )
@ -336,18 +369,24 @@ static void radeonSetTexImages( radeonContextPtr rmesa,
/*@}*/
/******************************************************************
* \name Texture combine functions
/******************************************************************/
/** \name Texture combine functions
*/
/*@{*/
#define RADEON_DISABLE 0
#define RADEON_REPLACE 1
#define RADEON_MODULATE 2
#define RADEON_DECAL 3
#define RADEON_BLEND 4
#define RADEON_MAX_COMBFUNC 5
enum {
RADEON_DISABLE = 0, /**< \brief disabled */
RADEON_REPLACE = 1, /**< \brief replace function */
RADEON_MODULATE = 2, /**< \brief modulate function */
RADEON_DECAL = 3, /**< \brief decal function */
RADEON_BLEND = 4, /**< \brief blend function */
RADEON_MAX_COMBFUNC = 5 /**< \brief max number of combine functions */
}
/**
* \brief Color combine function hardware state table.
*/
static GLuint radeon_color_combine[][RADEON_MAX_COMBFUNC] =
{
/* Unit 0:
@ -401,6 +440,9 @@ static GLuint radeon_color_combine[][RADEON_MAX_COMBFUNC] =
};
/**
* \brief Alpha combine function hardware state table.
*/
static GLuint radeon_alpha_combine[][RADEON_MAX_COMBFUNC] =
{
/* Unit 0:
@ -458,8 +500,8 @@ static GLuint radeon_alpha_combine[][RADEON_MAX_COMBFUNC] =
/*@}*/
/******************************************************************
* \name Texture unit state management
/******************************************************************/
/** \name Texture unit state management
*/
/*@{*/

110
src/mesa/drivers/dri/radeon/radeon_subset_vtx.c
View file

@ -1,5 +1,6 @@
/**
* \file radeon_subset_vtx.c
* \brief Vertex buffering.
*
* \author Keith Whitwell <keith@tungstengraphics.com>
*/
@ -50,54 +51,88 @@
#include "radeon_tex.h"
#include "radeon_subset.h"
/**
* \brief Union for vertex data.
*/
union vertex_dword { float f; int i; };
#define MAX_VERTEX_DWORDS 10 /* xyzw rgba st */
static struct {
/* Notification mechanism. These are treated as a stack to allow
* us to do things like build quads in temporary storage and then
* emit them as triangles:
/**
* \brief Maxium number of dwords per vertex.
*
* For \c xyzw \c rgba \c st.
*/
#define MAX_VERTEX_DWORDS 10
/**
* \brief Vertex global data.
*/
static struct vb_t {
/* \brief Notification mechanism.
*
* These are treated as a stack to allow us to do things like build quads in
* temporary storage and then emit them as triangles.
*/
struct {
GLint vertspace;
GLint initial_vertspace;
GLint *dmaptr;
void (*notify)( void );
GLint vertspace; /**< \brief free vertices count */
GLint initial_vertspace; /**< \brief total vertices count */
GLint *dmaptr; /**< \brief */
void (*notify)( void ); /**< \brief notification callback */
} stack[2];
/* Storage for current vertex:
/**
* \brief Storage for current vertex.
*/
union vertex_dword vertex[MAX_VERTEX_DWORDS];
/* Temporary storage for quads, etc:
/**
* \brief Temporary storage for quads, etc.
*/
union vertex_dword vertex_store[MAX_VERTEX_DWORDS * 4];
/* Pointers to either vertex or ctx->Current.Attrib, depending on
* whether color/texture participates in the current vertex:
/**
* \name Color/texture
*
* Pointers to either vertex or ctx->Current.Attrib, depending on whether
* color/texture participates in the current vertex.
*/
GLfloat *floatcolorptr;
GLfloat *texcoordptr;
/*@{*/
GLfloat *floatcolorptr; /**< \brief color */
GLfloat *texcoordptr; /**< \brief texture */
/*@}*/
/* Pointer to the context.
/**
* \brief Pointer to the context.
*/
GLcontext *context;
GLcontext *context;
/* Active prim (may differ from ctx->Driver.CurrentExecPrimitive)
/**
* \brief Active primitive.
*
* \note May differ from ctx->Driver.CurrentExecPrimitive.
*/
GLenum prim;
GLuint vertex_format;
GLint vertex_size;
/*@{*/
GLenum prim; /**< \brief primitive */
GLuint vertex_format; /**< \brief vertex format */
GLint vertex_size; /**< \brief vertex size */
GLboolean recheck;
/*@}*/
} vb;
static void radeonFlushVertices( GLcontext *, GLuint );
static struct { int start, incr, hwprim; } prims[10] = {
/**
* \brief Primitive information table.
*/
static struct prims_t {
int start, /**< \brief start vertex count */
incr, /**< \brief vertex increment */
hwprim; /**< \brief hardware primitive */
} prims[10] = {
{ 1, 1, RADEON_CP_VC_CNTL_PRIM_TYPE_POINT},
{ 2, 2, RADEON_CP_VC_CNTL_PRIM_TYPE_LINE },
{ 2, 1, RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP },
@ -110,6 +145,7 @@ static struct { int start, incr, hwprim; } prims[10] = {
{ 3, 1, RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN },
};
static void finish_prim( radeonContextPtr rmesa )
{
GLuint prim_end = vb.stack[0].initial_vertspace - vb.stack[0].vertspace;
@ -135,7 +171,6 @@ static void finish_prim( radeonContextPtr rmesa )
}
static void copy_vertex( radeonContextPtr rmesa, GLuint n, GLfloat *dst )
{
GLuint i;
@ -267,7 +302,8 @@ static void push_notify( void (*notify)( void ), int space,
}
/* Emit a stored vertex (in vb.vertex_store) to dma.
/**
* \brief Emit a stored vertex (in vb.vertex_store) to DMA.
*/
static void emit_vertex( int v )
{
@ -281,7 +317,8 @@ static void emit_vertex( int v )
}
/* Emit a quad (in vb.vertex_store) to dma as two triangles.
/**
* \brief Emit a quad (in vb.vertex_store) to dma as two triangles.
*/
static void emit_quad( int v0, int v1, int v2, int v3 )
{
@ -289,7 +326,8 @@ static void emit_quad( int v0, int v1, int v2, int v3 )
emit_vertex( v1 ); emit_vertex( v2 ); emit_vertex( v3 );
}
/* Every fourth vertex in a quad primitive, this is called to emit:
/**
* \brief Every fourth vertex in a quad primitive, this is called to emit.
*/
static void notify_quad( void )
{
@ -298,8 +336,9 @@ static void notify_quad( void )
push_notify( notify_quad, 4, vb.vertex_store );
}
/* After the 4th vertex, emit either a quad or a flipped quad each two
* vertices:
/*
* After the 4th vertex, emit either a quad or a flipped quad each two
* vertices.
*/
static void notify_qstrip1( void );
static void notify_qstrip0( void )
@ -316,8 +355,10 @@ static void notify_qstrip1( void )
push_notify( notify_qstrip0, 2, vb.vertex_store + 2*vb.vertex_size );
}
/* Emit the saved vertex (but hang on to it for later). Continue
* processing this primitive as a linestrip.
/**
* \brief Emit the saved vertex (but hang on to it for later).
*
* Continue processing this primitive as a linestrip.
*/
static void notify_lineloop0( void )
{
@ -645,7 +686,12 @@ void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
}
/**
* Called by radeonPointsBitmap to disable TCL.
* \brief Called by radeonPointsBitmap() to disable TCL.
*
* \param rmesa Radeon context.
* \param flag whether to enable or disable TCL.
*
* Updates radeon_tcl_info::tcl_flag.
*/
void radeonSubsetVtxEnableTCL( radeonContextPtr rmesa, GLboolean flag )
{

203
src/mesa/drivers/dri/radeon/server/radeon_common.h
View file

@ -1,6 +1,6 @@
/**
* \file server/radeon_common.h
* \brief Common header definitions for Radeon 2D/3D/DRM suite.
* \brief Common header definitions for Radeon 2D/3D/DRM driver suite.
*
* \author Gareth Hughes <gareth@valinux.com>
* \author Kevin E. Martin <martin@valinux.com>
@ -279,115 +279,142 @@ typedef struct {
drmClipRect *boxes;
} drmRadeonCmdBuffer;
/* New style per-packet identifiers for use in cmd_buffer ioctl with
* the RADEON_EMIT_PACKET command. Comments relate new packets to old
* state bits and the packet size:
/**
* \brief New style per-packet identifiers for use in cmd_buffer IOCTL with
* the RADEON_EMIT_PACKET command.
*
* \note Comments relate new packets to old state bits and the packet size.
*/
#define RADEON_EMIT_PP_MISC 0 /* context/7 */
#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/6 */
#define R200_EMIT_TFACTOR_0 30 /* tf/6 */
#define R200_EMIT_VTX_FMT_0 31 /* vtx/4 */
#define R200_EMIT_VAP_CTL 32 /* vap/1 */
#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
#define R200_EMIT_PP_CUBIC_FACES_0 61
#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
#define R200_EMIT_PP_CUBIC_FACES_1 63
#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
#define R200_EMIT_PP_CUBIC_FACES_2 65
#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
#define R200_EMIT_PP_CUBIC_FACES_3 67
#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
#define R200_EMIT_PP_CUBIC_FACES_4 69
#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
#define R200_EMIT_PP_CUBIC_FACES_5 71
#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
#define RADEON_MAX_STATE_PACKETS 73
enum {
RADEON_EMIT_PP_MISC = 0, /* context/7 */
RADEON_EMIT_PP_CNTL = 1, /* context/3 */
RADEON_EMIT_RB3D_COLORPITCH = 2, /* context/1 */
RADEON_EMIT_RE_LINE_PATTERN = 3, /* line/2 */
RADEON_EMIT_SE_LINE_WIDTH = 4, /* line/1 */
RADEON_EMIT_PP_LUM_MATRIX = 5, /* bumpmap/1 */
RADEON_EMIT_PP_ROT_MATRIX_0 = 6, /* bumpmap/2 */
RADEON_EMIT_RB3D_STENCILREFMASK = 7, /* masks/3 */
RADEON_EMIT_SE_VPORT_XSCALE = 8, /* viewport/6 */
RADEON_EMIT_SE_CNTL = 9, /* setup/2 */
RADEON_EMIT_SE_CNTL_STATUS = 10, /* setup/1 */
RADEON_EMIT_RE_MISC = 11, /* misc/1 */
RADEON_EMIT_PP_TXFILTER_0 = 12, /* tex0/6 */
RADEON_EMIT_PP_BORDER_COLOR_0 = 13, /* tex0/1 */
RADEON_EMIT_PP_TXFILTER_1 = 14, /* tex1/6 */
RADEON_EMIT_PP_BORDER_COLOR_1 = 15, /* tex1/1 */
RADEON_EMIT_PP_TXFILTER_2 = 16, /* tex2/6 */
RADEON_EMIT_PP_BORDER_COLOR_2 = 17, /* tex2/1 */
RADEON_EMIT_SE_ZBIAS_FACTOR = 18, /* zbias/2 */
RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT = 19, /* tcl/11 */
RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED = 20, /* material/17 */
R200_EMIT_PP_TXCBLEND_0 = 21, /* tex0/4 */
R200_EMIT_PP_TXCBLEND_1 = 22, /* tex1/4 */
R200_EMIT_PP_TXCBLEND_2 = 23, /* tex2/4 */
R200_EMIT_PP_TXCBLEND_3 = 24, /* tex3/4 */
R200_EMIT_PP_TXCBLEND_4 = 25, /* tex4/4 */
R200_EMIT_PP_TXCBLEND_5 = 26, /* tex5/4 */
R200_EMIT_PP_TXCBLEND_6 = 27, /* /4 */
R200_EMIT_PP_TXCBLEND_7 = 28, /* /4 */
R200_EMIT_TCL_LIGHT_MODEL_CTL_0 = 29, /* tcl/6 */
R200_EMIT_TFACTOR_0 = 30, /* tf/6 */
R200_EMIT_VTX_FMT_0 = 31, /* vtx/4 */
R200_EMIT_VAP_CTL = 32, /* vap/1 */
R200_EMIT_MATRIX_SELECT_0 = 33, /* msl/5 */
R200_EMIT_TEX_PROC_CTL_2 = 34, /* tcg/5 */
R200_EMIT_TCL_UCP_VERT_BLEND_CTL = 35, /* tcl/1 */
R200_EMIT_PP_TXFILTER_0 = 36, /* tex0/6 */
R200_EMIT_PP_TXFILTER_1 = 37, /* tex1/6 */
R200_EMIT_PP_TXFILTER_2 = 38, /* tex2/6 */
R200_EMIT_PP_TXFILTER_3 = 39, /* tex3/6 */
R200_EMIT_PP_TXFILTER_4 = 40, /* tex4/6 */
R200_EMIT_PP_TXFILTER_5 = 41, /* tex5/6 */
R200_EMIT_PP_TXOFFSET_0 = 42, /* tex0/1 */
R200_EMIT_PP_TXOFFSET_1 = 43, /* tex1/1 */
R200_EMIT_PP_TXOFFSET_2 = 44, /* tex2/1 */
R200_EMIT_PP_TXOFFSET_3 = 45, /* tex3/1 */
R200_EMIT_PP_TXOFFSET_4 = 46, /* tex4/1 */
R200_EMIT_PP_TXOFFSET_5 = 47, /* tex5/1 */
R200_EMIT_VTE_CNTL = 48, /* vte/1 */
R200_EMIT_OUTPUT_VTX_COMP_SEL = 49, /* vtx/1 */
R200_EMIT_PP_TAM_DEBUG3 = 50, /* tam/1 */
R200_EMIT_PP_CNTL_X = 51, /* cst/1 */
R200_EMIT_RB3D_DEPTHXY_OFFSET = 52, /* cst/1 */
R200_EMIT_RE_AUX_SCISSOR_CNTL = 53, /* cst/1 */
R200_EMIT_RE_SCISSOR_TL_0 = 54, /* cst/2 */
R200_EMIT_RE_SCISSOR_TL_1 = 55, /* cst/2 */
R200_EMIT_RE_SCISSOR_TL_2 = 56, /* cst/2 */
R200_EMIT_SE_VAP_CNTL_STATUS = 57, /* cst/1 */
R200_EMIT_SE_VTX_STATE_CNTL = 58, /* cst/1 */
R200_EMIT_RE_POINTSIZE = 59, /* cst/1 */
R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 = 60, /* cst/4 */
R200_EMIT_PP_CUBIC_FACES_0 = 61,
R200_EMIT_PP_CUBIC_OFFSETS_0 = 62,
R200_EMIT_PP_CUBIC_FACES_1 = 63,
R200_EMIT_PP_CUBIC_OFFSETS_1 = 64,
R200_EMIT_PP_CUBIC_FACES_2 = 65,
R200_EMIT_PP_CUBIC_OFFSETS_2 = 66,
R200_EMIT_PP_CUBIC_FACES_3 = 67,
R200_EMIT_PP_CUBIC_OFFSETS_3 = 68,
R200_EMIT_PP_CUBIC_FACES_4 = 69,
R200_EMIT_PP_CUBIC_OFFSETS_4 = 70,
R200_EMIT_PP_CUBIC_FACES_5 = 71,
R200_EMIT_PP_CUBIC_OFFSETS_5 = 72,
RADEON_MAX_STATE_PACKETS = 73
} ;
/* Commands understood by cmd_buffer ioctl. More can be added but
* obviously these can't be removed or changed:
/**
* \brief Command types understood by cmd_buffer IOCTL.
*
* More can be added but obviously these can't be removed or changed.
*
* \sa drmRadeonCmdHeader.
*/
#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
#define RADEON_CMD_SCALARS 2 /* emit scalar data */
#define RADEON_CMD_VECTORS 3 /* emit vector data */
#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
#define RADEON_CMD_PACKET3 5 /* emit hw packet */
#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
#define RADEON_CMD_SCALARS2 7 /* R200 stopgap */
#define RADEON_CMD_WAIT 8 /* synchronization */
enum drmRadeonCmdType {
RADEON_CMD_PACKET = 1, /**< \brief emit one of the register packets above */
RADEON_CMD_SCALARS = 2, /**< \brief emit scalar data */
RADEON_CMD_VECTORS = 3, /**< \brief emit vector data */
RADEON_CMD_DMA_DISCARD = 4, /**< \brief discard current DMA buffer */
RADEON_CMD_PACKET3 = 5, /**< \brief emit hw packet */
RADEON_CMD_PACKET3_CLIP = 6, /**< \brief emit hw packet wrapped in cliprects */
RADEON_CMD_SCALARS2 = 7, /**< \brief R200 stopgap */
RADEON_CMD_WAIT = 8 /**< \brief synchronization */
} ;
/**
* \brief Commands understood by cmd_buffer IOCTL.
*
* \sa drmRadeonCmdType.
*/
typedef union {
/** \brief integer equivalent */
int i;
struct {
unsigned char cmd_type, pad0, pad1, pad2;
} header;
/** \brief emit a register packet */
struct {
unsigned char cmd_type, packet_id, pad0, pad1;
} packet;
/** \brief scalar data */
struct {
unsigned char cmd_type, offset, stride, count;
} scalars;
/** \brief vector data */
struct {
unsigned char cmd_type, offset, stride, count;
} vectors;
/** \brief discard current DMA buffer */
struct {
unsigned char cmd_type, buf_idx, pad0, pad1;
} dma;
/** \brief synchronization */
struct {
unsigned char cmd_type, flags, pad0, pad1;
} wait;

2
src/mesa/drivers/dri/radeon/server/radeon_sarea.h
View file

@ -1,6 +1,6 @@
/**
* \file server/radeon_sarea.h
* \brief SAREA definition for the Radeon driver.
* \brief SAREA definition.
*
* \author Kevin E. Martin <martin@xfree86.org>
* \author Gareth Hughes <gareth@valinux.com>