fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-31 18:30:09 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

iris: Emit CS Stall before Instruction Cache flush for gen12 WA

Browse source 
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
This commit is contained in:
Jordan Justen 2020-01-16 13:16:24 -08:00 • committed by Marge Bot
parent b175effc72
commit da03e07cc2
1 changed files with 12 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
src/gallium/drivers/iris/iris_state.c
View file

@ -6848,6 +6848,18 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
0, NULL, 0, 0);
}
/* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
* invalidates the instruction cache
*/
if (GEN_GEN == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) {
iris_emit_raw_pipe_control(batch,
"workaround: CS stall before instruction "
"cache invalidate",
PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset,
imm);
}
if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*