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i965/barrier: Do the correct flushes for framebuffer access

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Framebuffer access includes framebuffer reads so we need to invalidate
the texture cache.  We do not, however, need to flush the depth cache
because you cannot do bind a depth texture as an image.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2017-06-14 22:28:25 -07:00 • committed by Kenneth Graunke
parent 45991479a3
commit d9ed4f6c32
1 changed files with 1 additions and 1 deletions
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src/mesa/drivers/dri/i965/brw_program.c
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@ -274,7 +274,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield barriers)
PIPE_CONTROL_RENDER_TARGET_FLUSH);
if (barriers & GL_FRAMEBUFFER_BARRIER_BIT)
bits |= (PIPE_CONTROL_DEPTH_CACHE_FLUSH |
bits |= (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_RENDER_TARGET_FLUSH);
/* Typed surface messages are handled by the render cache on IVB, so we