From d9d1894bb950697c163ac9e875e4e95bd1b71287 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 25 Nov 2024 15:11:22 +0200 Subject: [PATCH] anv: move tracking of tcs_input_vertices/fs_msaa_flags to hw state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Lionel Landwerlin Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/anv_private.h | 28 +++++++++---- src/intel/vulkan/genX_blorp_exec.c | 1 - src/intel/vulkan/genX_gfx_state.c | 59 ++++++++++++++------------- src/intel/vulkan/genX_simple_shader.c | 1 - 4 files changed, 50 insertions(+), 39 deletions(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 27c01937a15..f380edfaadb 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1480,6 +1480,8 @@ enum anv_gfx_state_bits { ANV_GFX_STATE_WA_18019816803, /* Fake state to implement workaround */ ANV_GFX_STATE_WA_14018283232, /* Fake state to implement workaround */ ANV_GFX_STATE_TBIMR_TILE_PASS_INFO, + ANV_GFX_STATE_FS_MSAA_FLAGS, + ANV_GFX_STATE_TCS_INPUT_VERTICES, ANV_GFX_STATE_MAX, }; @@ -1770,6 +1772,21 @@ struct anv_gfx_dynamic_state { } tbimr; bool use_tbimr; + /** + * Dynamic msaa flags, this value can be different from + * anv_push_constants::gfx::fs_msaa_flags, as the push constant value only + * needs to be updated for fragment shaders dynamically checking the value. + */ + enum intel_msaa_flags fs_msaa_flags; + + /** + * Dynamic TCS input vertices, this value can be different from + * anv_driver_constants::gfx::tcs_input_vertices, as the push constant + * value only needs to be updated for tesselation control shaders + * dynamically checking the value. + */ + uint32_t tcs_input_vertices; + bool pma_fix; /** @@ -3355,9 +3372,8 @@ enum anv_cmd_dirty_bits { ANV_CMD_DIRTY_XFB_ENABLE = 1 << 4, ANV_CMD_DIRTY_RESTART_INDEX = 1 << 5, ANV_CMD_DIRTY_OCCLUSION_QUERY_ACTIVE = 1 << 6, - ANV_CMD_DIRTY_FS_MSAA_FLAGS = 1 << 7, - ANV_CMD_DIRTY_COARSE_PIXEL_ACTIVE = 1 << 8, - ANV_CMD_DIRTY_INDIRECT_DATA_STRIDE = 1 << 9, + ANV_CMD_DIRTY_COARSE_PIXEL_ACTIVE = 1 << 7, + ANV_CMD_DIRTY_INDIRECT_DATA_STRIDE = 1 << 8, }; typedef enum anv_cmd_dirty_bits anv_cmd_dirty_mask_t; @@ -3911,12 +3927,6 @@ struct anv_cmd_graphics_state { struct vk_vertex_input_state vertex_input; struct vk_sample_locations_state sample_locations; - /* Dynamic msaa flags, this value can be different from - * anv_push_constants::gfx::fs_msaa_flags, as the push constant value only - * needs to be updated for fragment shaders dynamically checking the value. - */ - enum intel_msaa_flags fs_msaa_flags; - bool object_preemption; bool has_uint_rt; diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index baa70522bcb..c5c8c0e707a 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -427,7 +427,6 @@ blorp_exec_on_render(struct blorp_batch *batch, anv_cmd_dirty_mask_t dirty = ~(ANV_CMD_DIRTY_INDEX_BUFFER | ANV_CMD_DIRTY_XFB_ENABLE | ANV_CMD_DIRTY_OCCLUSION_QUERY_ACTIVE | - ANV_CMD_DIRTY_FS_MSAA_FLAGS | ANV_CMD_DIRTY_RESTART_INDEX | ANV_CMD_DIRTY_COARSE_PIXEL_ACTIVE); diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index c8d46c44988..fc972d6b8fd 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -745,23 +745,14 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) /* Check the last push constant value and update */ - if (gfx->base.push_constants.gfx.fs_msaa_flags != fs_msaa_flags) { - gfx->base.push_constants.gfx.fs_msaa_flags = fs_msaa_flags; - cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT; - gfx->base.push_constants_data_dirty = true; - } + SET(FS_MSAA_FLAGS, fs_msaa_flags, fs_msaa_flags); } } - - if (fs_msaa_flags != gfx->fs_msaa_flags) { - gfx->fs_msaa_flags = fs_msaa_flags; - gfx->dirty |= ANV_CMD_DIRTY_FS_MSAA_FLAGS; - } } if ((gfx->dirty & ANV_CMD_DIRTY_PIPELINE) || - (gfx->dirty & ANV_CMD_DIRTY_FS_MSAA_FLAGS) || - (gfx->dirty & ANV_CMD_DIRTY_COARSE_PIXEL_ACTIVE)) { + (gfx->dirty & ANV_CMD_DIRTY_COARSE_PIXEL_ACTIVE) || + BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_FS_MSAA_FLAGS)) { if (wm_prog_data) { const struct anv_shader_bin *fs_bin = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; @@ -769,7 +760,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) struct GENX(3DSTATE_PS) ps = {}; intel_set_ps_dispatch_state(&ps, device->info, wm_prog_data, MAX2(dyn->ms.rasterization_samples, 1), - gfx->fs_msaa_flags); + hw_state->fs_msaa_flags); SET(PS, ps.KernelStartPointer0, fs_bin->kernel.offset + @@ -806,14 +797,14 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) SET(PS, ps.PositionXYOffsetSelect, !wm_prog_data->uses_pos_offset ? POSOFFSET_NONE : - brw_wm_prog_data_is_persample(wm_prog_data, gfx->fs_msaa_flags) ? + brw_wm_prog_data_is_persample(wm_prog_data, hw_state->fs_msaa_flags) ? POSOFFSET_SAMPLE : POSOFFSET_CENTROID); SET(PS_EXTRA, ps_extra.PixelShaderIsPerSample, - brw_wm_prog_data_is_persample(wm_prog_data, gfx->fs_msaa_flags)); + brw_wm_prog_data_is_persample(wm_prog_data, hw_state->fs_msaa_flags)); #if GFX_VER >= 11 const bool uses_coarse_pixel = - brw_wm_prog_data_is_coarse(wm_prog_data, gfx->fs_msaa_flags); + brw_wm_prog_data_is_coarse(wm_prog_data, hw_state->fs_msaa_flags); SET(PS_EXTRA, ps_extra.PixelShaderIsPerCoarsePixel, uses_coarse_pixel); #endif #if GFX_VERx10 >= 125 @@ -832,7 +823,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) SET(PS_EXTRA, ps_extra.EnablePSDependencyOnCPsizeChange, needs_ps_dependency); #endif SET(WM, wm.BarycentricInterpolationMode, - wm_prog_data_barycentric_modes(wm_prog_data, gfx->fs_msaa_flags)); + wm_prog_data_barycentric_modes(wm_prog_data, hw_state->fs_msaa_flags)); } else { #if GFX_VER < 20 SET(PS, ps._8PixelDispatchEnable, false); @@ -926,10 +917,10 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) #if GFX_VER >= 11 if (cmd_buffer->device->vk.enabled_extensions.KHR_fragment_shading_rate && ((gfx->dirty & ANV_CMD_DIRTY_PIPELINE) || - (gfx->dirty & ANV_CMD_DIRTY_FS_MSAA_FLAGS) || - BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_FSR))) { + BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_FSR) || + BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_FS_MSAA_FLAGS))) { const bool cps_enable = wm_prog_data && - brw_wm_prog_data_is_coarse(wm_prog_data, gfx->fs_msaa_flags); + brw_wm_prog_data_is_coarse(wm_prog_data, hw_state->fs_msaa_flags); #if GFX_VER == 11 SET(CPS, cps.CoarsePixelShadingMode, cps_enable ? CPS_MODE_CONSTANT : CPS_MODE_NONE); @@ -1746,20 +1737,14 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) } #endif - struct anv_push_constants *push = &cmd_buffer->state.gfx.base.push_constants; - /* If the pipeline uses a dynamic value of patch_control_points and either * the pipeline change or the dynamic value change, check the value and * reemit if needed. */ if (pipeline->dynamic_patch_control_points && ((gfx->dirty & ANV_CMD_DIRTY_PIPELINE) || - BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_PATCH_CONTROL_POINTS)) && - push->gfx.tcs_input_vertices != dyn->ts.patch_control_points) { - push->gfx.tcs_input_vertices = dyn->ts.patch_control_points; - cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT; - gfx->base.push_constants_data_dirty = true; - } + BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_PATCH_CONTROL_POINTS))) + SET(TCS_INPUT_VERTICES, tcs_input_vertices, dyn->ts.patch_control_points); #undef GET #undef SET @@ -1871,6 +1856,8 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer) anv_pipeline_to_graphics(gfx->base.pipeline); const struct vk_dynamic_graphics_state *dyn = &cmd_buffer->vk.dynamic_graphics_state; + struct anv_push_constants *push_consts = + &cmd_buffer->state.gfx.base.push_constants; struct anv_gfx_dynamic_state *hw_state = &gfx->dyn_state; const bool protected = cmd_buffer->vk.pool->flags & VK_COMMAND_POOL_CREATE_PROTECTED_BIT; @@ -1889,6 +1876,22 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer) BITSET_CLEAR(hw_state->dirty, ANV_GFX_STATE_DS); #endif + /* + * Values provided by push constants + */ + + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_TCS_INPUT_VERTICES)) { + push_consts->gfx.tcs_input_vertices = dyn->ts.patch_control_points; + cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT; + gfx->base.push_constants_data_dirty = true; + } + + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_FS_MSAA_FLAGS)) { + push_consts->gfx.fs_msaa_flags = hw_state->fs_msaa_flags; + cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT; + gfx->base.push_constants_data_dirty = true; + } + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_URB)) { genX(urb_workaround)(cmd_buffer, &pipeline->urb_cfg); diff --git a/src/intel/vulkan/genX_simple_shader.c b/src/intel/vulkan/genX_simple_shader.c index 062db96c4f0..1f3c51fc422 100644 --- a/src/intel/vulkan/genX_simple_shader.c +++ b/src/intel/vulkan/genX_simple_shader.c @@ -367,7 +367,6 @@ genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state) state->cmd_buffer->state.gfx.dirty |= ~(ANV_CMD_DIRTY_INDEX_BUFFER | ANV_CMD_DIRTY_XFB_ENABLE | ANV_CMD_DIRTY_OCCLUSION_QUERY_ACTIVE | - ANV_CMD_DIRTY_FS_MSAA_FLAGS | ANV_CMD_DIRTY_RESTART_INDEX); state->cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT; state->cmd_buffer->state.gfx.push_constant_stages = VK_SHADER_STAGE_FRAGMENT_BIT;