From d9bfe075a591c623ca9e80c452afd69ea61d354e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 19 Aug 2024 21:02:21 -0400 Subject: [PATCH] radeonsi: don't use SI_COHERENCY_CB_META Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute_blit.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index 4736bc8ac45..829f31fe943 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -514,6 +514,10 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) { assert(sctx->gfx_level < GFX12); + /* Flush and wait for CB before retiling DCC. */ + sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB; + si_mark_atom_dirty(sctx, &sctx->atoms.s.cache_flush); + /* Set the DCC buffer. */ assert(tex->surface.meta_offset && tex->surface.meta_offset <= UINT_MAX); assert(tex->surface.display_dcc_offset && tex->surface.display_dcc_offset <= UINT_MAX); @@ -546,7 +550,7 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex) set_work_size(&info, 8, 8, 1, width, height, 1); si_launch_grid_internal_ssbos(sctx, &info, *shader, SI_OP_SYNC_BEFORE, - SI_COHERENCY_CB_META, 1, &sb, 0x1); + SI_COHERENCY_SHADER, 1, &sb, 0x1); /* Don't flush caches. L2 will be flushed by the kernel fence. */ }