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ac: Add variable slice mode interface

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Co-authored-by: Benjamin Cheng <benjamin.cheng@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40329>
This commit is contained in:
David Rosca 2025-10-28 17:16:31 -04:00 • committed by Marge Bot
parent efcc8b6d89
commit d9ba641e28
2 changed files with 44 additions and 0 deletions
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18
src/amd/common/ac_vcn_enc.c
View file

@ -10,6 +10,7 @@
#include <stdbool.h>
#include "ac_vcn_enc.h"
#include "ac_gpu_info.h"
#define RENCODE_IB_PARAM_SESSION_INFO 0x00000001
#define RENCODE_IB_PARAM_TASK_INFO 0x00000002
@ -35,11 +36,13 @@
#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
#define RENCODE_HEVC_IB_PARAM_SPEC_MISC 0x00100002
#define RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER 0x00100003
#define RENCODE_HEVC_IB_PARAM_SLICE_INFO_VAR 0x00100004
#define RENCODE_H264_IB_PARAM_SLICE_CONTROL 0x00200001
#define RENCODE_H264_IB_PARAM_SPEC_MISC 0x00200002
#define RENCODE_H264_IB_PARAM_ENCODE_PARAMS 0x00200003
#define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER 0x00200004
#define RENCODE_H264_IB_PARAM_SLICE_INFO_VAR 0x00200005
#define RENCODE_V2_IB_PARAM_DIRECT_OUTPUT_NALU 0x0000000a
#define RENCODE_V2_IB_PARAM_SLICE_HEADER 0x0000000b
@ -62,6 +65,7 @@
#define RENCODE_V5_IB_PARAM_METADATA_BUFFER 0x0000001c
#define RENCODE_V5_IB_PARAM_ENCODE_CONTEXT_BUFFER_OVERRIDE 0x0000001d
#define RENCODE_V5_HEVC_IB_PARAM_ENCODE_PARAMS 0x00100004
#define RENCODE_V5_HEVC_IB_PARAM_SLICE_INFO_VAR 0x00100005
#define RENCODE_V5_AV1_IB_PARAM_TILE_CONFIG 0x00300002
#define RENCODE_V5_AV1_IB_PARAM_BITSTREAM_INSTRUCTION 0x00300003
#define RENCODE_V5_AV1_IB_PARAM_ENCODE_PARAMS 0x00300004
@ -116,6 +120,8 @@ void ac_vcn_enc_init_cmds(rvcn_enc_cmd_t *cmd, enum vcn_version version)
cmd->enc_statistics = RENCODE_V4_IB_PARAM_ENCODE_STATISTICS;
cmd->spec_misc_av1 = RENCODE_V4_AV1_IB_PARAM_SPEC_MISC;
cmd->bitstream_instruction_av1 = RENCODE_V4_AV1_IB_PARAM_BITSTREAM_INSTRUCTION;
cmd->slice_info_h264 = RENCODE_H264_IB_PARAM_SLICE_INFO_VAR;
cmd->slice_info_hevc = RENCODE_HEVC_IB_PARAM_SLICE_INFO_VAR;
}
if (version >= VCN_5_0_0) {
@ -125,5 +131,17 @@ void ac_vcn_enc_init_cmds(rvcn_enc_cmd_t *cmd, enum vcn_version version)
cmd->tile_config_av1 = RENCODE_V5_AV1_IB_PARAM_TILE_CONFIG;
cmd->bitstream_instruction_av1 = RENCODE_V5_AV1_IB_PARAM_BITSTREAM_INSTRUCTION;
cmd->enc_params_av1 = RENCODE_V5_AV1_IB_PARAM_ENCODE_PARAMS;
cmd->slice_info_hevc = RENCODE_V5_HEVC_IB_PARAM_SLICE_INFO_VAR;
}
}
bool
ac_vcn_enc_variable_slice_mode_supported(const struct radeon_info *info)
{
if (info->vcn_ip_version >= VCN_5_0_0)
return info->vcn_enc_minor_version >= 11;
else if (info->vcn_ip_version >= VCN_4_0_0)
return info->vcn_enc_minor_version >= 24;
else
return false;
}

26
src/amd/common/ac_vcn_enc.h
View file

@ -66,9 +66,11 @@
#define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS 0x00000000
#define RENCODE_H264_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
#define RENCODE_H264_SLICE_CONTROL_MODE_VARIABLE_MBS 0x00000002
#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS 0x00000000
#define RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_BITS 0x00000001
#define RENCODE_HEVC_SLICE_CONTROL_MODE_VARIABLE_CTBS 0x00000002
#define RENCODE_RATE_CONTROL_METHOD_NONE 0x00000000
#define RENCODE_RATE_CONTROL_METHOD_LATENCY_CONSTRAINED_VBR 0x00000001
@ -684,6 +686,8 @@ typedef struct rvcn_enc_cmd_s {
uint32_t metadata;
uint32_t ctx_override;
uint32_t enc_latency;
uint32_t slice_info_hevc;
uint32_t slice_info_h264;
} rvcn_enc_cmd_t;
typedef struct rvcn_enc_quality_modes_s
@ -753,6 +757,28 @@ typedef struct rvcn_enc_latency_s
uint32_t encode_latency;
} rvcn_enc_latency_t;
#define RENCODE_MAX_NUM_SLICES 32
typedef struct rvcn_enc_h264_slice_info_var_s
{
uint32_t num_slices;
struct slice_info
{
uint32_t num_mbs_per_slice;
} slice_info[RENCODE_MAX_NUM_SLICES];
} rvcn_enc_h264_slice_info_var_t;
typedef struct rvcn_enc_hevc_slice_info_var_s
{
uint32_t num_slice_segments;
struct slice_segment_info
{
uint32_t num_ctbs_per_segment;
uint32_t is_independent;
} slice_segment_info[RENCODE_MAX_NUM_SLICES];
} rvcn_enc_hevc_slice_info_var_t;
void ac_vcn_enc_init_cmds(rvcn_enc_cmd_t *cmd, enum vcn_version version);
bool ac_vcn_enc_variable_slice_mode_supported(const struct radeon_info *info);
#endif