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synced 2026-01-21 21:40:22 +01:00
fixup draw/depth region handling in i830 along lines of i915
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parent
6ab6518735
commit
d98e1f3761
3 changed files with 75 additions and 47 deletions
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@ -156,6 +156,11 @@ do { \
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*/
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extern void i830InitVtbl(struct i830_context *i830);
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extern void
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i830_state_draw_region(struct intel_context *intel,
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struct i830_hw_state *state,
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struct intel_region *color_region,
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struct intel_region *depth_region);
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/* i830_context.c
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*/
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extern GLboolean
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@ -400,40 +400,12 @@ meta_import_pixel_state(struct intel_context *intel)
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*/
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static void
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meta_draw_region(struct intel_context *intel,
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struct intel_region *draw_region,
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struct intel_region *color_region,
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struct intel_region *depth_region)
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{
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struct i830_context *i830 = i830_context(&intel->ctx);
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GLuint format;
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GLuint depth_format = DEPTH_FRMT_16_FIXED;
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intel_region_release(&i830->meta.draw_region);
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intel_region_reference(&i830->meta.draw_region, draw_region);
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intel_region_release(&i830->meta.depth_region);
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intel_region_reference(&i830->meta.depth_region, depth_region);
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/* XXX FBO: grab code from i915 meta_draw_region */
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/* XXX: 555 support?
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*/
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if (draw_region->cpp == 2)
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format = DV_PF_565;
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else
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format = DV_PF_8888;
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if (depth_region) {
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if (depth_region->cpp == 2)
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depth_format = DEPTH_FRMT_16_FIXED;
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else
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depth_format = DEPTH_FRMT_24_FIXED_8_OTHER;
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}
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i830->meta.Buffer[I830_DESTREG_DV1] = (DSTORG_HORT_BIAS(0x8) | /* .5 */
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DSTORG_VERT_BIAS(0x8) | /* .5 */
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format | DEPTH_IS_Z | depth_format);
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i830->meta.emitted &= ~I830_UPLOAD_BUFFERS;
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i830_state_draw_region(intel, &i830->meta, color_region, depth_region);
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}
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@ -518,28 +518,79 @@ i830_destroy_context(struct intel_context *intel)
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_tnl_free_vertices(&intel->ctx);
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}
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void
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i830_state_draw_region(struct intel_context *intel,
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struct i830_hw_state *state,
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struct intel_region *color_region,
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struct intel_region *depth_region)
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{
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struct i830_context *i830 = i830_context(&intel->ctx);
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GLuint value;
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ASSERT(state == &i830->state || state == &i830->meta);
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if (state->draw_region != color_region) {
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intel_region_release(&state->draw_region);
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intel_region_reference(&state->draw_region, color_region);
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}
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if (state->depth_region != depth_region) {
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intel_region_release(&state->depth_region);
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intel_region_reference(&state->depth_region, depth_region);
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}
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/*
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* Set stride/cpp values
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*/
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if (color_region) {
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state->Buffer[I830_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
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state->Buffer[I830_DESTREG_CBUFADDR1] =
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(BUF_3D_ID_COLOR_BACK |
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BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
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BUF_3D_USE_FENCE);
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}
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if (depth_region) {
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state->Buffer[I830_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
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state->Buffer[I830_DESTREG_DBUFADDR1] =
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(BUF_3D_ID_DEPTH |
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BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
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BUF_3D_USE_FENCE);
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}
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/*
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* Compute/set I830_DESTREG_DV1 value
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*/
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value = (DSTORG_HORT_BIAS(0x8) | /* .5 */
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DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */
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if (color_region && color_region->cpp == 4) {
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value |= DV_PF_8888;
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}
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else {
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value |= DV_PF_565;
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}
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if (depth_region && depth_region->cpp == 4) {
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value |= DEPTH_FRMT_24_FIXED_8_OTHER;
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}
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else {
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value |= DEPTH_FRMT_16_FIXED;
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}
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state->Buffer[I830_DESTREG_DV1] = value;
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I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
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}
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static void
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i830_set_draw_region(struct intel_context *intel,
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struct intel_region *draw_region,
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struct intel_region *color_region,
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struct intel_region *depth_region)
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{
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struct i830_context *i830 = i830_context(&intel->ctx);
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intel_region_release(&i830->state.draw_region);
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intel_region_release(&i830->state.depth_region);
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intel_region_reference(&i830->state.draw_region, draw_region);
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intel_region_reference(&i830->state.depth_region, depth_region);
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/* XXX FBO: Need code from i915_set_draw_region() */
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I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
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I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
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i830->state.Buffer[I830_DESTREG_CBUFADDR1] =
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(BUF_3D_ID_COLOR_BACK | BUF_3D_PITCH(draw_region->pitch) |
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BUF_3D_USE_FENCE);
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i830->state.Buffer[I830_DESTREG_DBUFADDR1] =
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(BUF_3D_ID_DEPTH | BUF_3D_PITCH(depth_region->pitch) |
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BUF_3D_USE_FENCE);
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i830_state_draw_region(intel, &i830->state, color_region, depth_region);
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}
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#if 0
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