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radv: refactor some texture descriptor state.

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This just splits out some non-gfx9 bits in advance to avoid
regressions.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2017-06-05 02:09:30 +01:00
parent a5d181f60b
commit d987f90354
1 changed files with 17 additions and 9 deletions
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26
src/amd/vulkan/radv_image.c
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@ -310,14 +310,18 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
util_logbase2(image->info.samples) :
last_level) |
S_008F1C_POW2_PAD(image->info.levels > 1) |
S_008F1C_TYPE(type));
state[4] = S_008F20_DEPTH(depth - 1);
state[5] = (S_008F24_BASE_ARRAY(first_layer) |
S_008F24_LAST_ARRAY(last_layer));
state[4] = 0;
state[5] = S_008F24_BASE_ARRAY(first_layer);
state[6] = 0;
state[7] = 0;
{
state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
state[4] |= S_008F20_DEPTH(depth - 1);
state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
if (image->dcc_offset) {
unsigned swap = radv_translate_colorswap(vk_format, FALSE);
@ -367,14 +371,18 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
S_008F1C_TILING_INDEX(image->fmask.tile_mode_index) |
S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 0, false));
fmask_state[4] = S_008F20_DEPTH(depth - 1) |
S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
S_008F24_LAST_ARRAY(last_layer);
fmask_state[4] = 0;
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
fmask_state[6] = 0;
fmask_state[7] = 0;
{
fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
}
}