From d97381efd8c2e39b2e92f0fe78281c04a0249bd2 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Fri, 6 Sep 2024 15:15:19 -0700 Subject: [PATCH] intel/brw: Add fs_builder::BROADCAST() helper Include in the helper which already take care of using exec_all() and taking the first component of the result. Both are expected by SHADER_OPCODE_BROADCAST. Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_fs_builder.h | 16 ++++++++++------ src/intel/compiler/brw_fs_nir.cpp | 7 +++---- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index ca81c491de1..ab93b90e046 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/src/intel/compiler/brw_fs_builder.h @@ -378,14 +378,10 @@ namespace brw { * dispatch. Once we teach const/copy propagation about scalars we * should go back to scalar destinations here. */ - const fs_builder ubld = exec_all(); const brw_reg chan_index = vgrf(BRW_TYPE_UD); - const brw_reg dst = vgrf(src.type); - ubld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index); - ubld.emit(SHADER_OPCODE_BROADCAST, dst, src, component(chan_index, 0)); - - return brw_reg(component(dst, 0)); + exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, chan_index); + return BROADCAST(src, component(chan_index, 0)); } brw_reg @@ -773,6 +769,14 @@ namespace brw { return reg; } + brw_reg + BROADCAST(brw_reg value, brw_reg index) const + { + const brw_reg dst = vgrf(value.type); + exec_all().emit(SHADER_OPCODE_BROADCAST, dst, value, index); + return component(dst, 0); + } + fs_visitor *shader; fs_inst *BREAK() { return emit(BRW_OPCODE_BREAK); } diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 858f9383644..264d6a71967 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -6811,7 +6811,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, break; } - brw_reg tmp = bld.vgrf(value.type); /* When for some reason the subgroup_size picked by NIR is larger than * the dispatch size picked by the backend (this could happen in RT, @@ -6823,10 +6822,10 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, bound_invocation = bld.AND(bound_invocation, brw_imm_ud(s.dispatch_width - 1)); } - bld.exec_all().emit(SHADER_OPCODE_BROADCAST, tmp, value, - bld.emit_uniformize(bound_invocation)); - bld.MOV(retype(dest, value.type), brw_reg(component(tmp, 0))); + brw_reg tmp = bld.BROADCAST(value, bld.emit_uniformize(bound_invocation)); + + bld.MOV(retype(dest, value.type), tmp); break; }