From d918bbfa1cedb38e71255632ca1e44ab3ad7c29d Mon Sep 17 00:00:00 2001
From: Danylo Piliaiev <dpiliaiev@igalia.com>
Date: Thu, 8 Apr 2021 15:06:21 +0300
Subject: [PATCH] ir3: treat 16b imul as mul.s24

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10054>
---
 src/freedreno/ir3/ir3_compiler_nir.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index bfafd4de66f..71bfb9aff78 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -571,6 +571,10 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
 	case nir_op_imad24_ir3:
 		dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
 		break;
+	case nir_op_imul:
+		compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) == 16);
+		dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
+		break;
 	case nir_op_imul24:
 		dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
 		break;