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intel/blorp: Halve the Gen12 fast-clear/resolve rectangle

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Update their dimensions according to the Bspec.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Nanley Chery 2019-05-09 16:38:12 -07:00
parent 43b48ee752
commit d90bffaef8
1 changed files with 9 additions and 4 deletions
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13
src/intel/blorp/blorp_clear.c
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@ -232,10 +232,12 @@ get_fast_clear_rect(const struct isl_device *dev,
x_align *= 16;
/* SKL+ line alignment requirement for Y-tiled are half those of the prior
* generations.
/* The line alignment requirement for Y-tiled is halved at SKL and again
* at TGL.
*/
if (dev->info->gen >= 9)
if (dev->info->gen >= 12)
y_align *= 8;
else if (dev->info->gen >= 9)
y_align *= 16;
else
y_align *= 32;
@ -990,7 +992,10 @@ blorp_ccs_resolve(struct blorp_batch *batch,
assert(aux_fmtl->txc == ISL_TXC_CCS);
unsigned x_scaledown, y_scaledown;
if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 9) {
if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 12) {
x_scaledown = aux_fmtl->bw * 8;
y_scaledown = aux_fmtl->bh * 4;
} else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 9) {
x_scaledown = aux_fmtl->bw * 8;
y_scaledown = aux_fmtl->bh * 8;
} else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 8) {