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radv: Use vk_image_view as the base for radv_image_view

Browse source 
I've left the extent field because, even though it looks like it should
be roughly equivalent, it's weirdly different on different hardware and
I didn't want to mess with it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16376>
This commit is contained in:
Jason Ekstrand 2022-03-25 16:14:19 -05:00 • committed by Marge Bot
parent c56f3dcbaa
commit d9048e31a0
10 changed files with 185 additions and 197 deletions
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90
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1766,7 +1766,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
struct radv_image *image = iview->image;
if (!radv_layout_dcc_compressed(
cmd_buffer->device, image, iview->base_mip, layout, in_render_loop,
cmd_buffer->device, image, iview->vk.base_mip_level, layout, in_render_loop,
radv_image_queue_family_mask(image, cmd_buffer->qf,
cmd_buffer->qf))) {
cb_color_info &= C_028C70_DCC_ENABLE;
@ -1858,11 +1858,11 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,
if (G_028C70_DCC_ENABLE(cb_color_info)) {
/* Drawing with DCC enabled also compresses colorbuffers. */
VkImageSubresourceRange range = {
.aspectMask = iview->aspect_mask,
.baseMipLevel = iview->base_mip,
.levelCount = iview->level_count,
.baseArrayLayer = iview->base_layer,
.layerCount = iview->layer_count,
.aspectMask = iview->vk.aspects,
.baseMipLevel = iview->vk.base_mip_level,
.levelCount = iview->vk.level_count,
.baseArrayLayer = iview->vk.base_array_layer,
.layerCount = iview->vk.layer_count,
};
radv_update_dcc_metadata(cmd_buffer, image, &range, true);
@ -1902,7 +1902,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_
* SET_CONTEXT_REG packet.
*/
if (requires_cond_exec) {
uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip);
uint64_t va = radv_get_tc_compat_zrange_va(image, iview->vk.base_mip_level);
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
radeon_emit(cmd_buffer->cs, va);
@ -2136,11 +2136,11 @@ radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
VkClearDepthStencilValue ds_clear_value)
{
VkImageSubresourceRange range = {
.aspectMask = iview->aspect_mask,
.baseMipLevel = iview->base_mip,
.levelCount = iview->level_count,
.baseArrayLayer = iview->base_layer,
.layerCount = iview->layer_count,
.aspectMask = iview->vk.aspects,
.baseMipLevel = iview->vk.base_mip_level,
.levelCount = iview->vk.level_count,
.baseArrayLayer = iview->vk.base_array_layer,
.layerCount = iview->vk.layer_count,
};
uint32_t cond_val;
@ -2161,11 +2161,11 @@ radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
VkClearDepthStencilValue ds_clear_value, VkImageAspectFlags aspects)
{
VkImageSubresourceRange range = {
.aspectMask = iview->aspect_mask,
.baseMipLevel = iview->base_mip,
.levelCount = iview->level_count,
.baseArrayLayer = iview->base_layer,
.layerCount = iview->layer_count,
.aspectMask = iview->vk.aspects,
.baseMipLevel = iview->vk.base_mip_level,
.levelCount = iview->vk.level_count,
.baseArrayLayer = iview->vk.base_array_layer,
.layerCount = iview->vk.layer_count,
};
struct radv_image *image = iview->image;
@ -2189,7 +2189,7 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const struct rad
struct radeon_cmdbuf *cs = cmd_buffer->cs;
const struct radv_image *image = iview->image;
VkImageAspectFlags aspects = vk_format_aspects(image->vk.format);
uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip);
uint64_t va = radv_get_ds_clear_value_va(image, iview->vk.base_mip_level);
unsigned reg_offset = 0, reg_count = 0;
assert(radv_image_has_htile(image));
@ -2352,14 +2352,14 @@ radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_image *image = iview->image;
VkImageSubresourceRange range = {
.aspectMask = iview->aspect_mask,
.baseMipLevel = iview->base_mip,
.levelCount = iview->level_count,
.baseArrayLayer = iview->base_layer,
.layerCount = iview->layer_count,
.aspectMask = iview->vk.aspects,
.baseMipLevel = iview->vk.base_mip_level,
.levelCount = iview->vk.level_count,
.baseArrayLayer = iview->vk.base_array_layer,
.layerCount = iview->vk.layer_count,
};
assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, iview->base_mip));
assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, iview->vk.base_mip_level));
/* Do not need to update the clear value for images that are fast cleared with the comp-to-single
* mode because the hardware gets the value from the image directly.
@ -2382,7 +2382,7 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i
struct radeon_cmdbuf *cs = cmd_buffer->cs;
struct radv_image *image = iview->image;
if (!radv_image_has_cmask(image) && !radv_dcc_enabled(image, iview->base_mip))
if (!radv_image_has_cmask(image) && !radv_dcc_enabled(image, iview->vk.base_mip_level))
return;
if (iview->image->support_comp_to_single)
@ -2394,7 +2394,7 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i
return;
}
uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip);
uint64_t va = radv_image_get_fast_clear_va(image, iview->vk.base_mip_level);
uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {
@ -2445,12 +2445,12 @@ radv_emit_fb_mip_change_flush(struct radv_cmd_buffer *cmd_buffer)
struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;
if ((radv_image_has_CB_metadata(iview->image) ||
radv_dcc_enabled(iview->image, iview->base_mip) ||
radv_dcc_enabled(iview->image, iview->vk.base_mip_level) ||
radv_dcc_enabled(iview->image, cmd_buffer->state.cb_mip[i])) &&
cmd_buffer->state.cb_mip[i] != iview->base_mip)
cmd_buffer->state.cb_mip[i] != iview->vk.base_mip_level)
color_mip_changed = true;
cmd_buffer->state.cb_mip[i] = iview->base_mip;
cmd_buffer->state.cb_mip[i] = iview->vk.base_mip_level;
}
if (color_mip_changed) {
@ -2527,8 +2527,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->image->bo);
assert(iview->aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
assert(iview->vk.aspects & (VK_IMAGE_ASPECT_COLOR_BIT | VK_IMAGE_ASPECT_PLANE_0_BIT |
VK_IMAGE_ASPECT_PLANE_1_BIT | VK_IMAGE_ASPECT_PLANE_2_BIT));
radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout,
in_render_loop);
@ -4224,10 +4224,10 @@ radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;
struct radv_sample_locations_state *sample_locs;
VkImageSubresourceRange range;
range.aspectMask = view->aspect_mask;
range.baseMipLevel = view->base_mip;
range.aspectMask = view->vk.aspects;
range.baseMipLevel = view->vk.base_mip_level;
range.levelCount = 1;
range.baseArrayLayer = view->base_layer;
range.baseArrayLayer = view->vk.base_array_layer;
range.layerCount = cmd_buffer->state.framebuffer->layers;
if (cmd_buffer->state.subpass->view_mask) {
@ -4435,7 +4435,7 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer, struct radv
}
state->attachments[i].iview = iview;
if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
if (iview->vk.aspects & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);
} else {
radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);
@ -5944,7 +5944,7 @@ radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer, uint32_t subpa
int ds_idx = subpass->depth_stencil_attachment->attachment;
struct radv_image_view *ds_iview = cmd_buffer->state.attachments[ds_idx].iview;
struct radv_image *ds_image = ds_iview->image;
uint32_t level = ds_iview->base_mip;
uint32_t level = ds_iview->vk.base_mip_level;
VkExtent2D extent = {
.width = radv_minify(ds_image->info.width, level),
@ -7810,7 +7810,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
color_refs[i] = (VkAttachmentReference2){.sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2,
.attachment = att_count,
.layout = info->imageLayout,
.aspectMask = iview->aspect_mask};
.aspectMask = iview->vk.aspects};
iviews[att_count] = info->imageView;
clear_values[att_count] = info->clearValue;
@ -7818,7 +7818,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
memset(att, 0, sizeof(*att));
att->sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
att->format = iview->vk_format;
att->format = iview->vk.format;
att->samples = iview->image->info.samples;
att->loadOp = info->loadOp;
att->storeOp = info->storeOp;
@ -7838,14 +7838,14 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
(VkAttachmentReference2){.sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2,
.attachment = att_count,
.layout = info->resolveImageLayout,
.aspectMask = resolve_iview->aspect_mask};
.aspectMask = resolve_iview->vk.aspects};
iviews[att_count] = info->resolveImageView;
att = att_desc + att_count++;
memset(att, 0, sizeof(*att));
att->sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
att->format = resolve_iview->vk_format;
att->format = resolve_iview->vk.format;
att->samples = resolve_iview->image->info.samples;
att->loadOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE;
att->storeOp = VK_ATTACHMENT_STORE_OP_STORE;
@ -7880,7 +7880,7 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
memset(att, 0, sizeof(*att));
att->sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
att->format = iview->vk_format;
att->format = iview->vk.format;
att->samples = iview->image->info.samples;
if (pRenderingInfo->pDepthAttachment) {
@ -7936,14 +7936,14 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
(VkAttachmentReference2){.sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2,
.attachment = att_count,
.layout = common_info->resolveImageLayout,
.aspectMask = resolve_iview->aspect_mask};
.aspectMask = resolve_iview->vk.aspects};
iviews[att_count] = common_info->resolveImageView;
att = att_desc + att_count++;
memset(att, 0, sizeof(*att));
att->sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
att->format = resolve_iview->vk_format;
att->format = resolve_iview->vk.format;
att->samples = resolve_iview->image->info.samples;
att->loadOp = VK_ATTACHMENT_LOAD_OP_DONT_CARE;
att->storeOp = VK_ATTACHMENT_STORE_OP_STORE;
@ -7990,14 +7990,14 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
vrs_ref = (VkAttachmentReference2){.sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2,
.attachment = att_count,
.layout = vrs_info->imageLayout,
.aspectMask = iview->aspect_mask};
.aspectMask = iview->vk.aspects};
iviews[att_count] = vrs_info->imageView;
VkAttachmentDescription2 *att = att_desc + att_count++;
memset(att, 0, sizeof(*att));
att->sType = VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2;
att->format = iview->vk_format;
att->format = iview->vk.format;
att->samples = iview->image->info.samples;
att->loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
att->storeOp = VK_ATTACHMENT_STORE_OP_DONT_CARE;

45
src/amd/vulkan/radv_device.c
View file

@ -5489,8 +5489,8 @@ si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool st
static uint32_t
radv_surface_max_layer_count(struct radv_image_view *iview)
{
return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth
: (iview->base_layer + iview->layer_count);
return iview->vk.view_type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth
: (iview->vk.base_array_layer + iview->vk.layer_count);
}
static unsigned
@ -5531,7 +5531,7 @@ radv_init_dcc_control_reg(struct radv_device *device, struct radv_image_view *iv
unsigned independent_128b_blocks;
unsigned independent_64b_blocks;
if (!radv_dcc_enabled(iview->image, iview->base_mip))
if (!radv_dcc_enabled(iview->image, iview->vk.base_mip_level))
return 0;
/* For GFX9+ ac_surface computes values for us (except min_compressed
@ -5584,7 +5584,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
const struct radeon_surf *surf = &plane->surface;
desc = vk_format_description(iview->vk_format);
desc = vk_format_description(iview->vk.format);
memset(cb, 0, sizeof(*cb));
@ -5623,7 +5623,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
cb->cb_color_base |= surf->tile_swizzle;
} else {
const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->vk.base_mip_level];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
cb->cb_color_base += level_info->offset_256B;
@ -5632,7 +5632,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
pitch_tile_max = level_info->nblk_x / 8 - 1;
slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
tile_mode_index = si_tile_mode_index(plane, iview->vk.base_mip_level, false);
cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
@ -5663,9 +5663,9 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
va = radv_buffer_get_va(iview->image->bo) + iview->image->offset;
va += surf->meta_offset;
if (radv_dcc_enabled(iview->image, iview->base_mip) &&
if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) &&
device->physical_device->rad_info.gfx_level <= GFX8)
va += plane->surface.u.legacy.color.dcc_level[iview->base_mip].dcc_offset;
va += plane->surface.u.legacy.color.dcc_level[iview->vk.base_mip_level].dcc_offset;
unsigned dcc_tile_swizzle = surf->tile_swizzle;
dcc_tile_swizzle &= ((1 << surf->meta_alignment_log2) - 1) >> 8;
@ -5676,7 +5676,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
/* GFX10 field has the same base shift as the GFX6 field. */
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
cb->cb_color_view =
S_028C6C_SLICE_START(iview->base_layer) | S_028C6C_SLICE_MAX_GFX10(max_slice);
S_028C6C_SLICE_START(iview->vk.base_array_layer) | S_028C6C_SLICE_MAX_GFX10(max_slice);
if (iview->image->info.samples > 1) {
unsigned log_samples = util_logbase2(iview->image->info.samples);
@ -5696,12 +5696,12 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
cb->cb_color_fmask = cb->cb_color_base;
}
ntype = radv_translate_color_numformat(iview->vk_format, desc,
vk_format_get_first_non_void_channel(iview->vk_format));
format = radv_translate_colorformat(iview->vk_format);
ntype = radv_translate_color_numformat(iview->vk.format, desc,
vk_format_get_first_non_void_channel(iview->vk.format));
format = radv_translate_colorformat(iview->vk.format);
assert(format != V_028C70_COLOR_INVALID);
swap = radv_translate_colorswap(iview->vk_format, false);
swap = radv_translate_colorswap(iview->vk.format, false);
endian = radv_colorformat_endian_swap(format);
/* blend clamp should be set for all NORM/SRGB types */
@ -5765,7 +5765,7 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
!(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
if (radv_dcc_enabled(iview->image, iview->base_mip) && !iview->disable_dcc_mrt &&
if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level) && !iview->disable_dcc_mrt &&
device->physical_device->rad_info.gfx_level < GFX11)
cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
@ -5787,13 +5787,13 @@ radv_initialise_color_surface(struct radv_device *device, struct radv_color_buff
vk_format_get_plane_height(iview->image->vk.format, iview->plane_id, iview->extent.height);
if (device->physical_device->rad_info.gfx_level >= GFX10) {
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->vk.base_mip_level);
cb->cb_color_attrib3 |=
S_028EE0_MIP0_DEPTH(mip0_depth) | S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
S_028EE0_RESOURCE_LEVEL(device->physical_device->rad_info.gfx_level >= GFX11 ? 0 : 1);
} else {
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->vk.base_mip_level);
cb->cb_color_attrib |=
S_028C74_MIP0_DEPTH(mip0_depth) | S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
}
@ -5814,7 +5814,7 @@ radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_v
/* Default value for 32-bit depth surfaces. */
max_zplanes = 4;
if (iview->vk_format == VK_FORMAT_D16_UNORM && iview->image->info.samples > 1)
if (iview->vk.format == VK_FORMAT_D16_UNORM && iview->image->info.samples > 1)
max_zplanes = 2;
/* Workaround for a DB hang when ITERATE_256 is set to 1. Only affects 4X MSAA D/S images. */
@ -5827,7 +5827,7 @@ radv_calc_decompress_on_z_planes(struct radv_device *device, struct radv_image_v
max_zplanes = max_zplanes + 1;
} else {
if (iview->vk_format == VK_FORMAT_D16_UNORM) {
if (iview->vk.format == VK_FORMAT_D16_UNORM) {
/* Do not enable Z plane compression for 16-bit depth
* surfaces because isn't supported on GFX8. Only
* 32-bit depth surfaces are supported by the hardware.
@ -5877,7 +5877,7 @@ void
radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_info *ds,
struct radv_image_view *iview)
{
unsigned level = iview->base_mip;
unsigned level = iview->vk.base_mip_level;
unsigned format, stencil_format;
uint64_t va, s_offs, z_offs;
bool stencil_only = iview->image->vk.format == VK_FORMAT_S8_UINT;
@ -5911,10 +5911,11 @@ radv_initialise_ds_surface(struct radv_device *device, struct radv_ds_buffer_inf
stencil_format = surf->has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) | S_028008_SLICE_MAX(max_slice);
ds->db_depth_view = S_028008_SLICE_START(iview->vk.base_array_layer) |
S_028008_SLICE_MAX(max_slice);
if (device->physical_device->rad_info.gfx_level >= GFX10) {
ds->db_depth_view |=
S_028008_SLICE_START_HI(iview->base_layer >> 11) | S_028008_SLICE_MAX_HI(max_slice >> 11);
ds->db_depth_view |= S_028008_SLICE_START_HI(iview->vk.base_array_layer >> 11) |
S_028008_SLICE_MAX_HI(max_slice >> 11);
}
ds->db_htile_data_base = 0;

81
src/amd/vulkan/radv_image.c
View file

@ -1934,7 +1934,7 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
{
struct radv_image *image = iview->image;
struct radv_image_plane *plane = &image->planes[plane_id];
bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
bool is_stencil = iview->vk.aspects == VK_IMAGE_ASPECT_STENCIL_BIT;
uint32_t blk_w;
union radv_descriptor *descriptor;
uint32_t hw_level = 0;
@ -1951,11 +1951,11 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
vk_format_get_blockwidth(vk_format);
if (device->physical_device->rad_info.gfx_level >= GFX9)
hw_level = iview->base_mip;
hw_level = iview->vk.base_mip_level;
radv_make_texture_descriptor(
device, image, is_storage_image, iview->type, vk_format, components, hw_level,
hw_level + iview->level_count - 1, iview->base_layer,
iview->base_layer + iview->layer_count - 1,
device, image, is_storage_image, iview->vk.view_type, vk_format, components, hw_level,
hw_level + iview->vk.level_count - 1, iview->vk.base_array_layer,
iview->vk.base_array_layer + iview->vk.layer_count - 1,
vk_format_get_plane_width(image->vk.format, plane_id, iview->extent.width),
vk_format_get_plane_height(image->vk.format, plane_id, iview->extent.height),
iview->extent.depth, min_lod, descriptor->plane_descriptors[descriptor_plane_id],
@ -1965,16 +1965,16 @@ radv_image_view_make_descriptor(struct radv_image_view *iview, struct radv_devic
const struct legacy_surf_level *base_level_info = NULL;
if (device->physical_device->rad_info.gfx_level <= GFX9) {
if (is_stencil)
base_level_info = &plane->surface.u.legacy.zs.stencil_level[iview->base_mip];
base_level_info = &plane->surface.u.legacy.zs.stencil_level[iview->vk.base_mip_level];
else
base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
base_level_info = &plane->surface.u.legacy.level[iview->vk.base_mip_level];
}
bool enable_write_compression = radv_image_use_dcc_image_stores(device, image);
if (is_storage_image && !(enable_write_compression || enable_compression))
disable_compression = true;
si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->base_mip,
iview->base_mip, blk_w, is_stencil, is_storage_image,
si_set_mutable_tex_desc_fields(device, image, base_level_info, plane_id, iview->vk.base_mip_level,
iview->vk.base_mip_level, blk_w, is_stencil, is_storage_image,
disable_compression, enable_write_compression,
descriptor->plane_descriptors[descriptor_plane_id]);
}
@ -2035,7 +2035,7 @@ radv_image_view_can_fast_clear(const struct radv_device *device,
return false;
/* Only fast clear if all layers are bound. */
if (iview->base_layer > 0 || iview->layer_count != image->info.array_size)
if (iview->vk.base_array_layer > 0 || iview->vk.layer_count != image->info.array_size)
return false;
/* Only fast clear if the view covers the whole image. */
@ -2062,7 +2062,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
if (min_lod_info)
min_lod = min_lod_info->minLod;
vk_object_base_init(&device->vk, &iview->base, VK_OBJECT_TYPE_IMAGE_VIEW);
bool from_client = extra_create_info && extra_create_info->from_client;
vk_image_view_init(&device->vk, &iview->vk, !from_client, pCreateInfo);
switch (image->vk.image_type) {
case VK_IMAGE_TYPE_1D:
@ -2078,44 +2079,39 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
unreachable("bad VkImageType");
}
iview->image = image;
iview->type = pCreateInfo->viewType;
iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
iview->base_layer = range->baseArrayLayer;
iview->layer_count = radv_get_layerCount(image, range);
iview->base_mip = range->baseMipLevel;
iview->level_count = radv_get_levelCount(image, range);
iview->vk_format = pCreateInfo->format;
/* If the image has an Android external format, pCreateInfo->format will be
* VK_FORMAT_UNDEFINED. */
if (iview->vk_format == VK_FORMAT_UNDEFINED)
iview->vk_format = image->vk.format;
if (iview->vk.format == VK_FORMAT_UNDEFINED) {
iview->vk.format = image->vk.format;
iview->vk.view_format = image->vk.format;
}
/* Split out the right aspect. Note that for internal meta code we sometimes
* use an equivalent color format for the aspect so we first have to check
* if we actually got depth/stencil formats. */
if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
if (vk_format_has_stencil(iview->vk_format))
iview->vk_format = vk_format_stencil_only(iview->vk_format);
} else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
if (vk_format_has_depth(iview->vk_format))
iview->vk_format = vk_format_depth_only(iview->vk_format);
if (iview->vk.aspects == VK_IMAGE_ASPECT_STENCIL_BIT) {
if (vk_format_has_stencil(iview->vk.view_format))
iview->vk.view_format = vk_format_stencil_only(iview->vk.view_format);
} else if (iview->vk.aspects == VK_IMAGE_ASPECT_DEPTH_BIT) {
if (vk_format_has_depth(iview->vk.view_format))
iview->vk.view_format = vk_format_depth_only(iview->vk.view_format);
}
if (vk_format_get_plane_count(image->vk.format) > 1 &&
iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT) {
plane_count = vk_format_get_plane_count(iview->vk_format);
pCreateInfo->subresourceRange.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
plane_count = vk_format_get_plane_count(iview->vk.format);
}
if (device->physical_device->emulate_etc2 &&
vk_format_description(image->vk.format)->layout == UTIL_FORMAT_LAYOUT_ETC) {
const struct util_format_description *desc = vk_format_description(iview->vk_format);
const struct util_format_description *desc = vk_format_description(iview->vk.format);
assert(desc);
if (desc->layout == UTIL_FORMAT_LAYOUT_ETC) {
iview->plane_id = 1;
iview->vk_format = etc2_emulation_format(iview->vk_format);
iview->vk.format = etc2_emulation_format(iview->vk.format);
iview->vk.view_format = etc2_emulation_format(iview->vk.format);
}
plane_count = 1;
@ -2128,16 +2124,12 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
.depth = image->info.depth,
};
} else {
iview->extent = (VkExtent3D){
.width = radv_minify(image->info.width, range->baseMipLevel),
.height = radv_minify(image->info.height, range->baseMipLevel),
.depth = radv_minify(image->info.depth, range->baseMipLevel),
};
iview->extent = iview->vk.extent;
}
if (iview->vk_format != image->planes[iview->plane_id].format) {
unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
if (iview->vk.format != image->planes[iview->plane_id].format) {
unsigned view_bw = vk_format_get_blockwidth(iview->vk.format);
unsigned view_bh = vk_format_get_blockheight(iview->vk.format);
unsigned img_bw = vk_format_get_blockwidth(image->planes[iview->plane_id].format);
unsigned img_bh = vk_format_get_blockheight(image->planes[iview->plane_id].format);
@ -2171,11 +2163,11 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
* the plain converted dimensions the physical layout is correct.
*/
if (device->physical_device->rad_info.gfx_level >= GFX9 &&
vk_format_is_compressed(image->vk.format) && !vk_format_is_compressed(iview->vk_format)) {
vk_format_is_compressed(image->vk.format) && !vk_format_is_compressed(iview->vk.format)) {
/* If we have multiple levels in the view we should ideally take the last level,
* but the mip calculation has a max(..., 1) so walking back to the base mip in an
* useful way is hard. */
if (iview->level_count > 1) {
if (iview->vk.level_count > 1) {
iview->extent.width = iview->image->planes[0].surface.u.gfx9.base_mip_width;
iview->extent.height = iview->image->planes[0].surface.u.gfx9.base_mip_height;
} else {
@ -2202,7 +2194,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
bool disable_compression = extra_create_info ? extra_create_info->disable_compression : false;
bool enable_compression = extra_create_info ? extra_create_info->enable_compression : false;
for (unsigned i = 0; i < plane_count; ++i) {
VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
VkFormat format = vk_format_get_plane_format(iview->vk.view_format, i);
radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, min_lod, false,
disable_compression, enable_compression, iview->plane_id + i,
i, img_create_flags);
@ -2215,7 +2207,7 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
void
radv_image_view_finish(struct radv_image_view *iview)
{
vk_object_base_finish(&iview->base);
vk_image_view_finish(&iview->vk);
}
bool
@ -2476,7 +2468,8 @@ radv_CreateImageView(VkDevice _device, const VkImageViewCreateInfo *pCreateInfo,
if (view == NULL)
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
radv_image_view_init(view, device, pCreateInfo, image->vk.create_flags, NULL);
radv_image_view_init(view, device, pCreateInfo, image->vk.create_flags,
&(struct radv_image_view_extra_create_info){.from_client = true});
*pView = radv_image_view_to_handle(view);

16
src/amd/vulkan/radv_meta_blit.c
View file

@ -245,11 +245,11 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkSampler sampler)
{
struct radv_device *device = cmd_buffer->device;
uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip);
uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip);
uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip);
uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip);
uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip);
uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->vk.base_mip_level);
uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->vk.base_mip_level);
uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->vk.base_mip_level);
uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->vk.base_mip_level);
uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->vk.base_mip_level);
assert(src_image->info.samples == dest_image->info.samples);
@ -269,7 +269,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkRenderingAttachmentInfo color_att = {0}, depth_att = {0}, stencil_att = {0};
switch (src_iview->aspect_mask) {
switch (src_iview->vk.aspects) {
case VK_IMAGE_ASPECT_COLOR_BIT: {
unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
VkImageLayout layout = radv_meta_dst_layout_to_layout(dst_layout);
@ -354,7 +354,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
}
if (!*pipeline) {
VkResult ret = build_pipeline(device, src_iview->aspect_mask,
VkResult ret = build_pipeline(device, src_iview->vk.aspects,
translate_sampler_dim(src_image->vk.image_type),
format, pipeline);
if (ret != VK_SUCCESS) {
@ -408,7 +408,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
.layerCount = 1,
};
switch (src_iview->aspect_mask) {
switch (src_iview->image->vk.aspects) {
case VK_IMAGE_ASPECT_COLOR_BIT:
rendering_info.colorAttachmentCount = 1;
rendering_info.pColorAttachments = &color_att;

2
src/amd/vulkan/radv_meta_blit2d.c
View file

@ -238,7 +238,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
aspect_mask == VK_IMAGE_ASPECT_PLANE_0_BIT ||
aspect_mask == VK_IMAGE_ASPECT_PLANE_1_BIT ||
aspect_mask == VK_IMAGE_ASPECT_PLANE_2_BIT) {
unsigned fs_key = radv_format_meta_fs_key(device, dst_temps.iview.vk_format);
unsigned fs_key = radv_format_meta_fs_key(device, dst_temps.iview.vk.format);
if (device->meta_state.blit2d[log2_samples].pipelines[src_type][fs_key] ==
VK_NULL_HANDLE) {

60
src/amd/vulkan/radv_meta_clear.c
View file

@ -331,7 +331,7 @@ emit_color_clear(struct radv_cmd_buffer *cmd_buffer, const VkClearAttachment *cl
*/
if (iview) {
samples = iview->image->info.samples;
format = iview->vk_format;
format = iview->vk.format;
} else {
samples = cmd_buffer->state.pass->attachments[pass_att].samples;
format = cmd_buffer->state.pass->attachments[pass_att].format;
@ -528,8 +528,8 @@ depth_view_can_fast_clear(struct radv_cmd_buffer *cmd_buffer, const struct radv_
clear_value.depth != 1.0) ||
((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && clear_value.stencil != 0)))
return false;
if (radv_htile_enabled(iview->image, iview->base_mip) && iview->base_mip == 0 &&
iview->base_layer == 0 && iview->layer_count == iview->image->info.array_size &&
if (radv_htile_enabled(iview->image, iview->vk.base_mip_level) && iview->vk.base_mip_level == 0 &&
iview->vk.base_array_layer == 0 && iview->vk.layer_count == iview->image->info.array_size &&
radv_layout_is_htile_compressed(cmd_buffer->device, iview->image, layout, in_render_loop,
queue_mask) &&
radv_image_extent_compare(iview->image, &iview->extent))
@ -847,7 +847,7 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_
return false;
if (iview->image->info.levels > 1) {
uint32_t last_level = iview->base_mip + iview->level_count - 1;
uint32_t last_level = iview->vk.base_mip_level + iview->vk.level_count - 1;
if (last_level >= iview->image->planes[0].surface.num_meta_levels) {
/* Do not fast clears if one level can't be fast cleared. */
return false;
@ -880,10 +880,10 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_imag
VkImageSubresourceRange range = {
.aspectMask = aspects,
.baseMipLevel = iview->base_mip,
.levelCount = iview->level_count,
.baseArrayLayer = iview->base_layer,
.layerCount = iview->layer_count,
.baseMipLevel = iview->vk.base_mip_level,
.levelCount = iview->vk.level_count,
.baseArrayLayer = iview->vk.base_array_layer,
.layerCount = iview->vk.layer_count,
};
flush_bits = radv_clear_htile(cmd_buffer, iview->image, &range, clear_word);
@ -1562,12 +1562,12 @@ gfx8_get_fast_clear_parameters(struct radv_device *device, const struct radv_ima
*can_avoid_fast_clear_elim = false;
}
const struct util_format_description *desc = vk_format_description(iview->vk_format);
if (iview->vk_format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
iview->vk_format == VK_FORMAT_R5G6B5_UNORM_PACK16 || iview->vk_format == VK_FORMAT_B5G6R5_UNORM_PACK16)
const struct util_format_description *desc = vk_format_description(iview->vk.format);
if (iview->vk.format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
iview->vk.format == VK_FORMAT_R5G6B5_UNORM_PACK16 || iview->vk.format == VK_FORMAT_B5G6R5_UNORM_PACK16)
extra_channel = -1;
else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
if (vi_alpha_is_on_msb(device, iview->vk_format))
if (vi_alpha_is_on_msb(device, iview->vk.format))
extra_channel = desc->nr_channels - 1;
else
extra_channel = 0;
@ -1652,13 +1652,13 @@ gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_im
bool unorm_0001 = true;
bool unorm_1110 = true;
const struct util_format_description *desc = vk_format_description(iview->vk_format);
if (iview->vk_format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
iview->vk_format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
iview->vk_format == VK_FORMAT_B5G6R5_UNORM_PACK16)
const struct util_format_description *desc = vk_format_description(iview->vk.format);
if (iview->vk.format == VK_FORMAT_B10G11R11_UFLOAT_PACK32 ||
iview->vk.format == VK_FORMAT_R5G6B5_UNORM_PACK16 ||
iview->vk.format == VK_FORMAT_B5G6R5_UNORM_PACK16)
extra_channel = -1;
else if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN) {
if (vi_alpha_is_on_msb(device, iview->vk_format))
if (vi_alpha_is_on_msb(device, iview->vk.format))
extra_channel = desc->nr_channels - 1;
else
extra_channel = 0;
@ -1719,7 +1719,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_
return false;
if (!radv_layout_can_fast_clear(
cmd_buffer->device, iview->image, iview->base_mip, image_layout, in_render_loop,
cmd_buffer->device, iview->image, iview->vk.base_mip_level, image_layout, in_render_loop,
radv_image_queue_family_mask(iview->image, cmd_buffer->qf,
cmd_buffer->qf)))
return false;
@ -1738,7 +1738,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_
return false;
/* DCC */
if (!radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value))
if (!radv_format_pack_clear_color(iview->vk.format, clear_color, &clear_value))
return false;
/* Images that support comp-to-single clears don't have clear values. */
@ -1746,7 +1746,7 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_
!radv_image_has_clear_value(iview->image) && (clear_color[0] != 0 || clear_color[1] != 0))
return false;
if (radv_dcc_enabled(iview->image, iview->base_mip)) {
if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) {
bool can_avoid_fast_clear_elim;
uint32_t reset_value;
@ -1761,14 +1761,14 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_
if (iview->image->info.levels > 1) {
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
uint32_t last_level = iview->base_mip + iview->level_count - 1;
uint32_t last_level = iview->vk.base_mip_level + iview->vk.level_count - 1;
if (last_level >= iview->image->planes[0].surface.num_meta_levels) {
/* Do not fast clears if one level can't be fast cleard. */
return false;
}
} else {
for (uint32_t l = 0; l < iview->level_count; l++) {
uint32_t level = iview->base_mip + l;
for (uint32_t l = 0; l < iview->vk.level_count; l++) {
uint32_t level = iview->vk.base_mip_level + l;
struct legacy_surf_dcc_level *dcc_level =
&iview->image->planes[0].surface.u.legacy.color.dcc_level[level];
@ -1794,11 +1794,11 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_imag
uint32_t clear_color[2], flush_bits = 0;
uint32_t cmask_clear_value;
VkImageSubresourceRange range = {
.aspectMask = iview->aspect_mask,
.baseMipLevel = iview->base_mip,
.levelCount = iview->level_count,
.baseArrayLayer = iview->base_layer,
.layerCount = iview->layer_count,
.aspectMask = iview->vk.aspects,
.baseMipLevel = iview->vk.base_mip_level,
.levelCount = iview->vk.level_count,
.baseArrayLayer = iview->vk.base_array_layer,
.layerCount = iview->vk.layer_count,
};
if (pre_flush) {
@ -1810,13 +1810,13 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_imag
}
/* DCC */
radv_format_pack_clear_color(iview->vk_format, clear_color, &clear_value);
radv_format_pack_clear_color(iview->vk.format, clear_color, &clear_value);
cmask_clear_value = radv_get_cmask_fast_clear_value(iview->image);
/* clear cmask buffer */
bool need_decompress_pass = false;
if (radv_dcc_enabled(iview->image, iview->base_mip)) {
if (radv_dcc_enabled(iview->image, iview->vk.base_mip_level)) {
uint32_t reset_value;
bool can_avoid_fast_clear_elim = true;

34
src/amd/vulkan/radv_meta_resolve.c
View file

@ -496,7 +496,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
radv_CmdBeginRendering(radv_cmd_buffer_to_handle(cmd_buffer), &rendering_info);
emit_resolve(cmd_buffer, src_image, dst_image, dst_iview.vk_format,
emit_resolve(cmd_buffer, src_image, dst_image, dst_iview.vk.format,
&(VkOffset2D){
.x = dstOffset.x,
.y = dstOffset.y,
@ -603,14 +603,14 @@ radv_cmd_buffer_resolve_subpass_hw(struct radv_cmd_buffer *cmd_buffer)
uint32_t queue_mask = radv_image_queue_family_mask(dst_img, cmd_buffer->qf,
cmd_buffer->qf);
if (radv_layout_dcc_compressed(cmd_buffer->device, dst_img, dest_iview->base_mip,
if (radv_layout_dcc_compressed(cmd_buffer->device, dst_img, dest_iview->vk.base_mip_level,
dst_image_layout, false, queue_mask)) {
VkImageSubresourceRange range = {
.aspectMask = dest_iview->aspect_mask,
.baseMipLevel = dest_iview->base_mip,
.levelCount = dest_iview->level_count,
.baseArrayLayer = dest_iview->base_layer,
.layerCount = dest_iview->layer_count,
.aspectMask = dest_iview->vk.aspects,
.baseMipLevel = dest_iview->vk.base_mip_level,
.levelCount = dest_iview->vk.level_count,
.baseArrayLayer = dest_iview->vk.base_array_layer,
.layerCount = dest_iview->vk.layer_count,
};
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_img, &range, 0xffffffff);
@ -627,13 +627,13 @@ radv_cmd_buffer_resolve_subpass_hw(struct radv_cmd_buffer *cmd_buffer)
radv_cmd_buffer_set_subpass(cmd_buffer, &resolve_subpass);
VkResult ret = build_resolve_pipeline(
cmd_buffer->device, radv_format_meta_fs_key(cmd_buffer->device, dest_iview->vk_format));
cmd_buffer->device, radv_format_meta_fs_key(cmd_buffer->device, dest_iview->vk.format));
if (ret != VK_SUCCESS) {
cmd_buffer->record_result = ret;
continue;
}
emit_resolve(cmd_buffer, src_img, dst_img, dest_iview->vk_format, &(VkOffset2D){0, 0},
emit_resolve(cmd_buffer, src_img, dst_img, dest_iview->vk.format, &(VkOffset2D){0, 0},
&(VkExtent2D){fb->width, fb->height});
radv_cmd_buffer_restore_subpass(cmd_buffer, subpass);
@ -665,11 +665,11 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
/* Make sure to not clear the depth/stencil attachment after resolves. */
cmd_buffer->state.attachments[dst_att.attachment].pending_clear_aspects = 0;
radv_pick_resolve_method_images(cmd_buffer->device, src_iview->image, src_iview->vk_format,
dst_iview->image, dst_iview->base_mip, dst_att.layout,
radv_pick_resolve_method_images(cmd_buffer->device, src_iview->image, src_iview->vk.format,
dst_iview->image, dst_iview->vk.base_mip_level, dst_att.layout,
dst_att.in_render_loop, cmd_buffer, &resolve_method);
if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) &&
if ((src_iview->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE) {
if (resolve_method == RESOLVE_FRAGMENT) {
radv_depth_stencil_resolve_subpass_fs(cmd_buffer, VK_IMAGE_ASPECT_DEPTH_BIT,
@ -681,7 +681,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
}
}
if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) &&
if ((src_iview->vk.aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE) {
if (resolve_method == RESOLVE_FRAGMENT) {
radv_depth_stencil_resolve_subpass_fs(cmd_buffer, VK_IMAGE_ASPECT_STENCIL_BIT,
@ -732,8 +732,8 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image *src_img = src_iview->image;
radv_pick_resolve_method_images(cmd_buffer->device, src_img, src_iview->vk_format, dst_img,
dst_iview->base_mip, dest_att.layout,
radv_pick_resolve_method_images(cmd_buffer->device, src_img, src_iview->vk.format, dst_img,
dst_iview->vk.base_mip_level, dest_att.layout,
dest_att.in_render_loop, cmd_buffer, &resolve_method);
if (resolve_method == RESOLVE_FRAGMENT) {
@ -785,9 +785,9 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
VkImageResolve2 region = {0};
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2;
region.srcSubresource.aspectMask = src_iview->aspect_mask;
region.srcSubresource.aspectMask = src_iview->vk.aspects;
region.srcSubresource.mipLevel = 0;
region.srcSubresource.baseArrayLayer = src_iview->base_layer;
region.srcSubresource.baseArrayLayer = src_iview->vk.base_array_layer;
region.srcSubresource.layerCount = layer_count;
radv_decompress_resolve_src(cmd_buffer, src_image, src_att.layout, &region);

38
src/amd/vulkan/radv_meta_resolve_cs.c
View file

@ -496,9 +496,9 @@ radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image_
uint32_t samples_log2 = ffs(samples) - 1;
VkPipeline *pipeline;
if (vk_format_is_int(src_iview->vk_format))
if (vk_format_is_int(src_iview->vk.format))
pipeline = &state->resolve_compute.rc[samples_log2].i_pipeline;
else if (vk_format_is_srgb(src_iview->vk_format))
else if (vk_format_is_srgb(src_iview->vk.format))
pipeline = &state->resolve_compute.rc[samples_log2].srgb_pipeline;
else
pipeline = &state->resolve_compute.rc[samples_log2].pipeline;
@ -506,8 +506,8 @@ radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image_
if (!*pipeline) {
VkResult ret;
ret = create_resolve_pipeline(device, samples, vk_format_is_int(src_iview->vk_format),
vk_format_is_srgb(src_iview->vk_format), pipeline);
ret = create_resolve_pipeline(device, samples, vk_format_is_int(src_iview->vk.format),
vk_format_is_srgb(src_iview->vk.format), pipeline);
if (ret != VK_SUCCESS) {
cmd_buffer->record_result = ret;
return NULL;
@ -810,23 +810,23 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
.srcSubresource =
(VkImageSubresourceLayers){
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.mipLevel = src_iview->base_mip,
.baseArrayLayer = src_iview->base_layer,
.mipLevel = src_iview->vk.base_mip_level,
.baseArrayLayer = src_iview->vk.base_array_layer,
.layerCount = layer_count,
},
.dstSubresource =
(VkImageSubresourceLayers){
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.mipLevel = dst_iview->base_mip,
.baseArrayLayer = dst_iview->base_layer,
.mipLevel = dst_iview->vk.base_mip_level,
.baseArrayLayer = dst_iview->vk.base_array_layer,
.layerCount = layer_count,
},
.srcOffset = (VkOffset3D){0, 0, 0},
.dstOffset = (VkOffset3D){0, 0, 0},
};
radv_meta_resolve_compute_image(cmd_buffer, src_iview->image, src_iview->vk_format,
src_att.layout, dst_iview->image, dst_iview->vk_format,
radv_meta_resolve_compute_image(cmd_buffer, src_iview->image, src_iview->vk.format,
src_att.layout, dst_iview->image, dst_iview->vk.format,
dst_att.layout, &region);
}
@ -864,7 +864,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2;
region.srcSubresource.aspectMask = aspects;
region.srcSubresource.mipLevel = 0;
region.srcSubresource.baseArrayLayer = src_iview->base_layer;
region.srcSubresource.baseArrayLayer = src_iview->vk.base_array_layer;
region.srcSubresource.layerCount = layer_count;
radv_decompress_resolve_src(cmd_buffer, src_image, src_att.layout, &region);
@ -882,13 +882,13 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(src_image),
.viewType = radv_meta_get_view_type(src_image),
.format = src_iview->vk_format,
.format = src_iview->vk.format,
.subresourceRange =
{
.aspectMask = aspects,
.baseMipLevel = src_iview->base_mip,
.baseMipLevel = src_iview->vk.base_mip_level,
.levelCount = 1,
.baseArrayLayer = src_iview->base_layer,
.baseArrayLayer = src_iview->vk.base_array_layer,
.layerCount = layer_count,
},
},
@ -900,13 +900,13 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(dst_image),
.viewType = radv_meta_get_view_type(dst_image),
.format = dst_iview->vk_format,
.format = dst_iview->vk.format,
.subresourceRange =
{
.aspectMask = aspects,
.baseMipLevel = dst_iview->base_mip,
.baseMipLevel = dst_iview->vk.base_mip_level,
.levelCount = 1,
.baseArrayLayer = dst_iview->base_layer,
.baseArrayLayer = dst_iview->vk.base_array_layer,
.layerCount = layer_count,
},
},
@ -927,9 +927,9 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
if (radv_layout_is_htile_compressed(cmd_buffer->device, dst_image, layout, false, queue_mask)) {
VkImageSubresourceRange range = {0};
range.aspectMask = aspects;
range.baseMipLevel = dst_iview->base_mip;
range.baseMipLevel = dst_iview->vk.base_mip_level;
range.levelCount = 1;
range.baseArrayLayer = dst_iview->base_layer;
range.baseArrayLayer = dst_iview->vk.base_array_layer;
range.layerCount = layer_count;
uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, dst_image);

4
src/amd/vulkan/radv_meta_resolve_fs.c
View file

@ -619,7 +619,7 @@ radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image_
struct radv_image_view *dst_iview)
{
struct radv_device *device = cmd_buffer->device;
unsigned fs_key = radv_format_meta_fs_key(cmd_buffer->device, dst_iview->vk_format);
unsigned fs_key = radv_format_meta_fs_key(cmd_buffer->device, dst_iview->vk.format);
const uint32_t samples = src_iview->image->info.samples;
const uint32_t samples_log2 = ffs(samples) - 1;
VkPipeline *pipeline;
@ -997,7 +997,7 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(src_image),
.viewType = radv_meta_get_view_type(src_image),
.format = src_iview->vk_format,
.format = src_iview->vk.format,
.subresourceRange =
{
.aspectMask = aspects,

12
src/amd/vulkan/radv_private.h
View file

@ -2428,17 +2428,10 @@ union radv_descriptor {
};
struct radv_image_view {
struct vk_object_base base;
struct vk_image_view vk;
struct radv_image *image; /**< VkImageViewCreateInfo::image */
VkImageViewType type;
VkImageAspectFlags aspect_mask;
VkFormat vk_format;
unsigned plane_id;
uint32_t base_layer;
uint32_t layer_count;
uint32_t base_mip;
uint32_t level_count;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
/* Whether the image iview supports fast clear. */
@ -2495,6 +2488,7 @@ struct radv_image_view_extra_create_info {
bool disable_compression;
bool enable_compression;
bool disable_dcc_mrt;
bool from_client; /**< Set only if this came from vkCreateImage */
};
void radv_image_view_init(struct radv_image_view *view, struct radv_device *device,
@ -3019,7 +3013,7 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, base, VkDeviceMemory,
VK_OBJECT_TYPE_DEVICE_MEMORY)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_event, base, VkEvent, VK_OBJECT_TYPE_EVENT)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image, vk.base, VkImage, VK_OBJECT_TYPE_IMAGE)
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, base, VkImageView,
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, vk.base, VkImageView,
VK_OBJECT_TYPE_IMAGE_VIEW);
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, base, VkPipelineCache,
VK_OBJECT_TYPE_PIPELINE_CACHE)