mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-04 22:49:13 +02:00
pan/bi: Only rewrite COMBINE dest if not SSA
If it's already a register, there's no point in rewriting and it will
disturb the existing register, i.e. for
if (..) {
r0 = vecN ..
} else {
r0 = vecN ..
}
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
This commit is contained in:
parent
e42a5dfd4f
commit
d8c6a71878
1 changed files with 4 additions and 2 deletions
|
|
@ -197,7 +197,8 @@ bi_lower_combine(bi_context *ctx, bi_block *block)
|
|||
bi_foreach_instr_in_block_safe(block, ins) {
|
||||
if (ins->type != BI_COMBINE) continue;
|
||||
|
||||
unsigned R = bi_make_temp_reg(ctx);
|
||||
bool needs_rewrite = !(ins->dest & PAN_IS_REG);
|
||||
unsigned R = needs_rewrite ? bi_make_temp_reg(ctx) : ins->dest;
|
||||
unsigned sz = nir_alu_type_get_type_size(ins->dest_type);
|
||||
|
||||
bi_foreach_src(ins, s) {
|
||||
|
|
@ -226,8 +227,9 @@ bi_lower_combine(bi_context *ctx, bi_block *block)
|
|||
}
|
||||
}
|
||||
|
||||
if (needs_rewrite)
|
||||
bi_rewrite_uses(ctx, ins->dest, 0, R, 0);
|
||||
|
||||
bi_rewrite_uses(ctx, ins->dest, 0, R, 0);
|
||||
bi_remove_instruction(ins);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue