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i965/gen10+: Enable object level preemption.

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Set bit when initializing context.

v3:
 - Always toggle preemption bool to false before enabling it for the
 first time, so the state gets emitted (Chris Wilson).
 - Emit end of pipe sync with PIPE_CONTROL_RENDER_TARGET_FLUSH (Ken)

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Rafael Antognolli 2018-10-29 10:19:53 -07:00
parent 019a92ffa4
commit d8b50e152a
4 changed files with 36 additions and 1 deletions
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2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -844,6 +844,8 @@ struct brw_context
GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */ GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
bool object_preemption; /**< Object level preemption enabled. */
GLenum reduced_primitive; GLenum reduced_primitive;
/** /**

5
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1683,4 +1683,9 @@ enum brw_pixel_shader_coverage_mask_mode {
# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS (1 << 5) # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS (1 << 5)
# define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK REG_MASK(1 << 5) # define HEADERLESS_MESSAGE_FOR_PREEMPTABLE_CONTEXTS_MASK REG_MASK(1 << 5)
#define CS_CHICKEN1 0x2580 /* Gen9+ */
# define GEN9_REPLAY_MODE_MIDBUFFER (0 << 0)
# define GEN9_REPLAY_MODE_MIDOBJECT (1 << 0)
# define GEN9_REPLAY_MODE_MASK REG_MASK(1 << 0)
#endif #endif

3
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -128,7 +128,7 @@ void brw_disk_cache_write_compute_program(struct brw_context *brw);
void brw_disk_cache_write_render_programs(struct brw_context *brw); void brw_disk_cache_write_render_programs(struct brw_context *brw);
/*********************************************************************** /***********************************************************************
* brw_state.c * brw_state_upload.c
*/ */
void brw_upload_render_state(struct brw_context *brw); void brw_upload_render_state(struct brw_context *brw);
void brw_render_state_finished(struct brw_context *brw); void brw_render_state_finished(struct brw_context *brw);
@ -138,6 +138,7 @@ void brw_init_state(struct brw_context *brw);
void brw_destroy_state(struct brw_context *brw); void brw_destroy_state(struct brw_context *brw);
void brw_emit_select_pipeline(struct brw_context *brw, void brw_emit_select_pipeline(struct brw_context *brw,
enum brw_pipeline pipeline); enum brw_pipeline pipeline);
void brw_enable_obj_preemption(struct brw_context *brw, bool enable);
static inline void static inline void
brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline) brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)

27
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -45,6 +45,28 @@
#include "brw_cs.h" #include "brw_cs.h"
#include "main/framebuffer.h" #include "main/framebuffer.h"
void
brw_enable_obj_preemption(struct brw_context *brw, bool enable)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
assert(devinfo->gen >= 9);
if (enable == brw->object_preemption)
return;
/* A fixed function pipe flush is required before modifying this field */
brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
bool replay_mode = enable ?
GEN9_REPLAY_MODE_MIDOBJECT : GEN9_REPLAY_MODE_MIDBUFFER;
/* enable object level preemption */
brw_load_register_imm32(brw, CS_CHICKEN1,
replay_mode | GEN9_REPLAY_MODE_MASK);
brw->object_preemption = enable;
}
static void static void
brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_initial_gpu_state(struct brw_context *brw)
{ {
@ -160,6 +182,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
ADVANCE_BATCH(); ADVANCE_BATCH();
} }
} }
brw->object_preemption = false;
if (devinfo->gen >= 10)
brw_enable_obj_preemption(brw, true);
} }
static inline const struct brw_tracked_state * static inline const struct brw_tracked_state *