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retab ac_surface.h so that backports apply
This commit is contained in:
Dylan Baker
parent
50d73a42ba
commit
d894f844a9
1 changed files with 184 additions and 184 deletions
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@ -41,225 +41,225 @@ struct ac_addrlib;
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struct amdgpu_gpu_info;
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struct radeon_info;
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#define RADEON_SURF_MAX_LEVELS 15
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#define RADEON_SURF_MAX_LEVELS 15
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enum radeon_surf_mode {
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RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
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RADEON_SURF_MODE_1D = 2,
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RADEON_SURF_MODE_2D = 3,
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RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
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RADEON_SURF_MODE_1D = 2,
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RADEON_SURF_MODE_2D = 3,
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};
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/* This describes D/S/Z/R swizzle modes.
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* Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order.
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*/
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enum radeon_micro_mode {
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RADEON_MICRO_MODE_DISPLAY = 0,
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RADEON_MICRO_MODE_STANDARD = 1,
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RADEON_MICRO_MODE_DEPTH = 2,
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RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */
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RADEON_MICRO_MODE_DISPLAY = 0,
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RADEON_MICRO_MODE_STANDARD = 1,
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RADEON_MICRO_MODE_DEPTH = 2,
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RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */
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};
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/* the first 16 bits are reserved for libdrm_radeon, don't use them */
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#define RADEON_SURF_SCANOUT (1 << 16)
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#define RADEON_SURF_ZBUFFER (1 << 17)
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#define RADEON_SURF_SBUFFER (1 << 18)
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#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
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#define RADEON_SURF_SCANOUT (1 << 16)
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#define RADEON_SURF_ZBUFFER (1 << 17)
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#define RADEON_SURF_SBUFFER (1 << 18)
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#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
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/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
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#define RADEON_SURF_FMASK (1 << 21)
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#define RADEON_SURF_DISABLE_DCC (1 << 22)
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#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
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#define RADEON_SURF_IMPORTED (1 << 24)
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#define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1 << 25)
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#define RADEON_SURF_SHAREABLE (1 << 26)
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#define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
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#define RADEON_SURF_FMASK (1 << 21)
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#define RADEON_SURF_DISABLE_DCC (1 << 22)
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#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
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#define RADEON_SURF_IMPORTED (1 << 24)
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#define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1 << 25)
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#define RADEON_SURF_SHAREABLE (1 << 26)
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#define RADEON_SURF_NO_RENDER_TARGET (1 << 27)
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/* Force a swizzle mode (gfx9+) or tile mode (gfx6-8).
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* If this is not set, optimize for space. */
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#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
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#define RADEON_SURF_NO_FMASK (1 << 29)
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#define RADEON_SURF_NO_HTILE (1 << 30)
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#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1u << 31)
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#define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28)
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#define RADEON_SURF_NO_FMASK (1 << 29)
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#define RADEON_SURF_NO_HTILE (1 << 30)
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#define RADEON_SURF_FORCE_MICRO_TILE_MODE (1u << 31)
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struct legacy_surf_level {
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uint64_t offset;
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uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */
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uint32_t dcc_offset; /* relative offset within DCC mip tree */
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uint32_t dcc_fast_clear_size;
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uint32_t dcc_slice_fast_clear_size;
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unsigned nblk_x:15;
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unsigned nblk_y:15;
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enum radeon_surf_mode mode:2;
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uint64_t offset;
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uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */
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uint32_t dcc_offset; /* relative offset within DCC mip tree */
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uint32_t dcc_fast_clear_size;
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uint32_t dcc_slice_fast_clear_size;
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unsigned nblk_x:15;
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unsigned nblk_y:15;
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enum radeon_surf_mode mode:2;
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};
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struct legacy_surf_fmask {
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unsigned slice_tile_max; /* max 4M */
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uint8_t tiling_index; /* max 31 */
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uint8_t bankh; /* max 8 */
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uint16_t pitch_in_pixels;
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uint64_t slice_size;
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unsigned slice_tile_max; /* max 4M */
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uint8_t tiling_index; /* max 31 */
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uint8_t bankh; /* max 8 */
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uint16_t pitch_in_pixels;
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uint64_t slice_size;
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};
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struct legacy_surf_layout {
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unsigned bankw:4; /* max 8 */
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unsigned bankh:4; /* max 8 */
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unsigned mtilea:4; /* max 8 */
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unsigned tile_split:13; /* max 4K */
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unsigned stencil_tile_split:13; /* max 4K */
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unsigned pipe_config:5; /* max 17 */
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unsigned num_banks:5; /* max 16 */
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unsigned macro_tile_index:4; /* max 15 */
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unsigned bankw:4; /* max 8 */
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unsigned bankh:4; /* max 8 */
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unsigned mtilea:4; /* max 8 */
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unsigned tile_split:13; /* max 4K */
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unsigned stencil_tile_split:13; /* max 4K */
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unsigned pipe_config:5; /* max 17 */
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unsigned num_banks:5; /* max 16 */
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unsigned macro_tile_index:4; /* max 15 */
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/* Whether the depth miptree or stencil miptree as used by the DB are
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* adjusted from their TC compatible form to ensure depth/stencil
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* compatibility. If either is true, the corresponding plane cannot be
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* sampled from.
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*/
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unsigned depth_adjusted:1;
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unsigned stencil_adjusted:1;
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/* Whether the depth miptree or stencil miptree as used by the DB are
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* adjusted from their TC compatible form to ensure depth/stencil
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* compatibility. If either is true, the corresponding plane cannot be
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* sampled from.
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*/
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unsigned depth_adjusted:1;
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unsigned stencil_adjusted:1;
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struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS];
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struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
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uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
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uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
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struct legacy_surf_fmask fmask;
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unsigned cmask_slice_tile_max;
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struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS];
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struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
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uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
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uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
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struct legacy_surf_fmask fmask;
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unsigned cmask_slice_tile_max;
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};
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/* Same as addrlib - AddrResourceType. */
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enum gfx9_resource_type {
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RADEON_RESOURCE_1D = 0,
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RADEON_RESOURCE_2D,
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RADEON_RESOURCE_3D,
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RADEON_RESOURCE_1D = 0,
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RADEON_RESOURCE_2D,
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RADEON_RESOURCE_3D,
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};
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struct gfx9_surf_flags {
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uint16_t swizzle_mode; /* tile mode */
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uint16_t epitch; /* (pitch - 1) or (height - 1) */
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uint16_t swizzle_mode; /* tile mode */
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uint16_t epitch; /* (pitch - 1) or (height - 1) */
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};
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struct gfx9_surf_meta_flags {
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unsigned rb_aligned:1; /* optimal for RBs */
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unsigned pipe_aligned:1; /* optimal for TC */
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unsigned independent_64B_blocks:1;
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unsigned independent_128B_blocks:1;
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unsigned max_compressed_block_size:2;
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unsigned rb_aligned:1; /* optimal for RBs */
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unsigned pipe_aligned:1; /* optimal for TC */
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unsigned independent_64B_blocks:1;
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unsigned independent_128B_blocks:1;
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unsigned max_compressed_block_size:2;
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};
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struct gfx9_surf_layout {
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struct gfx9_surf_flags surf; /* color or depth surface */
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struct gfx9_surf_flags fmask; /* not added to surf_size */
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struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */
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struct gfx9_surf_flags surf; /* color or depth surface */
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struct gfx9_surf_flags fmask; /* not added to surf_size */
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struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */
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struct gfx9_surf_meta_flags dcc; /* metadata of color */
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struct gfx9_surf_meta_flags dcc; /* metadata of color */
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enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */
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uint16_t surf_pitch; /* in blocks */
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uint16_t surf_height;
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enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */
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uint16_t surf_pitch; /* in blocks */
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uint16_t surf_height;
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uint64_t surf_offset; /* 0 unless imported with an offset */
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/* The size of the 2D plane containing all mipmap levels. */
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uint64_t surf_slice_size;
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/* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
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uint32_t offset[RADEON_SURF_MAX_LEVELS];
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/* Mipmap level pitch in elements. Only valid for LINEAR. */
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uint16_t pitch[RADEON_SURF_MAX_LEVELS];
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uint64_t surf_offset; /* 0 unless imported with an offset */
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/* The size of the 2D plane containing all mipmap levels. */
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uint64_t surf_slice_size;
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/* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */
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uint32_t offset[RADEON_SURF_MAX_LEVELS];
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/* Mipmap level pitch in elements. Only valid for LINEAR. */
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uint16_t pitch[RADEON_SURF_MAX_LEVELS];
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uint64_t stencil_offset; /* separate stencil */
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uint64_t stencil_offset; /* separate stencil */
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uint8_t dcc_block_width;
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uint8_t dcc_block_height;
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uint8_t dcc_block_depth;
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uint8_t dcc_block_width;
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uint8_t dcc_block_height;
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uint8_t dcc_block_depth;
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/* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
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* The 3D engine doesn't support that layout except for chips with 1 RB.
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* All other chips must set rb_aligned=1.
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* A compute shader needs to convert from aligned DCC to unaligned.
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*/
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uint32_t display_dcc_size;
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uint32_t display_dcc_alignment;
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uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */
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bool dcc_retile_use_uint16; /* if all values fit into uint16_t */
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uint32_t dcc_retile_num_elements;
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void *dcc_retile_map;
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/* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0.
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* The 3D engine doesn't support that layout except for chips with 1 RB.
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* All other chips must set rb_aligned=1.
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* A compute shader needs to convert from aligned DCC to unaligned.
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*/
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uint32_t display_dcc_size;
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uint32_t display_dcc_alignment;
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uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */
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bool dcc_retile_use_uint16; /* if all values fit into uint16_t */
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uint32_t dcc_retile_num_elements;
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void *dcc_retile_map;
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};
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struct radeon_surf {
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/* Format properties. */
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unsigned blk_w:4;
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unsigned blk_h:4;
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unsigned bpe:5;
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/* Number of mipmap levels where DCC is enabled starting from level 0.
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* Non-zero levels may be disabled due to alignment constraints, but not
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* the first level.
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*/
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unsigned num_dcc_levels:4;
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unsigned is_linear:1;
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unsigned has_stencil:1;
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/* This might be true even if micro_tile_mode isn't displayable or rotated. */
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unsigned is_displayable:1;
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/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
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unsigned micro_tile_mode:3;
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uint32_t flags;
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/* Format properties. */
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unsigned blk_w:4;
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unsigned blk_h:4;
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unsigned bpe:5;
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/* Number of mipmap levels where DCC is enabled starting from level 0.
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* Non-zero levels may be disabled due to alignment constraints, but not
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* the first level.
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*/
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unsigned num_dcc_levels:4;
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unsigned is_linear:1;
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unsigned has_stencil:1;
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/* This might be true even if micro_tile_mode isn't displayable or rotated. */
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unsigned is_displayable:1;
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/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
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unsigned micro_tile_mode:3;
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uint32_t flags;
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/* These are return values. Some of them can be set by the caller, but
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* they will be treated as hints (e.g. bankw, bankh) and might be
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* changed by the calculator.
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*/
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/* These are return values. Some of them can be set by the caller, but
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* they will be treated as hints (e.g. bankw, bankh) and might be
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* changed by the calculator.
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*/
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/* Tile swizzle can be OR'd with low bits of the BASE_256B address.
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* The value is the same for all mipmap levels. Supported tile modes:
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* - GFX6: Only macro tiling.
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* - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
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* tail.
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*
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* Only these surfaces are allowed to set it:
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* - color (if it doesn't have to be displayable)
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* - DCC (same tile swizzle as color)
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* - FMASK
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* - CMASK if it's TC-compatible or if the gen is GFX9
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* - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
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*/
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uint8_t tile_swizzle;
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uint8_t fmask_tile_swizzle;
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/* Tile swizzle can be OR'd with low bits of the BASE_256B address.
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* The value is the same for all mipmap levels. Supported tile modes:
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* - GFX6: Only macro tiling.
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* - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip
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* tail.
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*
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* Only these surfaces are allowed to set it:
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* - color (if it doesn't have to be displayable)
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* - DCC (same tile swizzle as color)
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* - FMASK
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* - CMASK if it's TC-compatible or if the gen is GFX9
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* - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9
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*/
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uint8_t tile_swizzle;
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uint8_t fmask_tile_swizzle;
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uint64_t surf_size;
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uint64_t fmask_size;
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uint32_t surf_alignment;
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uint32_t fmask_alignment;
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uint64_t surf_size;
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uint64_t fmask_size;
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uint32_t surf_alignment;
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uint32_t fmask_alignment;
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/* DCC and HTILE are very small. */
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uint32_t dcc_size;
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uint32_t dcc_slice_size;
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uint32_t dcc_alignment;
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/* DCC and HTILE are very small. */
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uint32_t dcc_size;
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uint32_t dcc_slice_size;
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uint32_t dcc_alignment;
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uint32_t htile_size;
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uint32_t htile_slice_size;
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uint32_t htile_alignment;
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uint32_t htile_size;
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uint32_t htile_slice_size;
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uint32_t htile_alignment;
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uint32_t cmask_size;
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uint32_t cmask_slice_size;
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uint32_t cmask_alignment;
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uint32_t cmask_size;
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uint32_t cmask_slice_size;
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uint32_t cmask_alignment;
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/* All buffers combined. */
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uint64_t htile_offset;
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uint64_t fmask_offset;
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uint64_t cmask_offset;
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uint64_t dcc_offset;
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uint64_t display_dcc_offset;
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uint64_t dcc_retile_map_offset;
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uint64_t total_size;
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uint32_t alignment;
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/* All buffers combined. */
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uint64_t htile_offset;
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uint64_t fmask_offset;
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uint64_t cmask_offset;
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uint64_t dcc_offset;
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uint64_t display_dcc_offset;
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uint64_t dcc_retile_map_offset;
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uint64_t total_size;
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uint32_t alignment;
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union {
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/* Return values for GFX8 and older.
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*
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* Some of them can be set by the caller if certain parameters are
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* desirable. The allocator will try to obey them.
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*/
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struct legacy_surf_layout legacy;
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union {
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/* Return values for GFX8 and older.
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*
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* Some of them can be set by the caller if certain parameters are
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* desirable. The allocator will try to obey them.
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*/
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struct legacy_surf_layout legacy;
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/* GFX9+ return values. */
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struct gfx9_surf_layout gfx9;
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} u;
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/* GFX9+ return values. */
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struct gfx9_surf_layout gfx9;
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} u;
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};
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struct ac_surf_info {
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@ -283,38 +283,38 @@ struct ac_surf_config {
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};
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struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info,
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const struct amdgpu_gpu_info *amdinfo,
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uint64_t *max_alignment);
|
||||
const struct amdgpu_gpu_info *amdinfo,
|
||||
uint64_t *max_alignment);
|
||||
void ac_addrlib_destroy(struct ac_addrlib *addrlib);
|
||||
|
||||
int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info,
|
||||
const struct ac_surf_config * config,
|
||||
enum radeon_surf_mode mode,
|
||||
struct radeon_surf *surf);
|
||||
const struct ac_surf_config * config,
|
||||
enum radeon_surf_mode mode,
|
||||
struct radeon_surf *surf);
|
||||
void ac_surface_zero_dcc_fields(struct radeon_surf *surf);
|
||||
|
||||
void ac_surface_set_bo_metadata(const struct radeon_info *info,
|
||||
struct radeon_surf *surf, uint64_t tiling_flags,
|
||||
enum radeon_surf_mode *mode);
|
||||
struct radeon_surf *surf, uint64_t tiling_flags,
|
||||
enum radeon_surf_mode *mode);
|
||||
void ac_surface_get_bo_metadata(const struct radeon_info *info,
|
||||
struct radeon_surf *surf, uint64_t *tiling_flags);
|
||||
struct radeon_surf *surf, uint64_t *tiling_flags);
|
||||
|
||||
bool ac_surface_set_umd_metadata(const struct radeon_info *info,
|
||||
struct radeon_surf *surf,
|
||||
unsigned num_storage_samples,
|
||||
unsigned num_mipmap_levels,
|
||||
unsigned size_metadata,
|
||||
uint32_t metadata[64]);
|
||||
struct radeon_surf *surf,
|
||||
unsigned num_storage_samples,
|
||||
unsigned num_mipmap_levels,
|
||||
unsigned size_metadata,
|
||||
uint32_t metadata[64]);
|
||||
void ac_surface_get_umd_metadata(const struct radeon_info *info,
|
||||
struct radeon_surf *surf,
|
||||
unsigned num_mipmap_levels,
|
||||
uint32_t desc[8],
|
||||
unsigned *size_metadata, uint32_t metadata[64]);
|
||||
struct radeon_surf *surf,
|
||||
unsigned num_mipmap_levels,
|
||||
uint32_t desc[8],
|
||||
unsigned *size_metadata, uint32_t metadata[64]);
|
||||
|
||||
void ac_surface_override_offset_stride(const struct radeon_info *info,
|
||||
struct radeon_surf *surf,
|
||||
unsigned num_mipmap_levels,
|
||||
uint64_t offset, unsigned pitch);
|
||||
struct radeon_surf *surf,
|
||||
unsigned num_mipmap_levels,
|
||||
uint64_t offset, unsigned pitch);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue